2012-06-17 19:52:06 +00:00
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From 63fe8261cee647b1edbb92b3c271e1cc6442a0bf Mon Sep 17 00:00:00 2001
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2011-11-20 00:01:55 +00:00
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From: Frank Rowand <frank.rowand@am.sony.com>
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Date: Mon, 19 Sep 2011 14:51:14 -0700
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2012-06-17 19:52:06 +00:00
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Subject: [018/254] preempt-rt: Convert arm boot_lock to raw
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2011-11-20 00:01:55 +00:00
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The arm boot_lock is used by the secondary processor startup code. The locking
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task is the idle thread, which has idle->sched_class == &idle_sched_class.
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idle_sched_class->enqueue_task == NULL, so if the idle task blocks on the
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lock, the attempt to wake it when the lock becomes available will fail:
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try_to_wake_up()
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...
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activate_task()
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enqueue_task()
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p->sched_class->enqueue_task(rq, p, flags)
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Fix by converting boot_lock to a raw spin lock.
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Signed-off-by: Frank Rowand <frank.rowand@am.sony.com>
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Link: http://lkml.kernel.org/r/4E77B952.3010606@am.sony.com
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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---
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arch/arm/mach-exynos/platsmp.c | 12 ++++++------
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arch/arm/mach-msm/platsmp.c | 10 +++++-----
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arch/arm/mach-omap2/omap-smp.c | 10 +++++-----
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arch/arm/mach-ux500/platsmp.c | 10 +++++-----
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arch/arm/plat-versatile/platsmp.c | 10 +++++-----
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2012-06-04 21:20:09 +00:00
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5 files changed, 26 insertions(+), 26 deletions(-)
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2011-11-20 00:01:55 +00:00
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2012-06-17 19:52:06 +00:00
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diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
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index 36c3984..77499ea 100644
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--- a/arch/arm/mach-exynos/platsmp.c
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+++ b/arch/arm/mach-exynos/platsmp.c
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2012-06-04 21:20:09 +00:00
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@@ -62,7 +62,7 @@ static void __iomem *scu_base_addr(void)
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2011-11-20 00:01:55 +00:00
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return (void __iomem *)(S5P_VA_SCU);
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}
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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2012-06-04 21:20:09 +00:00
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void __cpuinit platform_secondary_init(unsigned int cpu)
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2011-11-20 00:01:55 +00:00
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{
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2012-06-17 19:52:06 +00:00
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@@ -82,8 +82,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
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2011-11-20 00:01:55 +00:00
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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2012-06-17 19:52:06 +00:00
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@@ -94,7 +94,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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2011-11-20 00:01:55 +00:00
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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2012-06-17 19:52:06 +00:00
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@@ -123,7 +123,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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2011-11-20 00:01:55 +00:00
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if (timeout == 0) {
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printk(KERN_ERR "cpu1 power enable failed");
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return -ETIMEDOUT;
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}
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}
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2012-06-17 19:52:06 +00:00
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@@ -151,7 +151,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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2011-11-20 00:01:55 +00:00
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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2012-06-17 19:52:06 +00:00
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diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
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index db0117e..87daf5f 100644
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--- a/arch/arm/mach-msm/platsmp.c
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+++ b/arch/arm/mach-msm/platsmp.c
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2012-06-04 21:20:09 +00:00
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@@ -40,7 +40,7 @@ extern void msm_secondary_startup(void);
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2011-11-20 00:01:55 +00:00
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*/
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volatile int pen_release = -1;
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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static inline int get_core_count(void)
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{
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2012-06-17 19:52:06 +00:00
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@@ -70,8 +70,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
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2011-11-20 00:01:55 +00:00
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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static __cpuinit void prepare_cold_cpu(unsigned int cpu)
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2012-06-17 19:52:06 +00:00
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@@ -108,7 +108,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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2011-11-20 00:01:55 +00:00
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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2012-06-17 19:52:06 +00:00
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@@ -142,7 +142,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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2011-11-20 00:01:55 +00:00
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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2012-06-17 19:52:06 +00:00
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diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
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index deffbf1..81ca676 100644
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--- a/arch/arm/mach-omap2/omap-smp.c
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+++ b/arch/arm/mach-omap2/omap-smp.c
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2012-06-04 21:20:09 +00:00
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@@ -34,7 +34,7 @@
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2011-11-20 00:01:55 +00:00
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/* SCU base address */
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static void __iomem *scu_base;
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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2012-06-04 21:20:09 +00:00
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void __iomem *omap4_get_scu_base(void)
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2011-11-20 00:01:55 +00:00
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{
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2012-06-17 19:52:06 +00:00
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@@ -65,8 +65,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
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2011-11-20 00:01:55 +00:00
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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2012-06-17 19:52:06 +00:00
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@@ -77,7 +77,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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2011-11-20 00:01:55 +00:00
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* Update the AuxCoreBoot0 with boot state for secondary core.
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2012-06-17 19:52:06 +00:00
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@@ -117,7 +117,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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2011-11-20 00:01:55 +00:00
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* Now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return 0;
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}
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2012-06-17 19:52:06 +00:00
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diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
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index eff5842..acc9da2 100644
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--- a/arch/arm/mach-ux500/platsmp.c
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+++ b/arch/arm/mach-ux500/platsmp.c
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2012-06-04 21:20:09 +00:00
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@@ -58,7 +58,7 @@ static void __iomem *scu_base_addr(void)
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2011-11-20 00:01:55 +00:00
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return NULL;
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}
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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void __cpuinit platform_secondary_init(unsigned int cpu)
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{
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2012-06-17 19:52:06 +00:00
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@@ -78,8 +78,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
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2011-11-20 00:01:55 +00:00
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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2012-06-17 19:52:06 +00:00
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@@ -90,7 +90,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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2011-11-20 00:01:55 +00:00
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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2012-06-17 19:52:06 +00:00
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@@ -111,7 +111,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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2011-11-20 00:01:55 +00:00
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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2012-06-17 19:52:06 +00:00
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diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c
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index 49c7db4..1f7a3d2 100644
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--- a/arch/arm/plat-versatile/platsmp.c
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+++ b/arch/arm/plat-versatile/platsmp.c
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@@ -38,7 +38,7 @@ static void __cpuinit write_pen_release(int val)
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2011-11-20 00:01:55 +00:00
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outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
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}
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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void __cpuinit platform_secondary_init(unsigned int cpu)
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{
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2012-06-17 19:52:06 +00:00
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@@ -58,8 +58,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
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2011-11-20 00:01:55 +00:00
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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2012-06-17 19:52:06 +00:00
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@@ -70,7 +70,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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2011-11-20 00:01:55 +00:00
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* This is really belt and braces; we hold unintended secondary
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2012-06-17 19:52:06 +00:00
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@@ -100,7 +100,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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2011-11-20 00:01:55 +00:00
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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