[mipsel/mips64el] Backport loongson workarounds
MIPS: Loongson: Introduce and use loongson_llsc_mb()
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@ -607,6 +607,8 @@ linux (4.19.26-1) UNRELEASED; urgency=medium
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Enable CPU_HAS_MSA, HIGHMEM, CRYPTO_CRC32_MIPS, and NR_CPUS to 16.
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Support some boston drivers: IMG_ASCII_LCD, I2C_EG20T, PCH_PHUB, MMC,
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PCIE_XILINX, RTC_DRV_M41T80, SPI_TOPCLIFF_PCH.
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* [mipsel/mips64el] Backport MIPS: Loongson: Introduce and use
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loongson_llsc_mb()
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-- Ben Hutchings <ben@decadent.org.uk> Tue, 12 Feb 2019 12:49:10 +0000
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390
debian/patches/bugfix/mips/MIPS-Loongson-Introduce-and-use-loongson_llsc_mb.patch
vendored
Normal file
390
debian/patches/bugfix/mips/MIPS-Loongson-Introduce-and-use-loongson_llsc_mb.patch
vendored
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@ -0,0 +1,390 @@
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From e02e07e3127d8aec1f4bcdfb2fc52a2d99b4859e Mon Sep 17 00:00:00 2001
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From: Huacai Chen <chenhc@lemote.com>
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Date: Tue, 15 Jan 2019 16:04:54 +0800
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Subject: MIPS: Loongson: Introduce and use loongson_llsc_mb()
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On the Loongson-2G/2H/3A/3B there is a hardware flaw that ll/sc and
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lld/scd is very weak ordering. We should add sync instructions "before
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each ll/lld" and "at the branch-target between ll/sc" to workaround.
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Otherwise, this flaw will cause deadlock occasionally (e.g. when doing
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heavy load test with LTP).
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Below is the explaination of CPU designer:
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"For Loongson 3 family, when a memory access instruction (load, store,
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or prefetch)'s executing occurs between the execution of LL and SC, the
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success or failure of SC is not predictable. Although programmer would
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not insert memory access instructions between LL and SC, the memory
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instructions before LL in program-order, may dynamically executed
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between the execution of LL/SC, so a memory fence (SYNC) is needed
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before LL/LLD to avoid this situation.
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Since Loongson-3A R2 (3A2000), we have improved our hardware design to
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handle this case. But we later deduce a rarely circumstance that some
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speculatively executed memory instructions due to branch misprediction
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between LL/SC still fall into the above case, so a memory fence (SYNC)
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at branch-target (if its target is not between LL/SC) is needed for
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Loongson 3A1000, 3B1500, 3A2000 and 3A3000.
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Our processor is continually evolving and we aim to to remove all these
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workaround-SYNCs around LL/SC for new-come processor."
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Here is an example:
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Both cpu1 and cpu2 simutaneously run atomic_add by 1 on same atomic var,
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this bug cause both 'sc' run by two cpus (in atomic_add) succeed at same
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time('sc' return 1), and the variable is only *added by 1*, sometimes,
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which is wrong and unacceptable(it should be added by 2).
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Why disable fix-loongson3-llsc in compiler?
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Because compiler fix will cause problems in kernel's __ex_table section.
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This patch fix all the cases in kernel, but:
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+. the fix at the end of futex_atomic_cmpxchg_inatomic is for branch-target
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of 'bne', there other cases which smp_mb__before_llsc() and smp_llsc_mb() fix
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the ll and branch-target coincidently such as atomic_sub_if_positive/
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cmpxchg/xchg, just like this one.
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+. Loongson 3 does support CONFIG_EDAC_ATOMIC_SCRUB, so no need to touch
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edac.h
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+. local_ops and cmpxchg_local should not be affected by this bug since
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only the owner can write.
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+. mips_atomic_set for syscall.c is deprecated and rarely used, just let
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it go
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Signed-off-by: Huacai Chen <chenhc@lemote.com>
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Signed-off-by: Huang Pei <huangpei@loongson.cn>
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[paul.burton@mips.com:
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- Simplify the addition of -mno-fix-loongson3-llsc to cflags, and add
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a comment describing why it's there.
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- Make loongson_llsc_mb() a no-op when
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CONFIG_CPU_LOONGSON3_WORKAROUNDS=n, rather than a compiler memory
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barrier.
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- Add a comment describing the bug & how loongson_llsc_mb() helps
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in asm/barrier.h.]
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Signed-off-by: Paul Burton <paul.burton@mips.com>
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Cc: Ralf Baechle <ralf@linux-mips.org>
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Cc: ambrosehua@gmail.com
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Cc: Steven J . Hill <Steven.Hill@cavium.com>
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Cc: linux-mips@linux-mips.org
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Cc: Fuxin Zhang <zhangfx@lemote.com>
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Cc: Zhangjin Wu <wuzhangjin@gmail.com>
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Cc: Li Xuefeng <lixuefeng@loongson.cn>
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Cc: Xu Chenghua <xuchenghua@loongson.cn>
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---
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arch/mips/Kconfig | 15 +++++++++++++++
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arch/mips/include/asm/atomic.h | 6 ++++++
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arch/mips/include/asm/barrier.h | 36 ++++++++++++++++++++++++++++++++++++
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arch/mips/include/asm/bitops.h | 5 +++++
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arch/mips/include/asm/futex.h | 3 +++
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arch/mips/include/asm/pgtable.h | 2 ++
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arch/mips/loongson64/Platform | 23 +++++++++++++++++++++++
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arch/mips/mm/tlbex.c | 10 ++++++++++
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8 files changed, 100 insertions(+)
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diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
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index 0d14f51..a84c24d 100644
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--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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@@ -1403,6 +1403,21 @@ config LOONGSON3_ENHANCEMENT
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please say 'N' here. If you want a high-performance kernel to run on
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new Loongson 3 machines only, please say 'Y' here.
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+config CPU_LOONGSON3_WORKAROUNDS
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+ bool "Old Loongson 3 LLSC Workarounds"
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+ default y if SMP
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+ depends on CPU_LOONGSON3
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+ help
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+ Loongson 3 processors have the llsc issues which require workarounds.
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+ Without workarounds the system may hang unexpectedly.
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+
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+ Newer Loongson 3 will fix these issues and no workarounds are needed.
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+ The workarounds have no significant side effect on them but may
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+ decrease the performance of the system so this option should be
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+ disabled unless the kernel is intended to be run on old systems.
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+
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+ If unsure, please say Y.
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+
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config CPU_LOONGSON2E
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bool "Loongson 2E"
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depends on SYS_HAS_CPU_LOONGSON2E
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diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
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index 43fcd35..9409629 100644
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--- a/arch/mips/include/asm/atomic.h
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+++ b/arch/mips/include/asm/atomic.h
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@@ -58,6 +58,7 @@ static __inline__ void atomic_##op(int i, atomic_t * v) \
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if (kernel_uses_llsc) { \
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int temp; \
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\
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+ loongson_llsc_mb(); \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set "MIPS_ISA_LEVEL" \n" \
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@@ -85,6 +86,7 @@ static __inline__ int atomic_##op##_return_relaxed(int i, atomic_t * v) \
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if (kernel_uses_llsc) { \
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int temp; \
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\
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+ loongson_llsc_mb(); \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set "MIPS_ISA_LEVEL" \n" \
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@@ -118,6 +120,7 @@ static __inline__ int atomic_fetch_##op##_relaxed(int i, atomic_t * v) \
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if (kernel_uses_llsc) { \
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int temp; \
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\
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+ loongson_llsc_mb(); \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set "MIPS_ISA_LEVEL" \n" \
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@@ -256,6 +259,7 @@ static __inline__ void atomic64_##op(long i, atomic64_t * v) \
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if (kernel_uses_llsc) { \
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long temp; \
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\
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+ loongson_llsc_mb(); \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set "MIPS_ISA_LEVEL" \n" \
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@@ -283,6 +287,7 @@ static __inline__ long atomic64_##op##_return_relaxed(long i, atomic64_t * v) \
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if (kernel_uses_llsc) { \
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long temp; \
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\
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+ loongson_llsc_mb(); \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set "MIPS_ISA_LEVEL" \n" \
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@@ -316,6 +321,7 @@ static __inline__ long atomic64_fetch_##op##_relaxed(long i, atomic64_t * v) \
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if (kernel_uses_llsc) { \
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long temp; \
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\
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+ loongson_llsc_mb(); \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set "MIPS_ISA_LEVEL" \n" \
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diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h
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index a5eb1bb..b7f6ac5 100644
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--- a/arch/mips/include/asm/barrier.h
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+++ b/arch/mips/include/asm/barrier.h
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@@ -222,6 +222,42 @@
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#define __smp_mb__before_atomic() __smp_mb__before_llsc()
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#define __smp_mb__after_atomic() smp_llsc_mb()
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+/*
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+ * Some Loongson 3 CPUs have a bug wherein execution of a memory access (load,
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+ * store or pref) in between an ll & sc can cause the sc instruction to
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+ * erroneously succeed, breaking atomicity. Whilst it's unusual to write code
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+ * containing such sequences, this bug bites harder than we might otherwise
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+ * expect due to reordering & speculation:
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+ *
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+ * 1) A memory access appearing prior to the ll in program order may actually
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+ * be executed after the ll - this is the reordering case.
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+ *
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+ * In order to avoid this we need to place a memory barrier (ie. a sync
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+ * instruction) prior to every ll instruction, in between it & any earlier
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+ * memory access instructions. Many of these cases are already covered by
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+ * smp_mb__before_llsc() but for the remaining cases, typically ones in
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+ * which multiple CPUs may operate on a memory location but ordering is not
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+ * usually guaranteed, we use loongson_llsc_mb() below.
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+ *
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+ * This reordering case is fixed by 3A R2 CPUs, ie. 3A2000 models and later.
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+ *
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+ * 2) If a conditional branch exists between an ll & sc with a target outside
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+ * of the ll-sc loop, for example an exit upon value mismatch in cmpxchg()
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+ * or similar, then misprediction of the branch may allow speculative
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+ * execution of memory accesses from outside of the ll-sc loop.
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+ *
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+ * In order to avoid this we need a memory barrier (ie. a sync instruction)
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+ * at each affected branch target, for which we also use loongson_llsc_mb()
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+ * defined below.
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+ *
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+ * This case affects all current Loongson 3 CPUs.
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+ */
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+#ifdef CONFIG_CPU_LOONGSON3_WORKAROUNDS /* Loongson-3's LLSC workaround */
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+#define loongson_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
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+#else
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+#define loongson_llsc_mb() do { } while (0)
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+#endif
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+
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#include <asm-generic/barrier.h>
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#endif /* __ASM_BARRIER_H */
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diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
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index c467595..830c93a 100644
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--- a/arch/mips/include/asm/bitops.h
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+++ b/arch/mips/include/asm/bitops.h
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@@ -69,6 +69,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
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: "ir" (1UL << bit), GCC_OFF_SMALL_ASM() (*m));
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#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
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} else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
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+ loongson_llsc_mb();
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do {
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__asm__ __volatile__(
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" " __LL "%0, %1 # set_bit \n"
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@@ -79,6 +80,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
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} while (unlikely(!temp));
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#endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */
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} else if (kernel_uses_llsc) {
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+ loongson_llsc_mb();
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do {
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__asm__ __volatile__(
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" .set push \n"
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@@ -123,6 +125,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
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: "ir" (~(1UL << bit)));
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#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
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} else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
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+ loongson_llsc_mb();
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do {
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__asm__ __volatile__(
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" " __LL "%0, %1 # clear_bit \n"
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@@ -133,6 +136,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
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} while (unlikely(!temp));
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#endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */
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} else if (kernel_uses_llsc) {
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+ loongson_llsc_mb();
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do {
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__asm__ __volatile__(
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" .set push \n"
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@@ -193,6 +197,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp;
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+ loongson_llsc_mb();
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do {
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__asm__ __volatile__(
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" .set push \n"
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diff --git a/arch/mips/include/asm/futex.h b/arch/mips/include/asm/futex.h
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index c14d798..b83b039 100644
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--- a/arch/mips/include/asm/futex.h
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+++ b/arch/mips/include/asm/futex.h
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@@ -50,6 +50,7 @@
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"i" (-EFAULT) \
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: "memory"); \
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} else if (cpu_has_llsc) { \
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+ loongson_llsc_mb(); \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noat \n" \
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@@ -163,6 +164,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
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"i" (-EFAULT)
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: "memory");
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} else if (cpu_has_llsc) {
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+ loongson_llsc_mb();
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__asm__ __volatile__(
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"# futex_atomic_cmpxchg_inatomic \n"
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" .set push \n"
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@@ -192,6 +194,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
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: GCC_OFF_SMALL_ASM() (*uaddr), "Jr" (oldval), "Jr" (newval),
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"i" (-EFAULT)
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: "memory");
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+ loongson_llsc_mb();
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} else
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return -ENOSYS;
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diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
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index 57933fc..910851c 100644
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--- a/arch/mips/include/asm/pgtable.h
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+++ b/arch/mips/include/asm/pgtable.h
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@@ -228,6 +228,7 @@ static inline void set_pte(pte_t *ptep, pte_t pteval)
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: [buddy] "+m" (buddy->pte), [tmp] "=&r" (tmp)
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: [global] "r" (page_global));
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} else if (kernel_uses_llsc) {
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+ loongson_llsc_mb();
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__asm__ __volatile__ (
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" .set push \n"
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" .set "MIPS_ISA_ARCH_LEVEL" \n"
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@@ -242,6 +243,7 @@ static inline void set_pte(pte_t *ptep, pte_t pteval)
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" .set pop \n"
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: [buddy] "+m" (buddy->pte), [tmp] "=&r" (tmp)
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: [global] "r" (page_global));
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+ loongson_llsc_mb();
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}
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#else /* !CONFIG_SMP */
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if (pte_none(*buddy))
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diff --git a/arch/mips/loongson64/Platform b/arch/mips/loongson64/Platform
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index 0fce460..c1a4d4d 100644
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--- a/arch/mips/loongson64/Platform
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+++ b/arch/mips/loongson64/Platform
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@@ -23,6 +23,29 @@ ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS
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endif
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cflags-$(CONFIG_CPU_LOONGSON3) += -Wa,--trap
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+
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+#
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+# Some versions of binutils, not currently mainline as of 2019/02/04, support
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+# an -mfix-loongson3-llsc flag which emits a sync prior to each ll instruction
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+# to work around a CPU bug (see loongson_llsc_mb() in asm/barrier.h for a
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+# description).
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+#
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+# We disable this in order to prevent the assembler meddling with the
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+# instruction that labels refer to, ie. if we label an ll instruction:
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+#
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+# 1: ll v0, 0(a0)
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+#
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+# ...then with the assembler fix applied the label may actually point at a sync
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+# instruction inserted by the assembler, and if we were using the label in an
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+# exception table the table would no longer contain the address of the ll
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+# instruction.
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+#
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+# Avoid this by explicitly disabling that assembler behaviour. If upstream
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+# binutils does not merge support for the flag then we can revisit & remove
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+# this later - for now it ensures vendor toolchains don't cause problems.
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+#
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+cflags-$(CONFIG_CPU_LOONGSON3) += $(call as-option,-Wa$(comma)-mno-fix-loongson3-llsc,)
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+
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#
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# binutils from v2.25 on and gcc starting from v4.9.0 treat -march=loongson3a
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# as MIPS64 R2; older versions as just R1. This leaves the possibility open
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diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
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index 37b1cb2..65b6e85 100644
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--- a/arch/mips/mm/tlbex.c
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+++ b/arch/mips/mm/tlbex.c
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@@ -932,6 +932,8 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
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* to mimic that here by taking a load/istream page
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* fault.
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*/
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+ if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
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+ uasm_i_sync(p, 0);
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UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0);
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uasm_i_jr(p, ptr);
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@@ -1646,6 +1648,8 @@ static void
|
||||
iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
|
||||
{
|
||||
#ifdef CONFIG_SMP
|
||||
+ if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
|
||||
+ uasm_i_sync(p, 0);
|
||||
# ifdef CONFIG_PHYS_ADDR_T_64BIT
|
||||
if (cpu_has_64bits)
|
||||
uasm_i_lld(p, pte, 0, ptr);
|
||||
@@ -2259,6 +2263,8 @@ static void build_r4000_tlb_load_handler(void)
|
||||
#endif
|
||||
|
||||
uasm_l_nopage_tlbl(&l, p);
|
||||
+ if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
|
||||
+ uasm_i_sync(&p, 0);
|
||||
build_restore_work_registers(&p);
|
||||
#ifdef CONFIG_CPU_MICROMIPS
|
||||
if ((unsigned long)tlb_do_page_fault_0 & 1) {
|
||||
@@ -2313,6 +2319,8 @@ static void build_r4000_tlb_store_handler(void)
|
||||
#endif
|
||||
|
||||
uasm_l_nopage_tlbs(&l, p);
|
||||
+ if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
|
||||
+ uasm_i_sync(&p, 0);
|
||||
build_restore_work_registers(&p);
|
||||
#ifdef CONFIG_CPU_MICROMIPS
|
||||
if ((unsigned long)tlb_do_page_fault_1 & 1) {
|
||||
@@ -2368,6 +2376,8 @@ static void build_r4000_tlb_modify_handler(void)
|
||||
#endif
|
||||
|
||||
uasm_l_nopage_tlbm(&l, p);
|
||||
+ if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS))
|
||||
+ uasm_i_sync(&p, 0);
|
||||
build_restore_work_registers(&p);
|
||||
#ifdef CONFIG_CPU_MICROMIPS
|
||||
if ((unsigned long)tlb_do_page_fault_1 & 1) {
|
||||
--
|
||||
cgit v1.1
|
||||
|
|
@ -82,6 +82,7 @@ bugfix/m68k/m68k-build-with-ffreestanding.patch
|
|||
bugfix/x86/x86-kvmclock-set-offset-for-kvm-unstable-clock.patch
|
||||
bugfix/arm/ARM-dts-sun8i-h3-add-sy8106a-to-orange-pi-plus.patch
|
||||
bugfix/arm64/arm64-dts-allwinner-a64-Enable-A64-timer-workaround.patch
|
||||
bugfix/mips/MIPS-Loongson-Introduce-and-use-loongson_llsc_mb.patch
|
||||
|
||||
# Arch features
|
||||
features/mips/MIPS-increase-MAX-PHYSMEM-BITS-on-Loongson-3-only.patch
|
||||
|
|
Loading…
Reference in New Issue