From 28817f7dbdd7ab292387c6018f859100d680dabb Mon Sep 17 00:00:00 2001 From: Ben Hutchings Date: Tue, 4 May 2010 02:55:51 +0000 Subject: [PATCH] Merge /dists/sid/linux-2.6 (2.6.32-12). svn path=/dists/trunk/linux-2.6/; revision=15620 --- debian/changelog | 86 + debian/config/config | 3 +- debian/config/ia64/config | 2 +- debian/config/mips/config.sb1-bcm91250a | 1 + debian/config/sh4/config.sh7751r | 266 + debian/config/sh4/defines | 8 + debian/linux-base.postinst | 80 +- .../block-blk_abort_request-lock-fix.patch | 84 + .../all/cifs-allow-null-nd-on-create.patch | 127 + ...less-p54-txrx.c-Fix-off-by-one-error.patch | 31 + ...ying-to-use-ACPI-lid-status-to-deter.patch | 100 + ...on-kms-further-spread-spectrum-fixes.patch | 97 + ...rd-operation-before-releasing-blocks.patch | 62 + .../forcedeth-fix-tx-limit2-flag-check.patch | 35 + ..._futex_key-when-backed-by-huge-pages.patch | 78 + ...tial-null-dereferences-on-error-path.patch | 73 + .../libata-ata_piix-clear-spurious-IRQ.patch | 148 + ...ibata-fix-accesses-at-LBA28-boundary.patch | 35 + ...-regression-fix-header-digest-errors.patch | 49 + ...54pci-fix-bugs-in-p54p_check_tx_ring.patch | 106 + .../bugfix/all/p54pci-fix-regression.patch | 164 + .../p54pci-fix-serious-sparse-warning.patch | 103 + .../p54pci-move-tx-cleanup-into-tasklet.patch | 180 + .../all/p54pci-prevent-stuck-rx-ring.patch | 188 + .../bugfix/all/p54pci-revise-tx-locking.patch | 100 + ...usb-Add-usbid-for-Corega-CG-WLUSB2GT.patch | 27 + ...-fix-typo-in-bcm6xx-PHY-driver-table.patch | 17 + ...rfs-fix-permissions-on-reiserfs_priv.patch | 79 + ...tatus-channel-before-control-channel.patch | 62 + ...om-multiple-invalid-parameter-errors.patch | 218 + .../bugfix/all/thinkpad-acpi-add-x100e.patch | 16 + ...end-prior-to-entering-networked-mode.patch | 209 + .../bugfix/mips/drm-ttm-build-fix.patch | 25 + .../bugfix/mips/enable-pata-platform.patch | 36 + ...ly-skip-PAGE_USER-test-for-Fsl-booke.patch | 44 + ...Disable-MSI-for-MCP55-on-P5N32-E-SLI.patch | 42 + .../features/all/drm-radeon-evergreen.patch | 11729 ++++++++++++++++ debian/patches/features/all/ipheth-add.patch | 638 + ...le-table-to-all-existing-phy-drivers.patch | 266 + ...hylib-Support-phy-module-autoloading.patch | 53 + .../arm/dns323-rev-a1-gpio-request.patch | 31 + debian/patches/series/base | 35 + debian/templates/control.main.in | 3 +- debian/templates/temp.image.plain/postrm | 1 + 44 files changed, 15717 insertions(+), 20 deletions(-) create mode 100644 debian/config/sh4/config.sh7751r create mode 100644 debian/patches/bugfix/all/block-blk_abort_request-lock-fix.patch create mode 100644 debian/patches/bugfix/all/cifs-allow-null-nd-on-create.patch create mode 100644 debian/patches/bugfix/all/drivers-net-wireless-p54-txrx.c-Fix-off-by-one-error.patch create mode 100644 debian/patches/bugfix/all/drm-i915-Stop-trying-to-use-ACPI-lid-status-to-deter.patch create mode 100644 debian/patches/bugfix/all/drm-radeon-kms-further-spread-spectrum-fixes.patch create mode 100644 debian/patches/bugfix/all/ext4-issue-discard-operation-before-releasing-blocks.patch create mode 100644 debian/patches/bugfix/all/forcedeth-fix-tx-limit2-flag-check.patch create mode 100644 debian/patches/bugfix/all/hugetlb-fix-infinite-loop-in-get_futex_key-when-backed-by-huge-pages.patch create mode 100644 debian/patches/bugfix/all/ipheth-potential-null-dereferences-on-error-path.patch create mode 100644 debian/patches/bugfix/all/libata-ata_piix-clear-spurious-IRQ.patch create mode 100644 debian/patches/bugfix/all/libata-fix-accesses-at-LBA28-boundary.patch create mode 100644 debian/patches/bugfix/all/libiscsi-regression-fix-header-digest-errors.patch create mode 100644 debian/patches/bugfix/all/p54pci-fix-bugs-in-p54p_check_tx_ring.patch create mode 100644 debian/patches/bugfix/all/p54pci-fix-regression.patch create mode 100644 debian/patches/bugfix/all/p54pci-fix-serious-sparse-warning.patch create mode 100644 debian/patches/bugfix/all/p54pci-move-tx-cleanup-into-tasklet.patch create mode 100644 debian/patches/bugfix/all/p54pci-prevent-stuck-rx-ring.patch create mode 100644 debian/patches/bugfix/all/p54pci-revise-tx-locking.patch create mode 100644 debian/patches/bugfix/all/p54usb-Add-usbid-for-Corega-CG-WLUSB2GT.patch create mode 100644 debian/patches/bugfix/all/phylib-fix-typo-in-bcm6xx-PHY-driver-table.patch create mode 100644 debian/patches/bugfix/all/reiserfs-fix-permissions-on-reiserfs_priv.patch create mode 100644 debian/patches/bugfix/all/rndis_host-Poll-status-channel-before-control-channel.patch create mode 100644 debian/patches/bugfix/all/sctp-fix-skb_over_panic-resulting-from-multiple-invalid-parameter-errors.patch create mode 100644 debian/patches/bugfix/all/thinkpad-acpi-add-x100e.patch create mode 100644 debian/patches/bugfix/all/tipc-fix-oops-on-send-prior-to-entering-networked-mode.patch create mode 100644 debian/patches/bugfix/mips/drm-ttm-build-fix.patch create mode 100644 debian/patches/bugfix/mips/enable-pata-platform.patch create mode 100644 debian/patches/bugfix/powerpc/kgdb-dont-needlessly-skip-PAGE_USER-test-for-Fsl-booke.patch create mode 100644 debian/patches/bugfix/x86/PCI-Disable-MSI-for-MCP55-on-P5N32-E-SLI.patch create mode 100644 debian/patches/features/all/drm-radeon-evergreen.patch create mode 100644 debian/patches/features/all/ipheth-add.patch create mode 100644 debian/patches/features/all/phylib-Add-module-table-to-all-existing-phy-drivers.patch create mode 100644 debian/patches/features/all/phylib-Support-phy-module-autoloading.patch create mode 100644 debian/patches/features/arm/dns323-rev-a1-gpio-request.patch diff --git a/debian/changelog b/debian/changelog index e1f0601d4..71508996a 100644 --- a/debian/changelog +++ b/debian/changelog @@ -108,6 +108,92 @@ linux-2.6 (2.6.33-1~experimental.1) experimental; urgency=low -- maximilian attems Thu, 25 Feb 2010 15:21:38 +0100 +linux-2.6 (2.6.32-12) unstable; urgency=low + + * The "Microwave Background" release + + [ Ben Hutchings ] + * Prepare debconf templates for translation. (closes: #576758) + * [x86] PCI/forcedeth: Disable MSI for MCP55 on P5N32-E SLI + (Closes: #552299) + * phylib: Fix typo in bcm63xx PHY driver table + * linux-base: Fix bugs and improve libata transition code: + - Fix scope of _system() function (Closes: #576925) + - Fix case where a file may wrongly be listed as automatically converted + (Closes: #577047) + - Check device IDs in mdadm.conf rather than assuming it needs manual + conversion + - Use vol_id if available since the version of blkid in lenny does not + support the output format we need (Closes: #576608) + - Fix missing line breaks in updated crypttab (Closes: #577735) + * i915: Stop trying to use ACPI lid status to determine LVDS connection + (Closes: #577724) + * forcedeth: Fix hardware version check for TX bug workaround + (Closes: #572201) + * rndis_host: Poll status channel before control channel (Closes: #576929) + * megaraid_sas: Fix copying of sense data for 32-bit management tools on + 64-bit kernel (Closes: #578398) + * Add ipheth driver for iPhone tethering + * virtio_net: Make delayed refill more reliable (Closes: #576838) + + [ maximilian attems] + * [ia64] Built in fbcon. + * Update openvz patch to c05f95fcb04e. (closes: #574598) + * Reenable nouveau autoloading. + * reiserfs: Fix permissions on .reiserfs_priv. CVE-2010-1146 + * libata,ata_piix: detect and clear spurious IRQs. + * libata/SCSI: fix locking around blk_abort_request(). + * topconfig enable NET_DROP_MONITOR. (closes: #578568) + * Add stable 2.6.32.12: + - ACPI: EC: Allow multibyte access to EC; fixes temperature monitoring + on some Dell laptops (Closes: #563313) + - [x86] KVM: disable paravirt mmu reporting (Closes: #573071) + - thinkpad-acpi: lock down video output state access (Closes: #565790) + - xfs update (closes: #579410) + * Add drm changes from stable 2.6.33.3: + - drm/radeon: R300 AD only has one quad pipe (Closes: #575681) + * libata: Fix accesses at LBA28 boundary (old bug, but nasty) (v2) + * Add EC path for Thinkpad X100. + * Bump ABI to 5, apply: + - hrtimer: Tune hrtimer_interrupt hang logic + * Add libata TRIM support. + * Backport radeon r800 modesetting support. + * drm/radeon/kms: further spread spectrum fixes. + * Backport p54 fixes. + * net: export device speed and duplex via sysfs. + * postrm: rm modules.softdep. (closes: #579175) + * Backport KVM: Xen PV-on-HVM guest support. + * Backport KVM: x86: Add KVM_GET/SET_VCPU_EVENTS. + * hugetlb: fix infinite loop in get_futex_key() when backed by huge pages + * ext4: Issue the discard operation *before* releasing the blocks to be + reused. + * libiscsi: regression: fix header digest errors. + * Revert module.c and module.h changes from -stable update. + + [ dann frazier ] + * Add DRBD backport + * sctp: Fix skb_over_panic resulting from multiple invalid parameter + errors (CVE-2010-1173) + * [CIFS] Allow null nd (as nfs server uses) on create (CVE-2010-1148) + * tipc: Fix oops on send prior to entering networked mode (CVE-2010-1187) + * [powerpc] KGDB: don't needlessly skip PAGE_USER test for Fsl booke + Note: KGDB is not currently enabled in debian builds (CVE-2010-1446) + + [ Aurelien Jarno ] + * [sh4] Add a sh7751r flavour. + * [mips/*malta] Remove options that are present in topconfig. + + [ Martin Michlmayr ] + * dns323-setup.c: fix WARN() when booting (Arnaud Patard). + * mips: enable PATA platform on SWARM and LITTLESUR (Sebastian Andrzej + Siewior). + * [mips/sb1-bcm91250a] Enable PATA_PLATFORM. + + [ Bastian Blank ] + * Update Xen patch. + + -- Ben Hutchings Sat, 01 May 2010 02:58:31 +0100 + linux-2.6 (2.6.32-11) unstable; urgency=low [ Ben Hutchings ] diff --git a/debian/config/config b/debian/config/config index 23a6d58a6..24b3f56c0 100644 --- a/debian/config/config +++ b/debian/config/config @@ -1648,6 +1648,7 @@ CONFIG_USB_NET_ZAURUS=m CONFIG_USB_HSO=m CONFIG_USB_NET_INT51X1=m CONFIG_USB_CDC_PHONET=m +CONFIG_USB_IPHETH=m ## ## file: drivers/net/wan/Kconfig @@ -3417,7 +3418,7 @@ CONFIG_NETFILTER=y CONFIG_NETFILTER_ADVANCED=y CONFIG_BRIDGE_NETFILTER=y CONFIG_NET_PKTGEN=m -# CONFIG_NET_DROP_MONITOR is not set +CONFIG_NET_DROP_MONITOR=y CONFIG_WIRELESS=y ## diff --git a/debian/config/ia64/config b/debian/config/ia64/config index d64c6a684..f1b551f7d 100644 --- a/debian/config/ia64/config +++ b/debian/config/ia64/config @@ -700,7 +700,7 @@ CONFIG_FB_TRIDENT=m ## file: drivers/video/console/Kconfig ## CONFIG_VGA_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=m +CONFIG_FRAMEBUFFER_CONSOLE=y # CONFIG_FONTS is not set CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y diff --git a/debian/config/mips/config.sb1-bcm91250a b/debian/config/mips/config.sb1-bcm91250a index 1735e55bf..1a7335c7f 100644 --- a/debian/config/mips/config.sb1-bcm91250a +++ b/debian/config/mips/config.sb1-bcm91250a @@ -136,6 +136,7 @@ CONFIG_SATA_SIS=m CONFIG_SATA_ULI=m CONFIG_SATA_VIA=m CONFIG_SATA_VITESSE=m +CONFIG_PATA_PLATFORM=y ## ## file: drivers/block/Kconfig diff --git a/debian/config/sh4/config.sh7751r b/debian/config/sh4/config.sh7751r new file mode 100644 index 000000000..7aa1b73dd --- /dev/null +++ b/debian/config/sh4/config.sh7751r @@ -0,0 +1,266 @@ +# +# System type +# +CONFIG_CPU_SUBTYPE_SH7751R=y + +# +# Memory management options +# +CONFIG_QUICKLIST=y +CONFIG_MMU=y +CONFIG_PAGE_OFFSET=0x80000000 +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_MEMORY_START=0x0c000000 +CONFIG_MEMORY_SIZE=0x04000000 +CONFIG_29BIT=y +CONFIG_VSYSCALL=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_MAX_ACTIVE_REGIONS=1 +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_PAGE_SIZE_4KB=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_SPARSEMEM_STATIC=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_NR_QUICK=2 +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y + +# +# Processor features +# +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SH_FPU=y +CONFIG_CPU_HAS_INTEVT=y +CONFIG_CPU_HAS_SR_RB=y +CONFIG_CPU_HAS_FPU=y + +# +# Board support +# +CONFIG_SH_RTS7751R2D=y + +# +# RTS7751R2D Board Revision +# +CONFIG_RTS7751R2D_PLUS=y +CONFIG_RTS7751R2D_1=y + +# +# Timer and clock configuration +# +CONFIG_SH_TIMER_TMU=y +CONFIG_SH_PCLK_FREQ=60000000 +CONFIG_SH_CLK_CPG=y +CONFIG_SH_CLK_CPG_LEGACY=y +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y + +# +# Boot options +# +CONFIG_ZERO_PAGE_OFFSET=0x00010000 +CONFIG_BOOT_LINK_OFFSET=0x009e0000 +CONFIG_ENTRY_OFFSET=0x00001000 + +# +# Bus options +# +CONFIG_PCI=y +CONFIG_SH_PCIDMA_NONCOHERENT=y + +# +# Generic Driver Options +# +CONFIG_MTD=y +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_UTIL=y + +# +# Mapping drivers for chip access +# +CONFIG_MTD_PHYSMAP=y + +# +# UBI - Unsorted block images +# +CONFIG_HAVE_IDE=y + +# +# SCSI device support +# +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y + +# +# SCSI Transports +# +CONFIG_ATA=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_SATA_PMP=y +CONFIG_ATA_SFF=y +CONFIG_PATA_PLATFORM=y + +# net device + +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_ETHERNET=y +CONFIG_NET_PCI=y +CONFIG_8139CP=y + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SH_SCI_NR_UARTS=6 +CONFIG_SERIAL_SH_SCI_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_DEVPORT=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_BITBANG=y +CONFIG_SPI_SH_SCI=y + +# +# Multifunction device drivers +# +CONFIG_MFD_SM501=y + +# +# Graphics support +# +CONFIG_FB=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y + +# +# Frame buffer hardware drivers +# +CONFIG_FB_SM501=y + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_SUPERH_MONO=y +CONFIG_LOGO_SUPERH_VGA16=y +CONFIG_LOGO_SUPERH_CLUT224=y +CONFIG_HID_SUPPORT=y +CONFIG_HID=y + +# +# USB Input Devices +# +CONFIG_USB_HID=y + +# +# USB Host +# +CONFIG_USB_SUPPORT=y +CONFIG_USB=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICE_CLASS=y + +# +# USB Host Controller Drivers +# +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_LITTLE_ENDIAN=y + +# +# RTC +# +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y + +# +# SPI RTC drivers +# +CONFIG_RTC_DRV_R9701=y + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_SH is not set +# CONFIG_RTC_DRV_GENERIC is not set + +# +# File systems +# +CONFIG_EXT3_FS=y diff --git a/debian/config/sh4/defines b/debian/config/sh4/defines index ab45a8db8..7dd028a53 100644 --- a/debian/config/sh4/defines +++ b/debian/config/sh4/defines @@ -1,11 +1,19 @@ [base] flavours: + sh7751r sh7785lcr kernel-arch: sh [image] suggests: fdutils +[sh7751r_build] +image-file: arch/sh/boot/zImage + +[sh7751r_description] +hardware: sh7751r +hardware-long: Renesas SH7751R R2D plus board + [sh7785lcr_build] image-file: arch/sh/boot/zImage diff --git a/debian/linux-base.postinst b/debian/linux-base.postinst index c3219fe76..cd7d554d2 100644 --- a/debian/linux-base.postinst +++ b/debian/linux-base.postinst @@ -53,6 +53,9 @@ package DebianKernel::DiskId; ### utility +# Import _system() function +*_system = \&main::_system; + sub id_to_path { my ($id) = @_; $id =~ m|^/| @@ -881,7 +884,8 @@ sub cryptsetup_update { my ($text, $dst, $src, $key, $opts) = cryptsetup_next($old); last unless defined($text); if (defined($src) && defined($map->{$src})) { - $text = "# $text" . join(' ', $dst, $map->{$src}, $key, $opts); + $text = "# $text" . + join(' ', $dst, $map->{$src}, $key, $opts) . "\n"; } $new->print($text); } @@ -904,6 +908,25 @@ sub hdparm_list { return @results; } +### mdadm + +sub mdadm_list { + my ($file) = @_; + my (@results) = (); + + while (<$file>) { + # Look for DEVICE (case-insensitive, may be abbreviated to as + # little as 3 letters) followed by a whitespace-separated list + # of devices (or wildcards, or keywords!). Ignore comments + # (hash preceded by whitespace). + if (/^DEV(?:I(?:C(?:E)?)?)?[ \t]*((?:[^ \t]|[ \t][^#])*)/i) { + push @results, split(/[ \t]+/, $1); + } + } + + return @results; +} + ### list of all configuration files and functions my @config_files = ({packages => 'mount', @@ -984,7 +1007,8 @@ my @config_files = ({packages => 'mount', # mdadm.conf requires manual update because it may # contain wildcards. {packages => 'mdadm', - path => '/etc/mdadm/mdadm.conf'}, + path => '/etc/mdadm/mdadm.conf', + list => \&mdadm_list}, # hdparm.conf requires manual update because it # (1) refers to whole disks (2) might not work # properly with the new drivers (3) is in a very @@ -1170,8 +1194,11 @@ sub scan_config_files { $needs_update = defined($id_map_text) && $id_map_text ne ''; } elsif (exists($config->{list})) { for my $bdev (&{$config->{list}}($file)) { - if ($bdev =~ m{^/dev/(?:[hs]d[a-z]\d*|s(?:cd|r)\d+)$} && - -b $bdev) { + # Match standard IDE and SCSI device names, plus wildcards + # in disk device names to allow for mdadm insanity. + if ($bdev =~ m{^/dev/(?:[hs]d[a-z\?\*][\d\?\*]*| + s(?:cd|r)\d+)$}x && + ($bdev =~ m/[\?\*]/ || -b $bdev)) { $bdev_map{$bdev} = {}; push @matched_bdevs, $bdev; } @@ -1219,10 +1246,16 @@ sub add_tag { } sub scan_devices { + my $id_command; + if (-x '/sbin/vol_id') { + $id_command = '/sbin/vol_id'; + } else { + $id_command = 'blkid -o udev -s LABEL -s UUID'; + } for (`blkid -o device`) { chomp; my $bdev = $_; - for (`blkid -o udev -s LABEL -s UUID '$bdev'`) { + for (`$id_command '$bdev'`) { if (/^ID_FS_(LABEL|UUID)_ENC=(.+)\n$/) { add_tag($bdev, $1, $2); } @@ -1232,12 +1265,13 @@ sub scan_devices { # Discard all labels and UUIDs(!) that are ambiguous. # Discard all labels with 'unsafe' characters (escaped by blkid using # backslashes) as they will not be usable in all configuration files. + # Similarly for '#' which blkid surprisingly does not consider unsafe. # Sort each device's IDs in reverse lexical order so that UUIDs are # preferred. for my $bdev (keys(%bdev_map)) { @{$bdev_map{$bdev}->{ids}} = sort({$b cmp $a} - grep({ @{$id_map{$_}} == 1 && $_ !~ /\\/ } + grep({ @{$id_map{$_}} == 1 && $_ !~ /[\\#]/ } @{$bdev_map{$bdev}->{ids}})); } @@ -1341,10 +1375,7 @@ sub set_new_ids { } sub update_config { - my %map; - for my $bdev (keys(%bdev_map)) { - $map{$bdev} = $bdev_map{$bdev}->{ids}->[0]; - } + my $map = shift; for my $match (@_) { # Generate a new config @@ -1353,7 +1384,7 @@ sub update_config { my $new = new FileHandle("$path.new", POSIX::O_WRONLY | POSIX::O_CREAT, 0600) or die "$!"; - &{$match->{config}->{update}}($old, $new, \%map); + &{$match->{config}->{update}}($old, $new, $map); $old->close(); $new->close(); @@ -1386,6 +1417,7 @@ sub transition { my @auto_configs = grep({defined($_->{config}->{update})} @matched_configs); my $found_boot_loader = grep({$_->{config}->{is_boot_loader} && $_->{installed}} @found_configs); + my %update_map = (); # We can skip all of this if we didn't find any configuration # files that need conversion and we found the configuration file @@ -1412,6 +1444,22 @@ sub transition { scan_devices(); assign_new_ids(); + # Construct the device ID update map + for my $bdev (keys(%bdev_map)) { + if (@{$bdev_map{$bdev}->{ids}}) { + $update_map{$bdev} = $bdev_map{$bdev}->{ids}->[0]; + } + } + + # Weed out configurations which will be unaffected by this + # mapping or by a custom mapping described in id_map_text. + @auto_configs = grep({ defined($_->{id_map_text}) || + grep({exists($update_map{$_})} + @{$_->{devices}}) } + @auto_configs); + } + + if (@auto_configs && $answer eq 'true') { if (grep({$bdev_map{$_}->{new_id}} keys(%bdev_map))) { $question = 'linux-base/disk-id-convert-plan'; ($ret, $seen) = subst($question, 'relabel', @@ -1426,9 +1474,8 @@ sub transition { } ($ret, $seen) = subst($question, 'id_map', join("\\n", - map({sprintf("%s: %s", $_, $bdev_map{$_}->{ids}->[0])} - grep({@{$bdev_map{$_}->{ids}}} - keys(%bdev_map))), + map({sprintf("%s: %s", $_, $update_map{$_})} + keys(%update_map)), grep({defined} map({$_->{id_map_text}} @auto_configs)))); die "Error setting debconf substitutions in $question: $seen" if $ret; @@ -1449,7 +1496,7 @@ sub transition { if ($answer eq 'true') { set_new_ids(); - update_config(@auto_configs); + update_config(\%update_map, @auto_configs); } } @@ -1458,8 +1505,7 @@ sub transition { if (!defined($match->{config}->{update})) { push @unconv_files, $match->{config}->{path}; } else { - my @unconv_bdevs = grep({!exists($bdev_map{$_}->{ids}) || - @{$bdev_map{$_}->{ids}} == 0} + my @unconv_bdevs = grep({!exists($update_map{$_})} @{$match->{devices}}); if (@unconv_bdevs) { push @unconv_files, sprintf('%s: %s', $match->{config}->{path}, diff --git a/debian/patches/bugfix/all/block-blk_abort_request-lock-fix.patch b/debian/patches/bugfix/all/block-blk_abort_request-lock-fix.patch new file mode 100644 index 000000000..a0b32ee43 --- /dev/null +++ b/debian/patches/bugfix/all/block-blk_abort_request-lock-fix.patch @@ -0,0 +1,84 @@ +From: Tejun Heo +Subject: libata/SCSI: fix locking around blk_abort_request() +References: bnc#585927 +Patch-mainline: submitted for 2.6.34-rc5 and stable (as two patches) + +blk_abort_request() expects queue lock to be held by the caller. +Grab it before calling the function. + +Lack of this synchronization led to infinite loop on corrupt +q->timeout_list. + +Signed-off-by: Tejun Heo +--- + drivers/ata/libata-eh.c | 4 ++++ + drivers/scsi/libsas/sas_ata.c | 4 ++++ + drivers/scsi/libsas/sas_scsi_host.c | 4 ++++ + 3 files changed, 12 insertions(+) + +Index: linux-2.6.32-SLE11-SP1/drivers/ata/libata-eh.c +=================================================================== +--- linux-2.6.32-SLE11-SP1.orig/drivers/ata/libata-eh.c ++++ linux-2.6.32-SLE11-SP1/drivers/ata/libata-eh.c +@@ -870,6 +870,8 @@ static void ata_eh_set_pending(struct at + void ata_qc_schedule_eh(struct ata_queued_cmd *qc) + { + struct ata_port *ap = qc->ap; ++ struct request_queue *q = qc->scsicmd->device->request_queue; ++ unsigned long flags; + + WARN_ON(!ap->ops->error_handler); + +@@ -881,7 +883,9 @@ void ata_qc_schedule_eh(struct ata_queue + * Note that ATA_QCFLAG_FAILED is unconditionally set after + * this function completes. + */ ++ spin_lock_irqsave(q->queue_lock, flags); + blk_abort_request(qc->scsicmd->request); ++ spin_unlock_irqrestore(q->queue_lock, flags); + } + + /** +Index: linux-2.6.32-SLE11-SP1/drivers/scsi/libsas/sas_ata.c +=================================================================== +--- linux-2.6.32-SLE11-SP1.orig/drivers/scsi/libsas/sas_ata.c ++++ linux-2.6.32-SLE11-SP1/drivers/scsi/libsas/sas_ata.c +@@ -394,11 +394,15 @@ int sas_ata_init_host_and_port(struct do + void sas_ata_task_abort(struct sas_task *task) + { + struct ata_queued_cmd *qc = task->uldd_task; ++ struct request_queue *q = qc->scsicmd->device->request_queue; + struct completion *waiting; ++ unsigned long flags; + + /* Bounce SCSI-initiated commands to the SCSI EH */ + if (qc->scsicmd) { ++ spin_lock_irqsave(q->queue_lock, flags); + blk_abort_request(qc->scsicmd->request); ++ spin_unlock_irqrestore(q->queue_lock, flags); + scsi_schedule_eh(qc->scsicmd->device->host); + return; + } +Index: linux-2.6.32-SLE11-SP1/drivers/scsi/libsas/sas_scsi_host.c +=================================================================== +--- linux-2.6.32-SLE11-SP1.orig/drivers/scsi/libsas/sas_scsi_host.c ++++ linux-2.6.32-SLE11-SP1/drivers/scsi/libsas/sas_scsi_host.c +@@ -1029,6 +1029,8 @@ int __sas_task_abort(struct sas_task *ta + void sas_task_abort(struct sas_task *task) + { + struct scsi_cmnd *sc = task->uldd_task; ++ struct request_queue *q = sc->device->request_queue; ++ unsigned long flags; + + /* Escape for libsas internal commands */ + if (!sc) { +@@ -1043,7 +1045,9 @@ void sas_task_abort(struct sas_task *tas + return; + } + ++ spin_lock_irqsave(q->queue_lock, flags); + blk_abort_request(sc->request); ++ spin_unlock_irqrestore(q->queue_lock, flags); + scsi_schedule_eh(sc->device->host); + } + diff --git a/debian/patches/bugfix/all/cifs-allow-null-nd-on-create.patch b/debian/patches/bugfix/all/cifs-allow-null-nd-on-create.patch new file mode 100644 index 000000000..cb72298da --- /dev/null +++ b/debian/patches/bugfix/all/cifs-allow-null-nd-on-create.patch @@ -0,0 +1,127 @@ +[CIFS] Allow null nd (as nfs server uses) on create + +While creating a file on a server which supports unix extensions +such as Samba, if a file is being created which does not supply +nameidata (i.e. nd is null), cifs client can oops when calling +cifs_posix_open. + +Signed-off-by: Shirish Pargaonkar +Signed-off-by: Steve French +--- + + +Adjusted to apply to Debian's 2.6.32 by dann frazier + + +diff -urpN a/fs/cifs/cifsproto.h b/fs/cifs/cifsproto.h +--- a/fs/cifs/cifsproto.h 2009-12-02 20:51:21.000000000 -0700 ++++ b/fs/cifs/cifsproto.h 2010-04-30 00:24:18.000000000 -0600 +@@ -95,8 +95,10 @@ extern struct cifsFileInfo *cifs_new_fil + __u16 fileHandle, struct file *file, + struct vfsmount *mnt, unsigned int oflags); + extern int cifs_posix_open(char *full_path, struct inode **pinode, +- struct vfsmount *mnt, int mode, int oflags, +- __u32 *poplock, __u16 *pnetfid, int xid); ++ struct vfsmount *mnt, ++ struct super_block *sb, ++ int mode, int oflags, ++ __u32 *poplock, __u16 *pnetfid, int xid); + extern void cifs_unix_basic_to_fattr(struct cifs_fattr *fattr, + FILE_UNIX_BASIC_INFO *info, + struct cifs_sb_info *cifs_sb); +diff -urpN a/fs/cifs/dir.c b/fs/cifs/dir.c +--- a/fs/cifs/dir.c 2009-12-02 20:51:21.000000000 -0700 ++++ b/fs/cifs/dir.c 2010-04-30 00:24:18.000000000 -0600 +@@ -183,13 +183,14 @@ cifs_new_fileinfo(struct inode *newinode + } + + int cifs_posix_open(char *full_path, struct inode **pinode, +- struct vfsmount *mnt, int mode, int oflags, +- __u32 *poplock, __u16 *pnetfid, int xid) ++ struct vfsmount *mnt, struct super_block *sb, ++ int mode, int oflags, ++ __u32 *poplock, __u16 *pnetfid, int xid) + { + int rc; + FILE_UNIX_BASIC_INFO *presp_data; + __u32 posix_flags = 0; +- struct cifs_sb_info *cifs_sb = CIFS_SB(mnt->mnt_sb); ++ struct cifs_sb_info *cifs_sb = CIFS_SB(sb); + struct cifs_fattr fattr; + + cFYI(1, ("posix open %s", full_path)); +@@ -241,7 +242,7 @@ int cifs_posix_open(char *full_path, str + + /* get new inode and set it up */ + if (*pinode == NULL) { +- *pinode = cifs_iget(mnt->mnt_sb, &fattr); ++ *pinode = cifs_iget(sb, &fattr); + if (!*pinode) { + rc = -ENOMEM; + goto posix_open_ret; +@@ -250,7 +251,8 @@ int cifs_posix_open(char *full_path, str + cifs_fattr_to_inode(*pinode, &fattr); + } + +- cifs_new_fileinfo(*pinode, *pnetfid, NULL, mnt, oflags); ++ if (mnt) ++ cifs_new_fileinfo(*pinode, *pnetfid, NULL, mnt, oflags); + + posix_open_ret: + kfree(presp_data); +@@ -314,13 +316,14 @@ cifs_create(struct inode *inode, struct + if (nd && (nd->flags & LOOKUP_OPEN)) + oflags = nd->intent.open.flags; + else +- oflags = FMODE_READ; ++ oflags = FMODE_READ | SMB_O_CREAT; + + if (tcon->unix_ext && (tcon->ses->capabilities & CAP_UNIX) && + (CIFS_UNIX_POSIX_PATH_OPS_CAP & + le64_to_cpu(tcon->fsUnixInfo.Capability))) { +- rc = cifs_posix_open(full_path, &newinode, nd->path.mnt, +- mode, oflags, &oplock, &fileHandle, xid); ++ rc = cifs_posix_open(full_path, &newinode, ++ nd ? nd->path.mnt : NULL, ++ inode->i_sb, mode, oflags, &oplock, &fileHandle, xid); + /* EIO could indicate that (posix open) operation is not + supported, despite what server claimed in capability + negotation. EREMOTE indicates DFS junction, which is not +@@ -677,6 +680,7 @@ cifs_lookup(struct inode *parent_dir_ino + (nd->flags & LOOKUP_OPEN) && !pTcon->broken_posix_open && + (nd->intent.open.flags & O_CREAT)) { + rc = cifs_posix_open(full_path, &newInode, nd->path.mnt, ++ parent_dir_inode->i_sb, + nd->intent.open.create_mode, + nd->intent.open.flags, &oplock, + &fileHandle, xid); +diff -urpN a/fs/cifs/file.c b/fs/cifs/file.c +--- a/fs/cifs/file.c 2009-12-02 20:51:21.000000000 -0700 ++++ b/fs/cifs/file.c 2010-04-30 00:24:18.000000000 -0600 +@@ -295,10 +295,12 @@ int cifs_open(struct inode *inode, struc + (CIFS_UNIX_POSIX_PATH_OPS_CAP & + le64_to_cpu(tcon->fsUnixInfo.Capability))) { + int oflags = (int) cifs_posix_convert_flags(file->f_flags); ++ oflags |= SMB_O_CREAT; + /* can not refresh inode info since size could be stale */ + rc = cifs_posix_open(full_path, &inode, file->f_path.mnt, +- cifs_sb->mnt_file_mode /* ignored */, +- oflags, &oplock, &netfid, xid); ++ inode->i_sb, ++ cifs_sb->mnt_file_mode /* ignored */, ++ oflags, &oplock, &netfid, xid); + if (rc == 0) { + cFYI(1, ("posix open succeeded")); + /* no need for special case handling of setting mode +@@ -510,8 +512,9 @@ reopen_error_exit: + int oflags = (int) cifs_posix_convert_flags(file->f_flags); + /* can not refresh inode info since size could be stale */ + rc = cifs_posix_open(full_path, NULL, file->f_path.mnt, +- cifs_sb->mnt_file_mode /* ignored */, +- oflags, &oplock, &netfid, xid); ++ inode->i_sb, ++ cifs_sb->mnt_file_mode /* ignored */, ++ oflags, &oplock, &netfid, xid); + if (rc == 0) { + cFYI(1, ("posix reopen succeeded")); + goto reopen_success; diff --git a/debian/patches/bugfix/all/drivers-net-wireless-p54-txrx.c-Fix-off-by-one-error.patch b/debian/patches/bugfix/all/drivers-net-wireless-p54-txrx.c-Fix-off-by-one-error.patch new file mode 100644 index 000000000..aa3f0b2ac --- /dev/null +++ b/debian/patches/bugfix/all/drivers-net-wireless-p54-txrx.c-Fix-off-by-one-error.patch @@ -0,0 +1,31 @@ +From 088ea189c4c75cdf211146faa4b341a0f7476be6 Mon Sep 17 00:00:00 2001 +From: Darren Jenkins +Date: Wed, 17 Feb 2010 23:40:15 +1100 +Subject: [PATCH] drivers/net/wireless/p54/txrx.c Fix off by one error + +fix off by one error in the queue size check of p54_tx_qos_accounting_alloc() + +Coverity CID: 13314 + +Signed-off-by: Darren Jenkins +Signed-off-by: John W. Linville +--- + drivers/net/wireless/p54/txrx.c | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +diff --git a/drivers/net/wireless/p54/txrx.c b/drivers/net/wireless/p54/txrx.c +index 0e8f694..6605799 100644 +--- a/drivers/net/wireless/p54/txrx.c ++++ b/drivers/net/wireless/p54/txrx.c +@@ -186,7 +186,7 @@ static int p54_tx_qos_accounting_alloc(struct p54_common *priv, + struct p54_tx_queue_stats *queue; + unsigned long flags; + +- if (WARN_ON(p54_queue > P54_QUEUE_NUM)) ++ if (WARN_ON(p54_queue >= P54_QUEUE_NUM)) + return -EINVAL; + + queue = &priv->tx_stats[p54_queue]; +-- +1.6.5 + diff --git a/debian/patches/bugfix/all/drm-i915-Stop-trying-to-use-ACPI-lid-status-to-deter.patch b/debian/patches/bugfix/all/drm-i915-Stop-trying-to-use-ACPI-lid-status-to-deter.patch new file mode 100644 index 000000000..3283d2f55 --- /dev/null +++ b/debian/patches/bugfix/all/drm-i915-Stop-trying-to-use-ACPI-lid-status-to-deter.patch @@ -0,0 +1,100 @@ +From: Eric Anholt +Date: Wed, 17 Mar 2010 13:48:06 -0700 +Subject: [PATCH] drm/i915: Stop trying to use ACPI lid status to determine LVDS connection. + +I've been getting more and more quirk reports about this. It seems +clear at this point that other OSes are not using this for determining +whether the integrated panel should be turned on, and it is not +reliable for doing so. Better to light up an unintended panel than to +not light up the only usable output on the system. + +Signed-off-by: Eric Anholt +Acked-by: Jesse Barnes +[bwh: Backport to drm-2.6.33] + +--- a/drivers/gpu/drm/i915/i915_drv.h ++++ b/drivers/gpu/drm/i915/i915_drv.h +@@ -1045,6 +1045,13 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); + #define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx) + #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) + ++#define IS_GEN3(dev) (IS_I915G(dev) || \ ++ IS_I915GM(dev) || \ ++ IS_I945G(dev) || \ ++ IS_I945GM(dev) || \ ++ IS_G33(dev) || \ ++ IS_PINEVIEW(dev)) ++ + #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) + + /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte +--- a/drivers/gpu/drm/i915/intel_lvds.c ++++ b/drivers/gpu/drm/i915/intel_lvds.c +@@ -599,53 +599,6 @@ static void intel_lvds_mode_set(struct drm_encoder *encoder, + I915_WRITE(PFIT_CONTROL, lvds_priv->pfit_control); + } + +-/* Some lid devices report incorrect lid status, assume they're connected */ +-static const struct dmi_system_id bad_lid_status[] = { +- { +- .ident = "Compaq nx9020", +- .matches = { +- DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), +- DMI_MATCH(DMI_BOARD_NAME, "3084"), +- }, +- }, +- { +- .ident = "Samsung SX20S", +- .matches = { +- DMI_MATCH(DMI_SYS_VENDOR, "Samsung Electronics"), +- DMI_MATCH(DMI_BOARD_NAME, "SX20S"), +- }, +- }, +- { +- .ident = "Aspire One", +- .matches = { +- DMI_MATCH(DMI_SYS_VENDOR, "Acer"), +- DMI_MATCH(DMI_PRODUCT_NAME, "Aspire one"), +- }, +- }, +- { +- .ident = "Aspire 1810T", +- .matches = { +- DMI_MATCH(DMI_SYS_VENDOR, "Acer"), +- DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 1810T"), +- }, +- }, +- { +- .ident = "PC-81005", +- .matches = { +- DMI_MATCH(DMI_SYS_VENDOR, "MALATA"), +- DMI_MATCH(DMI_PRODUCT_NAME, "PC-81005"), +- }, +- }, +- { +- .ident = "Clevo M5x0N", +- .matches = { +- DMI_MATCH(DMI_SYS_VENDOR, "CLEVO Co."), +- DMI_MATCH(DMI_BOARD_NAME, "M5x0N"), +- }, +- }, +- { } +-}; +- + /** + * Detect the LVDS connection. + * +@@ -661,12 +614,9 @@ static enum drm_connector_status intel_lvds_detect(struct drm_connector *connect + /* ACPI lid methods were generally unreliable in this generation, so + * don't even bother. + */ +- if (IS_I8XX(dev)) ++ if (IS_I8XX(dev) || IS_GEN3(dev)) + return connector_status_connected; + +- if (!dmi_check_system(bad_lid_status) && !acpi_lid_open()) +- status = connector_status_disconnected; +- + return status; + } + diff --git a/debian/patches/bugfix/all/drm-radeon-kms-further-spread-spectrum-fixes.patch b/debian/patches/bugfix/all/drm-radeon-kms-further-spread-spectrum-fixes.patch new file mode 100644 index 000000000..ae081aa09 --- /dev/null +++ b/debian/patches/bugfix/all/drm-radeon-kms-further-spread-spectrum-fixes.patch @@ -0,0 +1,97 @@ +From 7aac5b711ff4c64bad5a6027cf6d38f1bbd53efe Mon Sep 17 00:00:00 2001 +From: Dave Airlie +Date: Tue, 20 Apr 2010 18:30:37 +1000 +Subject: [PATCH] drm/radeon/kms: further spread spectrum fixes + +Adjust modeset ordering to fix spread spectrum. +The spread spectrum command table relies on the +crtc routing to already be set in order to work +properly on some asics. + +Should fix fdo bug 25741. + +Signed-off-by: Alex Deucher +Signed-off-by: Dave Airlie + +Conflicts: + + drivers/gpu/drm/radeon/atombios_crtc.c +--- + drivers/gpu/drm/radeon/atombios_crtc.c | 5 +++++ + drivers/gpu/drm/radeon/radeon_encoders.c | 25 +++++++++++++++---------- + 2 files changed, 20 insertions(+), 10 deletions(-) + +diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c +index c076eac..e70b575 100644 +--- a/drivers/gpu/drm/radeon/atombios_crtc.c ++++ b/drivers/gpu/drm/radeon/atombios_crtc.c +@@ -1115,6 +1115,11 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, + + static void atombios_crtc_prepare(struct drm_crtc *crtc) + { ++ struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); ++ ++ /* pick pll */ ++ radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); ++ + atombios_lock_crtc(crtc, ATOM_ENABLE); + atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); + } +diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c +index cac9e06..ff28ad8 100644 +--- a/drivers/gpu/drm/radeon/radeon_encoders.c ++++ b/drivers/gpu/drm/radeon/radeon_encoders.c +@@ -1207,6 +1207,9 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder) + } + + atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); ++ ++ /* update scratch regs with new routing */ ++ radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); + } + + static void +@@ -1317,19 +1320,9 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, + struct drm_device *dev = encoder->dev; + struct radeon_device *rdev = dev->dev_private; + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); +- struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); + +- if (radeon_encoder->active_device & +- (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) { +- struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; +- if (dig) +- dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); +- } + radeon_encoder->pixel_clock = adjusted_mode->clock; + +- radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); +- atombios_set_encoder_crtc_source(encoder); +- + if (ASIC_IS_AVIVO(rdev)) { + if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) + atombios_yuv_setup(encoder, true); +@@ -1483,8 +1476,20 @@ radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connec + + static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) + { ++ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); ++ ++ if (radeon_encoder->active_device & ++ (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) { ++ struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; ++ if (dig) ++ dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); ++ } ++ + radeon_atom_output_lock(encoder, true); + radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); ++ ++ /* this is needed for the pll/ss setup to work correctly in some cases */ ++ atombios_set_encoder_crtc_source(encoder); + } + + static void radeon_atom_encoder_commit(struct drm_encoder *encoder) +-- +1.6.5.2 + diff --git a/debian/patches/bugfix/all/ext4-issue-discard-operation-before-releasing-blocks.patch b/debian/patches/bugfix/all/ext4-issue-discard-operation-before-releasing-blocks.patch new file mode 100644 index 000000000..aa103bdda --- /dev/null +++ b/debian/patches/bugfix/all/ext4-issue-discard-operation-before-releasing-blocks.patch @@ -0,0 +1,62 @@ +From: Theodore Ts'o +Date: Tue, 20 Apr 2010 20:51:59 +0000 (-0400) +Subject: ext4: Issue the discard operation *before* releasing the blocks to be reused +X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Ftorvalds%2Flinux-2.6.git;a=commitdiff_plain;h=b90f687018e6d6c77d981b09203780f7001407e5 + +ext4: Issue the discard operation *before* releasing the blocks to be reused + +[ backported to 2.6.3[23] ] + +Otherwise, we can end up having data corruption because the blocks +could get reused and then discarded! + +https://bugzilla.kernel.org/show_bug.cgi?id=15579 + +Signed-off-by: "Theodore Ts'o" +--- + +diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c +index 54df209..e5ab41b 100644 +--- a/fs/ext4/mballoc.c ++++ b/fs/ext4/mballoc.c +@@ -2534,6 +2534,20 @@ static void release_blocks_on_commit(journal_t *journal, transaction_t *txn) + mb_debug(1, "gonna free %u blocks in group %u (0x%p):", + entry->count, entry->group, entry); + ++ if (test_opt(sb, DISCARD)) { ++ ext4_fsblk_t discard_block; ++ struct ext4_super_block *es = EXT4_SB(sb)->s_es; ++ ++ discard_block = (ext4_fsblk_t)entry->group * ++ EXT4_BLOCKS_PER_GROUP(sb) ++ + entry->start_blk ++ + le32_to_cpu(es->s_first_data_block); ++ trace_ext4_discard_blocks(sb, ++ (unsigned long long)discard_block, ++ entry->count); ++ sb_issue_discard(sb, discard_block, entry->count); ++ } ++ + err = ext4_mb_load_buddy(sb, entry->group, &e4b); + /* we expect to find existing buddy because it's pinned */ + BUG_ON(err != 0); +@@ -2555,19 +2566,6 @@ static void release_blocks_on_commit(journal_t *journal, transaction_t *txn) + page_cache_release(e4b.bd_bitmap_page); + } + ext4_unlock_group(sb, entry->group); +- if (test_opt(sb, DISCARD)) { +- ext4_fsblk_t discard_block; +- struct ext4_super_block *es = EXT4_SB(sb)->s_es; +- +- discard_block = (ext4_fsblk_t)entry->group * +- EXT4_BLOCKS_PER_GROUP(sb) +- + entry->start_blk +- + le32_to_cpu(es->s_first_data_block); +- trace_ext4_discard_blocks(sb, +- (unsigned long long)discard_block, +- entry->count); +- sb_issue_discard(sb, discard_block, entry->count); +- } + kmem_cache_free(ext4_free_ext_cachep, entry); + ext4_mb_release_desc(&e4b); + } diff --git a/debian/patches/bugfix/all/forcedeth-fix-tx-limit2-flag-check.patch b/debian/patches/bugfix/all/forcedeth-fix-tx-limit2-flag-check.patch new file mode 100644 index 000000000..4b9ef1e8b --- /dev/null +++ b/debian/patches/bugfix/all/forcedeth-fix-tx-limit2-flag-check.patch @@ -0,0 +1,35 @@ +From 5c659322a904a7cc0265e7b183372b9bdebec6db Mon Sep 17 00:00:00 2001 +From: Ayaz Abdulla +Date: Tue, 13 Apr 2010 18:49:51 -0700 +Subject: [PATCH] forcedeth: fix tx limit2 flag check + +This is a fix for bug 572201 @ bugs.debian.org + +This patch fixes the TX_LIMIT feature flag. The previous logic check +for TX_LIMIT2 also took into account a device that only had TX_LIMIT +set. + +Reported-by: Stephen Mulcahu +Reported-by: Ben Huchings +Signed-off-by: Ayaz Abdulla +Signed-off-by: David S. Miller +--- + drivers/net/forcedeth.c | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c +index 73b260c..5c98f7c 100644 +--- a/drivers/net/forcedeth.c ++++ b/drivers/net/forcedeth.c +@@ -5899,7 +5899,7 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i + /* Limit the number of tx's outstanding for hw bug */ + if (id->driver_data & DEV_NEED_TX_LIMIT) { + np->tx_limit = 1; +- if ((id->driver_data & DEV_NEED_TX_LIMIT2) && ++ if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) && + pci_dev->revision >= 0xA2) + np->tx_limit = 0; + } +-- +1.7.0.3 + diff --git a/debian/patches/bugfix/all/hugetlb-fix-infinite-loop-in-get_futex_key-when-backed-by-huge-pages.patch b/debian/patches/bugfix/all/hugetlb-fix-infinite-loop-in-get_futex_key-when-backed-by-huge-pages.patch new file mode 100644 index 000000000..8dc7a9a6f --- /dev/null +++ b/debian/patches/bugfix/all/hugetlb-fix-infinite-loop-in-get_futex_key-when-backed-by-huge-pages.patch @@ -0,0 +1,78 @@ +From 23be7468e8802a2ac1de6ee3eecb3ec7f14dc703 Mon Sep 17 00:00:00 2001 +From: Mel Gorman +Date: Fri, 23 Apr 2010 13:17:56 -0400 +Subject: hugetlb: fix infinite loop in get_futex_key() when backed by huge pages + +From: Mel Gorman + +commit 23be7468e8802a2ac1de6ee3eecb3ec7f14dc703 upstream. + +If a futex key happens to be located within a huge page mapped +MAP_PRIVATE, get_futex_key() can go into an infinite loop waiting for a +page->mapping that will never exist. + +See https://bugzilla.redhat.com/show_bug.cgi?id=552257 for more details +about the problem. + +This patch makes page->mapping a poisoned value that includes +PAGE_MAPPING_ANON mapped MAP_PRIVATE. This is enough for futex to +continue but because of PAGE_MAPPING_ANON, the poisoned value is not +dereferenced or used by futex. No other part of the VM should be +dereferencing the page->mapping of a hugetlbfs page as its page cache is +not on the LRU. + +This patch fixes the problem with the test case described in the bugzilla. + +[akpm@linux-foundation.org: mel cant spel] +Signed-off-by: Mel Gorman +Acked-by: Peter Zijlstra +Acked-by: Darren Hart +Signed-off-by: Andrew Morton +Signed-off-by: Linus Torvalds +Signed-off-by: Greg Kroah-Hartman + +--- + include/linux/poison.h | 9 +++++++++ + mm/hugetlb.c | 5 ++++- + 2 files changed, 13 insertions(+), 1 deletion(-) + +--- a/include/linux/poison.h ++++ b/include/linux/poison.h +@@ -48,6 +48,15 @@ + #define POISON_FREE 0x6b /* for use-after-free poisoning */ + #define POISON_END 0xa5 /* end-byte of poisoning */ + ++/********** mm/hugetlb.c **********/ ++/* ++ * Private mappings of hugetlb pages use this poisoned value for ++ * page->mapping. The core VM should not be doing anything with this mapping ++ * but futex requires the existence of some page->mapping value even though it ++ * is unused if PAGE_MAPPING_ANON is set. ++ */ ++#define HUGETLB_POISON ((void *)(0x00300300 + POISON_POINTER_DELTA + PAGE_MAPPING_ANON)) ++ + /********** arch/$ARCH/mm/init.c **********/ + #define POISON_FREE_INITMEM 0xcc + +--- a/mm/hugetlb.c ++++ b/mm/hugetlb.c +@@ -545,6 +545,7 @@ static void free_huge_page(struct page * + + mapping = (struct address_space *) page_private(page); + set_page_private(page, 0); ++ page->mapping = NULL; + BUG_ON(page_count(page)); + INIT_LIST_HEAD(&page->lru); + +@@ -2095,8 +2096,10 @@ retry: + spin_lock(&inode->i_lock); + inode->i_blocks += blocks_per_huge_page(h); + spin_unlock(&inode->i_lock); +- } else ++ } else { + lock_page(page); ++ page->mapping = HUGETLB_POISON; ++ } + } + + /* diff --git a/debian/patches/bugfix/all/ipheth-potential-null-dereferences-on-error-path.patch b/debian/patches/bugfix/all/ipheth-potential-null-dereferences-on-error-path.patch new file mode 100644 index 000000000..5d5023ad7 --- /dev/null +++ b/debian/patches/bugfix/all/ipheth-potential-null-dereferences-on-error-path.patch @@ -0,0 +1,73 @@ +From d87ff58fda926fe5cb01214cccf1c72422ac776d Mon Sep 17 00:00:00 2001 +From: Dan Carpenter +Date: Mon, 26 Apr 2010 23:20:12 +0000 +Subject: [PATCH] ipheth: potential null dereferences on error path +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The calls to usb_free_buffer() dereference rx_urb and tx_urb in the +parameter list but those could be NULL. + +Signed-off-by: Dan Carpenter +Acked-by: L. Alberto Giménez +Signed-off-by: David S. Miller +--- + drivers/net/usb/ipheth.c | 15 ++++++++------- + 1 files changed, 8 insertions(+), 7 deletions(-) + +diff --git a/drivers/net/usb/ipheth.c b/drivers/net/usb/ipheth.c +index fd10331..418825d 100644 +--- a/drivers/net/usb/ipheth.c ++++ b/drivers/net/usb/ipheth.c +@@ -122,25 +122,25 @@ static int ipheth_alloc_urbs(struct ipheth_device *iphone) + + tx_urb = usb_alloc_urb(0, GFP_KERNEL); + if (tx_urb == NULL) +- goto error; ++ goto error_nomem; + + rx_urb = usb_alloc_urb(0, GFP_KERNEL); + if (rx_urb == NULL) +- goto error; ++ goto free_tx_urb; + + tx_buf = usb_buffer_alloc(iphone->udev, + IPHETH_BUF_SIZE, + GFP_KERNEL, + &tx_urb->transfer_dma); + if (tx_buf == NULL) +- goto error; ++ goto free_rx_urb; + + rx_buf = usb_buffer_alloc(iphone->udev, + IPHETH_BUF_SIZE, + GFP_KERNEL, + &rx_urb->transfer_dma); + if (rx_buf == NULL) +- goto error; ++ goto free_tx_buf; + + + iphone->tx_urb = tx_urb; +@@ -149,13 +149,14 @@ static int ipheth_alloc_urbs(struct ipheth_device *iphone) + iphone->rx_buf = rx_buf; + return 0; + +-error: +- usb_buffer_free(iphone->udev, IPHETH_BUF_SIZE, rx_buf, +- rx_urb->transfer_dma); ++free_tx_buf: + usb_buffer_free(iphone->udev, IPHETH_BUF_SIZE, tx_buf, + tx_urb->transfer_dma); ++free_rx_urb: + usb_free_urb(rx_urb); ++free_tx_urb: + usb_free_urb(tx_urb); ++error_nomem: + return -ENOMEM; + } + +-- +1.7.0.3 + diff --git a/debian/patches/bugfix/all/libata-ata_piix-clear-spurious-IRQ.patch b/debian/patches/bugfix/all/libata-ata_piix-clear-spurious-IRQ.patch new file mode 100644 index 000000000..2940473f1 --- /dev/null +++ b/debian/patches/bugfix/all/libata-ata_piix-clear-spurious-IRQ.patch @@ -0,0 +1,148 @@ +From: Tejun Heo +Subject: libata,ata_piix: detect and clear spurious IRQs +Patch-Mainline: Backported from changes pending for 2.6.34 +References: bnc#445872, bnc#589449 + +Backport spurious IRQ handling from 2.6.34. It isn't exactly the same +form in that it doesn't use callbacks but implements custom +piix_interrupt() but should function the same. This protects ata_piix +against nobody-cared which gets reported not so rarely. + +Signed-off-by: Tejun Heo +Signed-off-by: Tejun Heo +--- + drivers/ata/ata_piix.c | 76 ++++++++++++++++++++++++++++++++++++++++++++++- + drivers/ata/libata-sff.c | 12 ++++++- + 2 files changed, 85 insertions(+), 3 deletions(-) + +Index: linux-2.6.32-SLE11-SP1/drivers/ata/ata_piix.c +=================================================================== +--- linux-2.6.32-SLE11-SP1.orig/drivers/ata/ata_piix.c ++++ linux-2.6.32-SLE11-SP1/drivers/ata/ata_piix.c +@@ -949,6 +949,80 @@ static int piix_sidpr_scr_read(struct at + return 0; + } + ++static irqreturn_t piix_interrupt(int irq, void *dev_instance) ++{ ++ struct ata_host *host = dev_instance; ++ bool retried = false; ++ unsigned int i; ++ unsigned int handled = 0, polling = 0, idle = 0; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&host->lock, flags); ++retry: ++ handled = idle = polling = 0; ++ for (i = 0; i < host->n_ports; i++) { ++ struct ata_port *ap = host->ports[i]; ++ struct ata_queued_cmd *qc; ++ ++ if (ata_port_is_dummy(ap)) ++ continue; ++ ++ qc = ata_qc_from_tag(ap, ap->link.active_tag); ++ if (qc) { ++ if (!(qc->tf.flags & ATA_TFLAG_POLLING)) ++ handled |= ata_sff_host_intr(ap, qc); ++ else ++ polling |= 1 << i; ++ } else ++ idle |= 1 << i; ++ } ++ ++ /* ++ * If no port was expecting IRQ but the controller is actually ++ * asserting IRQ line, nobody cared will ensue. Check IRQ ++ * pending status if available and clear spurious IRQ. ++ */ ++ if (!handled && !retried) { ++ bool retry = false; ++ ++ for (i = 0; i < host->n_ports; i++) { ++ struct ata_port *ap = host->ports[i]; ++ u8 host_stat; ++ ++ if (polling & (1 << i)) ++ continue; ++ ++ if (unlikely(!ap->ioaddr.bmdma_addr)) ++ continue; ++ ++ host_stat = ap->ops->bmdma_status(ap); ++ if (!(host_stat & ATA_DMA_INTR)) ++ continue; ++ ++ if (idle & (1 << i)) { ++ ap->ops->sff_check_status(ap); ++ ap->ops->sff_irq_clear(ap); ++ } else { ++ /* clear INTRQ and check if BUSY cleared */ ++ if (!(ap->ops->sff_check_status(ap) & ATA_BUSY)) ++ retry |= true; ++ /* ++ * With command in flight, we can't do ++ * sff_irq_clear() w/o racing with completion. ++ */ ++ } ++ } ++ if (retry) { ++ retried = true; ++ goto retry; ++ } ++ } ++ ++ spin_unlock_irqrestore(&host->lock, flags); ++ ++ return IRQ_RETVAL(handled); ++} ++ + static int piix_sidpr_scr_write(struct ata_link *link, + unsigned int reg, u32 val) + { +@@ -1607,7 +1681,7 @@ static int __devinit piix_init_one(struc + host->flags |= ATA_HOST_PARALLEL_SCAN; + + pci_set_master(pdev); +- return ata_pci_sff_activate_host(host, ata_sff_interrupt, &piix_sht); ++ return ata_pci_sff_activate_host(host, piix_interrupt, &piix_sht); + } + + static void piix_remove_one(struct pci_dev *pdev) +Index: linux-2.6.32-SLE11-SP1/drivers/ata/libata-sff.c +=================================================================== +--- linux-2.6.32-SLE11-SP1.orig/drivers/ata/libata-sff.c ++++ linux-2.6.32-SLE11-SP1/drivers/ata/libata-sff.c +@@ -1667,6 +1667,7 @@ unsigned int ata_sff_host_intr(struct at + { + struct ata_eh_info *ehi = &ap->link.eh_info; + u8 status, host_stat = 0; ++ bool bmdma_stopped = false; + + VPRINTK("ata%u: protocol %d task_state %d\n", + ap->print_id, qc->tf.protocol, ap->hsm_task_state); +@@ -1699,6 +1700,7 @@ unsigned int ata_sff_host_intr(struct at + + /* before we do anything else, clear DMA-Start bit */ + ap->ops->bmdma_stop(qc); ++ bmdma_stopped = true; + + if (unlikely(host_stat & ATA_DMA_ERR)) { + /* error when transfering data to/from memory */ +@@ -1716,8 +1718,14 @@ unsigned int ata_sff_host_intr(struct at + + /* check main status, clearing INTRQ if needed */ + status = ata_sff_irq_status(ap); +- if (status & ATA_BUSY) +- goto idle_irq; ++ if (status & ATA_BUSY) { ++ if (bmdma_stopped) { ++ /* BMDMA engine is already stopped, we're screwed */ ++ qc->err_mask |= AC_ERR_HSM; ++ ap->hsm_task_state = HSM_ST_ERR; ++ } else ++ goto idle_irq; ++ } + + /* ack bmdma irq events */ + ap->ops->sff_irq_clear(ap); diff --git a/debian/patches/bugfix/all/libata-fix-accesses-at-LBA28-boundary.patch b/debian/patches/bugfix/all/libata-fix-accesses-at-LBA28-boundary.patch new file mode 100644 index 000000000..87036a31d --- /dev/null +++ b/debian/patches/bugfix/all/libata-fix-accesses-at-LBA28-boundary.patch @@ -0,0 +1,35 @@ +From: Mark Lord +Date: Wed, 7 Apr 2010 17:52:08 +0000 (-0400) +Subject: libata: Fix accesses at LBA28 boundary (old bug, but nasty) (v2) +X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Ftorvalds%2Flinux-2.6.git;a=commitdiff_plain;h=45c4d015a92f72ec47acd0c7557abdc0c8a6499d + +libata: Fix accesses at LBA28 boundary (old bug, but nasty) (v2) + +Most drives from Seagate, Hitachi, and possibly other brands, +do not allow LBA28 access to sector number 0x0fffffff (2^28 - 1). +So instead use LBA48 for such accesses. + +This bug could bite a lot of systems, especially when the user has +taken care to align partitions to 4KB boundaries. On misaligned systems, +it is less likely to be encountered, since a 4KB read would end at +0x10000000 rather than at 0x0fffffff. + +Signed-off-by: Mark Lord +Signed-off-by: Jeff Garzik +--- + +diff --git a/include/linux/ata.h b/include/linux/ata.h +index b4c85e2..700c5b9 100644 +--- a/include/linux/ata.h ++++ b/include/linux/ata.h +@@ -1025,8 +1025,8 @@ static inline int ata_ok(u8 status) + + static inline int lba_28_ok(u64 block, u32 n_block) + { +- /* check the ending block number */ +- return ((block + n_block) < ((u64)1 << 28)) && (n_block <= 256); ++ /* check the ending block number: must be LESS THAN 0x0fffffff */ ++ return ((block + n_block) < ((1 << 28) - 1)) && (n_block <= 256); + } + + static inline int lba_48_ok(u64 block, u32 n_block) diff --git a/debian/patches/bugfix/all/libiscsi-regression-fix-header-digest-errors.patch b/debian/patches/bugfix/all/libiscsi-regression-fix-header-digest-errors.patch new file mode 100644 index 000000000..59b557720 --- /dev/null +++ b/debian/patches/bugfix/all/libiscsi-regression-fix-header-digest-errors.patch @@ -0,0 +1,49 @@ +From: michaelc@cs.wisc.edu +To: linux-scsi@vger.kernel.org +Cc: Mike Christie +Subject: [PATCH] libiscsi: regression: fix header digest errors +Date: Sat, 24 Apr 2010 16:21:19 -0500 +Message-Id: <1272144079-10494-1-git-send-email-michaelc@cs.wisc.edu> + + +This fixes a regression introduced with this commit: +d3305f3407fa3e9452079ec6cc8379067456e4aa +in 2.6.32. + +When I moved the hdr->cmdsn after init_task, I added +a bug when header digests are used. The problem is +that the LLD may calculate the header digest in init_task, +so if we then set the cmdsn after the init_task call we +change what the digest will be calculated by the target. + +Signed-off-by: Mike Christie +--- + drivers/scsi/libiscsi.c | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +diff --git a/drivers/scsi/libiscsi.c b/drivers/scsi/libiscsi.c +index 6d5ae44..633e090 100644 +--- a/drivers/scsi/libiscsi.c ++++ b/drivers/scsi/libiscsi.c +@@ -471,12 +471,12 @@ static int iscsi_prep_scsi_cmd_pdu(struct iscsi_task *task) + + WARN_ON(hdrlength >= 256); + hdr->hlength = hdrlength & 0xFF; ++ hdr->cmdsn = task->cmdsn = cpu_to_be32(session->cmdsn); + + if (session->tt->init_task && session->tt->init_task(task)) + return -EIO; + + task->state = ISCSI_TASK_RUNNING; +- hdr->cmdsn = task->cmdsn = cpu_to_be32(session->cmdsn); + session->cmdsn++; + + conn->scsicmd_pdus_cnt++; +-- +1.6.6.1 + +-- +To unsubscribe from this list: send the line "unsubscribe linux-scsi" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html + diff --git a/debian/patches/bugfix/all/p54pci-fix-bugs-in-p54p_check_tx_ring.patch b/debian/patches/bugfix/all/p54pci-fix-bugs-in-p54p_check_tx_ring.patch new file mode 100644 index 000000000..4908ca27c --- /dev/null +++ b/debian/patches/bugfix/all/p54pci-fix-bugs-in-p54p_check_tx_ring.patch @@ -0,0 +1,106 @@ +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on dual +X-Spam-Level: +X-Spam-Status: No, score=0.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM, + KB_DATE_CONTAINS_TAB autolearn=no version=3.3.1 +X-Original-To: maks@dual +Delivered-To: maks@dual +Received: from dual (localhost.localdomain [127.0.0.1]) + by dual (Postfix) with ESMTP id ED48524045 + for ; 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Thu, 22 Apr 2010 19:52:17 +0200 (CEST) +Received: from blech.mobile (localhost [127.0.0.1]) + by blech.mobile (Postfix) with ESMTP id ADBA2342417; + Thu, 22 Apr 2010 19:52:17 +0200 (CEST) +From: Christian Lamparter +To: linux-wireless@vger.kernel.org +Subject: [PATCH 1/2] p54pci: fix bugs in p54p_check_tx_ring +Date: Thu, 22 Apr 2010 19:52:16 +0200 +User-Agent: KMail/1.12.4 (Linux/2.6.34-rc5-uber-wl; KDE/4.3.4; x86_64; ; ) +Cc: linville@tuxdriver.com, hdegoede@redhat.com +MIME-Version: 1.0 +X-Length: 2052 +X-UID: 75 +Content-Type: Text/Plain; + charset="iso-8859-1" +Content-Transfer-Encoding: 7bit +Message-Id: <201004221952.16857.chunkeey@googlemail.com> +Sender: linux-wireless-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org +Content-Length: 1159 + +From: Hans de Goede + +Hans de Goede identified a bug in p54p_check_tx_ring: + +there are two ring indices. 1 => tx data and 3 => tx management. +But the old code had a constant "1" and this resulted in spurious +dma unmapping failures. + +Cc: stable@kernel.org +Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=583623 +Bug-Identified-by: Hans de Goede +Signed-off-by: Christian Lamparter +--- +diff --git a/drivers/net/wireless/p54/p54pci.c b/drivers/net/wireless/p54/p54pci.c +index 679da7e..cffe2f2 100644 +--- a/drivers/net/wireless/p54/p54pci.c ++++ b/drivers/net/wireless/p54/p54pci.c +@@ -246,7 +246,7 @@ static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index, + u32 idx, i; + + i = (*index) % ring_limit; +- (*index) = idx = le32_to_cpu(ring_control->device_idx[1]); ++ (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]); + idx %= ring_limit; + + while (i != idx) { +-- +To unsubscribe from this list: send the line "unsubscribe linux-wireless" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html + diff --git a/debian/patches/bugfix/all/p54pci-fix-regression.patch b/debian/patches/bugfix/all/p54pci-fix-regression.patch new file mode 100644 index 000000000..905fccdc3 --- /dev/null +++ b/debian/patches/bugfix/all/p54pci-fix-regression.patch @@ -0,0 +1,164 @@ +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on dual +X-Spam-Level: +X-Spam-Status: No, score=0.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM, + KB_DATE_CONTAINS_TAB autolearn=no version=3.3.1 +X-Original-To: maks@dual +Delivered-To: maks@dual +Received: from dual (localhost.localdomain [127.0.0.1]) + by dual (Postfix) with ESMTP id 6945624045 + for ; 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Thu, 22 Apr 2010 19:52:44 +0200 (CEST) +Received: from blech.mobile (localhost [127.0.0.1]) + by blech.mobile (Postfix) with ESMTP id 80D53342417; + Thu, 22 Apr 2010 19:52:44 +0200 (CEST) +From: Christian Lamparter +To: linux-wireless@vger.kernel.org +Subject: [PATCH 2/2] p54pci: fix regression from prevent stuck rx-ring on slow system +Date: Thu, 22 Apr 2010 19:52:43 +0200 +User-Agent: KMail/1.12.4 (Linux/2.6.34-rc5-uber-wl; KDE/4.3.4; x86_64; ; ) +Cc: linville@tuxdriver.com, hdegoede@redhat.com +MIME-Version: 1.0 +X-Length: 4801 +X-UID: 74 +Content-Type: text/plain; + charset="iso-8859-1" +Content-Transfer-Encoding: 7bit +Message-Id: <201004221952.44071.chunkeey@googlemail.com> +Sender: linux-wireless-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org +Content-Length: 4096 + +From: Hans de Goede + +This patch fixes a recently introduced use-after-free regression +from "p54pci: prevent stuck rx-ring on slow system". + +Hans de Goede reported a use-after-free regression: +>BUG: unable to handle kernel paging request at 6b6b6b6b +>IP: [] p54p_check_tx_ring+0x84/0xb1 [p54pci] +>*pde = 00000000 +>Oops: 0000 [#1] SMP +>EIP: 0060:[] EFLAGS: 00010286 CPU: 0 +>EIP is at p54p_check_tx_ring+0x84/0xb1 [p54pci] +>EAX: 6b6b6b6b EBX: df10b170 ECX: 00000003 EDX: 00000001 +>ESI: dc471500 EDI: d8acaeb0 EBP: c098be9c ESP: c098be84 +> DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 +>Process swapper (pid: 0, ti=c098a000 task=c09ccfe0 task.ti=c098a000) +>Call Trace: +> [] ? p54p_tasklet+0xaa/0xb5 [p54pci] +> [] ? tasklet_action+0x78/0xcb +> [] ? __do_softirq+0xbc/0x173 + +Quote from comment #17: +"The problem is the innocent looking moving of the tx processing to + after the rx processing in the tasklet. Quoting from the changelog: + This patch does it the same way, except that it also prioritize + rx data processing, simply because tx routines *can* wait. + + This is causing an issue with us referencing already freed memory, + because some skb's we transmit, we immediately receive back, such + as those for reading the eeprom (*) and getting stats. + + What can happen because of the moving of the tx processing to after + the rx processing is that when the tasklet first runs after doing a + special skb tx (such as eeprom) we've already received the answer + to it. + + Then the rx processing ends up calling p54_find_and_unlink_skb to + find the matching tx skb for the just received special rx skb and + frees the tx skb. + + Then after the processing of the rx skb answer, and thus freeing + the tx skb, we go process the completed tx ring entires, and then + dereference the free-ed skb, to see if it should free free-ed by + p54p_check_tx_ring()." + +Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=583623 +Bug-Identified-by: Hans de Goede +Signed-off-by: Hans de Goede +Signed-off-by: Christian Lamparter +--- +diff --git a/drivers/net/wireless/p54/p54pci.c b/drivers/net/wireless/p54/p54pci.c +index ca42ccb..07c4528 100644 +--- a/drivers/net/wireless/p54/p54pci.c ++++ b/drivers/net/wireless/p54/p54pci.c +@@ -277,6 +277,14 @@ static void p54p_tasklet(unsigned long dev_id) + struct p54p_priv *priv = dev->priv; + struct p54p_ring_control *ring_control = priv->ring_control; + ++ p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, 3, ring_control->tx_mgmt, ++ ARRAY_SIZE(ring_control->tx_mgmt), ++ priv->tx_buf_mgmt); ++ ++ p54p_check_tx_ring(dev, &priv->tx_idx_data, 1, ring_control->tx_data, ++ ARRAY_SIZE(ring_control->tx_data), ++ priv->tx_buf_data); ++ + p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt, + ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt); + +@@ -285,14 +293,6 @@ static void p54p_tasklet(unsigned long dev_id) + + wmb(); + P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE)); +- +- p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, 3, ring_control->tx_mgmt, +- ARRAY_SIZE(ring_control->tx_mgmt), +- priv->tx_buf_mgmt); +- +- p54p_check_tx_ring(dev, &priv->tx_idx_data, 1, ring_control->tx_data, +- ARRAY_SIZE(ring_control->tx_data), +- priv->tx_buf_data); + } + + static irqreturn_t p54p_interrupt(int irq, void *dev_id) +-- +To unsubscribe from this list: send the line "unsubscribe linux-wireless" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html + diff --git a/debian/patches/bugfix/all/p54pci-fix-serious-sparse-warning.patch b/debian/patches/bugfix/all/p54pci-fix-serious-sparse-warning.patch new file mode 100644 index 000000000..221b84782 --- /dev/null +++ b/debian/patches/bugfix/all/p54pci-fix-serious-sparse-warning.patch @@ -0,0 +1,103 @@ +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on dual +X-Spam-Level: +X-Spam-Status: No, score=0.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM, + KB_DATE_CONTAINS_TAB autolearn=no version=3.3.1 +X-Original-To: maks@dual +Delivered-To: maks@dual +Received: from dual (localhost.localdomain [127.0.0.1]) + by dual (Postfix) with ESMTP id 4027E2429D + for ; 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Thu, 15 Apr 2010 14:17:08 +0200 (CEST) +Received: from blech.mobile (localhost [127.0.0.1]) + by blech.mobile (Postfix) with ESMTP id 6D2D834077B; + Thu, 15 Apr 2010 14:17:08 +0200 (CEST) +From: Christian Lamparter +To: linux-wireless@vger.kernel.org +Subject: [PATCH] p54pci: fix serious sparse warning +Date: Thu, 15 Apr 2010 14:17:07 +0200 +User-Agent: KMail/1.12.4 (Linux/2.6.34-rc3-uber-wl; KDE/4.3.4; x86_64; ; ) +Cc: linville@tuxdriver.com +MIME-Version: 1.0 +Content-Type: Text/Plain; + charset="iso-8859-1" +Content-Transfer-Encoding: 7bit +Message-Id: <201004151417.07538.chunkeey@googlemail.com> +Sender: linux-wireless-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org +X-Virus-Scanned: by Amavis (ClamAV) at stro.at +Content-Length: 1202 + +This patch fixes a bug which was just recently introduced by +("p54pci: prevent stuck rx-ring on slow system"). + +make M=drivers/net/wireless/p54 C=2 CF=-D__CHECK_ENDIAN__ + CHECK drivers/net/wireless/p54/p54pci.c +drivers/net/wireless/p54/p54pci.c:143:11: warning: cast to restricted __le32 + CC [M] drivers/net/wireless/p54/p54pci.o + +Reported-by: Johannes Berg +Signed-off-by: Christian Lamparter +--- +diff --git a/drivers/net/wireless/p54/p54pci.c b/drivers/net/wireless/p54/p54pci.c +index 86f3e9a..679da7e 100644 +--- a/drivers/net/wireless/p54/p54pci.c ++++ b/drivers/net/wireless/p54/p54pci.c +@@ -140,7 +140,7 @@ static void p54p_refill_rx_ring(struct ieee80211_hw *dev, + + idx = le32_to_cpu(ring_control->host_idx[ring_index]); + limit = idx; +- limit -= le32_to_cpu(index); ++ limit -= index; + limit = ring_limit - limit; + + i = idx % ring_limit; +-- +To unsubscribe from this list: send the line "unsubscribe linux-wireless" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html + diff --git a/debian/patches/bugfix/all/p54pci-move-tx-cleanup-into-tasklet.patch b/debian/patches/bugfix/all/p54pci-move-tx-cleanup-into-tasklet.patch new file mode 100644 index 000000000..ec556a98f --- /dev/null +++ b/debian/patches/bugfix/all/p54pci-move-tx-cleanup-into-tasklet.patch @@ -0,0 +1,180 @@ +From d713804c6032b95cd3035014e16fadebb9655c6f Mon Sep 17 00:00:00 2001 +From: Christian Lamparter +Date: Sun, 17 Jan 2010 23:19:25 +0100 +Subject: [PATCH] p54pci: move tx cleanup into tasklet + +This patch moves the tx cleanup routines out of the critical +interrupt context and into the (previously known as rx) tasklet. + +The main goal of this operation is to remove the extensive +usage of spin_lock_irqsaves in the generic p54common library. + +The next step would be to modify p54usb to do the +rx processing inside a tasklet (just like usbnet). + +Signed-off-by: Christian Lamparter +Signed-off-by: John W. Linville +--- + drivers/net/wireless/p54/p54pci.c | 56 +++++++++++++++++++------------------ + drivers/net/wireless/p54/p54pci.h | 6 ++-- + 2 files changed, 32 insertions(+), 30 deletions(-) + +diff --git a/drivers/net/wireless/p54/p54pci.c b/drivers/net/wireless/p54/p54pci.c +index 4bf4c21..48cae48 100644 +--- a/drivers/net/wireless/p54/p54pci.c ++++ b/drivers/net/wireless/p54/p54pci.c +@@ -234,25 +234,26 @@ static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index, + p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf); + } + +-/* caller must hold priv->lock */ + static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index, + int ring_index, struct p54p_desc *ring, u32 ring_limit, +- void **tx_buf) ++ struct sk_buff **tx_buf) + { ++ unsigned long flags; + struct p54p_priv *priv = dev->priv; + struct p54p_ring_control *ring_control = priv->ring_control; + struct p54p_desc *desc; ++ struct sk_buff *skb; + u32 idx, i; + + i = (*index) % ring_limit; + (*index) = idx = le32_to_cpu(ring_control->device_idx[1]); + idx %= ring_limit; + ++ spin_lock_irqsave(&priv->lock, flags); + while (i != idx) { + desc = &ring[i]; +- if (tx_buf[i]) +- if (FREE_AFTER_TX((struct sk_buff *) tx_buf[i])) +- p54_free_skb(dev, tx_buf[i]); ++ ++ skb = tx_buf[i]; + tx_buf[i] = NULL; + + pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr), +@@ -263,17 +264,32 @@ static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index, + desc->len = 0; + desc->flags = 0; + ++ if (skb && FREE_AFTER_TX(skb)) { ++ spin_unlock_irqrestore(&priv->lock, flags); ++ p54_free_skb(dev, skb); ++ spin_lock_irqsave(&priv->lock, flags); ++ } ++ + i++; + i %= ring_limit; + } ++ spin_unlock_irqrestore(&priv->lock, flags); + } + +-static void p54p_rx_tasklet(unsigned long dev_id) ++static void p54p_tasklet(unsigned long dev_id) + { + struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id; + struct p54p_priv *priv = dev->priv; + struct p54p_ring_control *ring_control = priv->ring_control; + ++ p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, 3, ring_control->tx_mgmt, ++ ARRAY_SIZE(ring_control->tx_mgmt), ++ priv->tx_buf_mgmt); ++ ++ p54p_check_tx_ring(dev, &priv->tx_idx_data, 1, ring_control->tx_data, ++ ARRAY_SIZE(ring_control->tx_data), ++ priv->tx_buf_data); ++ + p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt, + ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt); + +@@ -288,38 +304,24 @@ static irqreturn_t p54p_interrupt(int irq, void *dev_id) + { + struct ieee80211_hw *dev = dev_id; + struct p54p_priv *priv = dev->priv; +- struct p54p_ring_control *ring_control = priv->ring_control; + __le32 reg; + + spin_lock(&priv->lock); + reg = P54P_READ(int_ident); + if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) { +- spin_unlock(&priv->lock); +- return IRQ_HANDLED; ++ goto out; + } +- + P54P_WRITE(int_ack, reg); + + reg &= P54P_READ(int_enable); + +- if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE)) { +- p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, +- 3, ring_control->tx_mgmt, +- ARRAY_SIZE(ring_control->tx_mgmt), +- priv->tx_buf_mgmt); +- +- p54p_check_tx_ring(dev, &priv->tx_idx_data, +- 1, ring_control->tx_data, +- ARRAY_SIZE(ring_control->tx_data), +- priv->tx_buf_data); +- +- tasklet_schedule(&priv->rx_tasklet); +- +- } else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT)) ++ if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE)) ++ tasklet_schedule(&priv->tasklet); ++ else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT)) + complete(&priv->boot_comp); + ++out: + spin_unlock(&priv->lock); +- + return reg ? IRQ_HANDLED : IRQ_NONE; + } + +@@ -368,7 +370,7 @@ static void p54p_stop(struct ieee80211_hw *dev) + unsigned int i; + struct p54p_desc *desc; + +- tasklet_kill(&priv->rx_tasklet); ++ tasklet_kill(&priv->tasklet); + + P54P_WRITE(int_enable, cpu_to_le32(0)); + P54P_READ(int_enable); +@@ -559,7 +561,7 @@ static int __devinit p54p_probe(struct pci_dev *pdev, + priv->common.tx = p54p_tx; + + spin_lock_init(&priv->lock); +- tasklet_init(&priv->rx_tasklet, p54p_rx_tasklet, (unsigned long)dev); ++ tasklet_init(&priv->tasklet, p54p_tasklet, (unsigned long)dev); + + err = request_firmware(&priv->firmware, "isl3886pci", + &priv->pdev->dev); +diff --git a/drivers/net/wireless/p54/p54pci.h b/drivers/net/wireless/p54/p54pci.h +index fbb6839..2feead6 100644 +--- a/drivers/net/wireless/p54/p54pci.h ++++ b/drivers/net/wireless/p54/p54pci.h +@@ -92,7 +92,7 @@ struct p54p_priv { + struct p54_common common; + struct pci_dev *pdev; + struct p54p_csr __iomem *map; +- struct tasklet_struct rx_tasklet; ++ struct tasklet_struct tasklet; + const struct firmware *firmware; + spinlock_t lock; + struct p54p_ring_control *ring_control; +@@ -101,8 +101,8 @@ struct p54p_priv { + u32 rx_idx_mgmt, tx_idx_mgmt; + struct sk_buff *rx_buf_data[8]; + struct sk_buff *rx_buf_mgmt[4]; +- void *tx_buf_data[32]; +- void *tx_buf_mgmt[4]; ++ struct sk_buff *tx_buf_data[32]; ++ struct sk_buff *tx_buf_mgmt[4]; + struct completion boot_comp; + }; + +-- +1.6.5 + diff --git a/debian/patches/bugfix/all/p54pci-prevent-stuck-rx-ring.patch b/debian/patches/bugfix/all/p54pci-prevent-stuck-rx-ring.patch new file mode 100644 index 000000000..51d43605b --- /dev/null +++ b/debian/patches/bugfix/all/p54pci-prevent-stuck-rx-ring.patch @@ -0,0 +1,188 @@ +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on dual +X-Spam-Level: +X-Spam-Status: No, score=0.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM, + KB_DATE_CONTAINS_TAB autolearn=no version=3.3.1 +X-Original-To: maks@dual +Delivered-To: maks@dual +Received: from dual (localhost.localdomain [127.0.0.1]) + by dual (Postfix) with ESMTP id 9C5E5240B2 + for ; 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Fri, 09 Apr 2010 21:37:41 +0200 +To: linux-wireless@vger.kernel.org +Subject: [PATCH] p54pci: prevent stuck rx-ring on slow system +Cc: linville@tuxdriver.com +From: Christian Lamparter +Date: Fri, 9 Apr 2010 21:37:38 +0200 +MIME-Version: 1.0 +Content-Type: Text/Plain; + charset="iso-8859-1" +Content-Transfer-Encoding: 7bit +Message-Id: <201004092137.39285.chunkeey@googlemail.com> +Sender: linux-wireless-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-wireless@vger.kernel.org +X-Virus-Scanned: by Amavis (ClamAV) at stro.at +Content-Length: 4420 + +From: Quintin Pitts + +This patch fixes an old problem, which - under certain +circumstances - could cause the device to become +unresponsive. + +most of p54pci's rx-ring management is implemented in just +two distinct standalone functions. p54p_check_rx_ring takes +care of processing incoming data, while p54p_refill_rx_ring +tries to replenish all depleted communication buffers. + +This has always worked fine on my fast machine, but +now I know there is a hidden race... + +The most likely candidate here is ring_control->device_idx. +Quintin Pitts had already analyzed the culprit and posted +a patch back in Oct 2009. But sadly, no one's picked up on this. +( https://patchwork.kernel.org/patch/53079/ [2 & 3] ). +This patch does the same way, except that it also prioritize +rx data processing, simply because tx routines *can* wait. + +Reported-by: Sean Young +Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=11386 +Reported-by: Quintin Pitts +Signed-off-by: Quintin Pitts +Signed-off-by: Christian Lamparter +--- +John, + +It's been nearly a week and no complains or regressions +have been reported. Therefore I think it is now save to +finally merge this patch... Preferably into -next, so +bug #11386 can be closed for 2.6.34 release. + +Regards, + Chr +--- +diff --git a/drivers/net/wireless/p54/p54pci.c b/drivers/net/wireless/p54/p54pci.c +index ed4bdff..aa29663 100644 +--- a/drivers/net/wireless/p54/p54pci.c ++++ b/drivers/net/wireless/p54/p54pci.c +@@ -131,7 +131,7 @@ static int p54p_upload_firmware(struct ieee80211_hw *dev) + + static void p54p_refill_rx_ring(struct ieee80211_hw *dev, + int ring_index, struct p54p_desc *ring, u32 ring_limit, +- struct sk_buff **rx_buf) ++ struct sk_buff **rx_buf, u32 index) + { + struct p54p_priv *priv = dev->priv; + struct p54p_ring_control *ring_control = priv->ring_control; +@@ -139,7 +139,7 @@ static void p54p_refill_rx_ring(struct ieee80211_hw *dev, + + idx = le32_to_cpu(ring_control->host_idx[ring_index]); + limit = idx; +- limit -= le32_to_cpu(ring_control->device_idx[ring_index]); ++ limit -= le32_to_cpu(index); + limit = ring_limit - limit; + + i = idx % ring_limit; +@@ -231,7 +231,7 @@ static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index, + i %= ring_limit; + } + +- p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf); ++ p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf, *index); + } + + static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index, +@@ -276,14 +276,6 @@ static void p54p_tasklet(unsigned long dev_id) + struct p54p_priv *priv = dev->priv; + struct p54p_ring_control *ring_control = priv->ring_control; + +- p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, 3, ring_control->tx_mgmt, +- ARRAY_SIZE(ring_control->tx_mgmt), +- priv->tx_buf_mgmt); +- +- p54p_check_tx_ring(dev, &priv->tx_idx_data, 1, ring_control->tx_data, +- ARRAY_SIZE(ring_control->tx_data), +- priv->tx_buf_data); +- + p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt, + ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt); + +@@ -292,6 +284,14 @@ static void p54p_tasklet(unsigned long dev_id) + + wmb(); + P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE)); ++ ++ p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, 3, ring_control->tx_mgmt, ++ ARRAY_SIZE(ring_control->tx_mgmt), ++ priv->tx_buf_mgmt); ++ ++ p54p_check_tx_ring(dev, &priv->tx_idx_data, 1, ring_control->tx_data, ++ ARRAY_SIZE(ring_control->tx_data), ++ priv->tx_buf_data); + } + + static irqreturn_t p54p_interrupt(int irq, void *dev_id) +@@ -444,10 +444,10 @@ static int p54p_open(struct ieee80211_hw *dev) + priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0; + + p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data, +- ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data); ++ ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data, 0); + + p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt, +- ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt); ++ ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt, 0); + + P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma)); + P54P_READ(ring_control_base); +-- +To unsubscribe from this list: send the line "unsubscribe linux-wireless" in +the body of a message to majordomo@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html + diff --git a/debian/patches/bugfix/all/p54pci-revise-tx-locking.patch b/debian/patches/bugfix/all/p54pci-revise-tx-locking.patch new file mode 100644 index 000000000..5c3b77efd --- /dev/null +++ b/debian/patches/bugfix/all/p54pci-revise-tx-locking.patch @@ -0,0 +1,100 @@ +From b92f7d30830a319148df2943b7565989494e5ad1 Mon Sep 17 00:00:00 2001 +From: Christian Lamparter +Date: Fri, 22 Jan 2010 08:01:11 +0100 +Subject: [PATCH] p54pci: revise tx locking + +This patch continues the effort which began with: +"[PATCH] p54pci: move tx cleanup into tasklet". + +Thanks to these changes, p54pci's interrupt & tx +cleanup routines can be made lock-less. + +Signed-off-by: Christian Lamparter +Signed-off-by: John W. Linville +--- + drivers/net/wireless/p54/p54pci.c | 16 ++++------------ + 1 files changed, 4 insertions(+), 12 deletions(-) + +diff --git a/drivers/net/wireless/p54/p54pci.c b/drivers/net/wireless/p54/p54pci.c +index 48cae48..bda29c0 100644 +--- a/drivers/net/wireless/p54/p54pci.c ++++ b/drivers/net/wireless/p54/p54pci.c +@@ -238,7 +238,6 @@ static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index, + int ring_index, struct p54p_desc *ring, u32 ring_limit, + struct sk_buff **tx_buf) + { +- unsigned long flags; + struct p54p_priv *priv = dev->priv; + struct p54p_ring_control *ring_control = priv->ring_control; + struct p54p_desc *desc; +@@ -249,7 +248,6 @@ static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index, + (*index) = idx = le32_to_cpu(ring_control->device_idx[1]); + idx %= ring_limit; + +- spin_lock_irqsave(&priv->lock, flags); + while (i != idx) { + desc = &ring[i]; + +@@ -264,16 +262,12 @@ static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index, + desc->len = 0; + desc->flags = 0; + +- if (skb && FREE_AFTER_TX(skb)) { +- spin_unlock_irqrestore(&priv->lock, flags); ++ if (skb && FREE_AFTER_TX(skb)) + p54_free_skb(dev, skb); +- spin_lock_irqsave(&priv->lock, flags); +- } + + i++; + i %= ring_limit; + } +- spin_unlock_irqrestore(&priv->lock, flags); + } + + static void p54p_tasklet(unsigned long dev_id) +@@ -306,7 +300,6 @@ static irqreturn_t p54p_interrupt(int irq, void *dev_id) + struct p54p_priv *priv = dev->priv; + __le32 reg; + +- spin_lock(&priv->lock); + reg = P54P_READ(int_ident); + if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) { + goto out; +@@ -321,15 +314,14 @@ static irqreturn_t p54p_interrupt(int irq, void *dev_id) + complete(&priv->boot_comp); + + out: +- spin_unlock(&priv->lock); + return reg ? IRQ_HANDLED : IRQ_NONE; + } + + static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb) + { ++ unsigned long flags; + struct p54p_priv *priv = dev->priv; + struct p54p_ring_control *ring_control = priv->ring_control; +- unsigned long flags; + struct p54p_desc *desc; + dma_addr_t mapping; + u32 device_idx, idx, i; +@@ -370,14 +362,14 @@ static void p54p_stop(struct ieee80211_hw *dev) + unsigned int i; + struct p54p_desc *desc; + +- tasklet_kill(&priv->tasklet); +- + P54P_WRITE(int_enable, cpu_to_le32(0)); + P54P_READ(int_enable); + udelay(10); + + free_irq(priv->pdev->irq, dev); + ++ tasklet_kill(&priv->tasklet); ++ + P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET)); + + for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) { +-- +1.6.5 + diff --git a/debian/patches/bugfix/all/p54usb-Add-usbid-for-Corega-CG-WLUSB2GT.patch b/debian/patches/bugfix/all/p54usb-Add-usbid-for-Corega-CG-WLUSB2GT.patch new file mode 100644 index 000000000..42f6ff778 --- /dev/null +++ b/debian/patches/bugfix/all/p54usb-Add-usbid-for-Corega-CG-WLUSB2GT.patch @@ -0,0 +1,27 @@ +From 15a69a81731d337a3d9db51692ff8704c1114f43 Mon Sep 17 00:00:00 2001 +From: Shimada Hirofumi +Date: Sun, 14 Feb 2010 04:16:16 +0900 +Subject: [PATCH] p54usb: Add usbid for Corega CG-WLUSB2GT. + +Signed-off-by: Shimada Hirofumi +Signed-off-by: YOSHIFUJI Hideaki +Signed-off-by: John W. Linville +--- + drivers/net/wireless/p54/p54usb.c | 1 + + 1 files changed, 1 insertions(+), 0 deletions(-) + +diff --git a/drivers/net/wireless/p54/p54usb.c b/drivers/net/wireless/p54/p54usb.c +index 92af9b9..dcb484b 100644 +--- a/drivers/net/wireless/p54/p54usb.c ++++ b/drivers/net/wireless/p54/p54usb.c +@@ -36,6 +36,7 @@ static struct usb_device_id p54u_table[] __devinitdata = { + /* Version 1 devices (pci chip + net2280) */ + {USB_DEVICE(0x0506, 0x0a11)}, /* 3COM 3CRWE254G72 */ + {USB_DEVICE(0x0707, 0xee06)}, /* SMC 2862W-G */ ++ {USB_DEVICE(0x07aa, 0x001c)}, /* Corega CG-WLUSB2GT */ + {USB_DEVICE(0x083a, 0x4501)}, /* Accton 802.11g WN4501 USB */ + {USB_DEVICE(0x083a, 0x4502)}, /* Siemens Gigaset USB Adapter */ + {USB_DEVICE(0x083a, 0x5501)}, /* Phillips CPWUA054 */ +-- +1.6.5 + diff --git a/debian/patches/bugfix/all/phylib-fix-typo-in-bcm6xx-PHY-driver-table.patch b/debian/patches/bugfix/all/phylib-fix-typo-in-bcm6xx-PHY-driver-table.patch new file mode 100644 index 000000000..b51b22367 --- /dev/null +++ b/debian/patches/bugfix/all/phylib-fix-typo-in-bcm6xx-PHY-driver-table.patch @@ -0,0 +1,17 @@ +From: Florian Fainelli +Subject: [PATCH] PHY: fix typo in bcm63xx PHY driver table +Date: Fri, 9 Apr 2010 13:04:45 +0200 + + +Signed-off-by: Florian Fainelli +--- +diff --git a/drivers/net/phy/bcm63xx.c b/drivers/net/phy/bcm63xx.c +index ac5e498..c128156 100644 +--- a/drivers/net/phy/bcm63xx.c ++++ b/drivers/net/phy/bcm63xx.c +@@ -137,4 +137,4 @@ static struct mdio_device_id bcm63xx_tbl[] = { + { } + }; + +-MODULE_DEVICE_TABLE(mdio, bcm64xx_tbl); ++MODULE_DEVICE_TABLE(mdio, bcm63xx_tbl); diff --git a/debian/patches/bugfix/all/reiserfs-fix-permissions-on-reiserfs_priv.patch b/debian/patches/bugfix/all/reiserfs-fix-permissions-on-reiserfs_priv.patch new file mode 100644 index 000000000..4a2257b10 --- /dev/null +++ b/debian/patches/bugfix/all/reiserfs-fix-permissions-on-reiserfs_priv.patch @@ -0,0 +1,79 @@ +From: Jeff Mahoney +Subject: [PATCH] reiserfs: Fix permissions on .reiserfs_priv +References: bnc#593906 CVE-2010-1146 +Patch-mainline: Submitted 8 Apr 2010 + + Commit 677c9b2e393a0cd203bd54e9c18b012b2c73305a removed the magic + from the lookup code to hide the .reiserfs_priv directory since it + was getting loaded at mount-time instead. The intent was that the + entry would be hidden from the user via a poisoned d_compare, but + this was faulty. + + This introduced a security issue where unpriviledged users could + access and modify extended attributes or ACLs belonging to other + users, including root. + + This patch resolves the issue by properly hiding .reiserfs_priv. This + was the intent of the xattr poisoning code, but it appears to have + never worked as expected. This is fixed by using d_revalidate instead + of d_compare. + + This patch makes -oexpose_privroot a no-op. I'm fine leaving it this + way. The effort involved in working out the corner cases wrt permissions + and caching outweigh the benefit of the feature. + +Signed-off-by: Jeff Mahoney +--- + + fs/reiserfs/dir.c | 2 -- + fs/reiserfs/xattr.c | 17 ++++------------- + 2 files changed, 4 insertions(+), 15 deletions(-) + +--- a/fs/reiserfs/dir.c ++++ b/fs/reiserfs/dir.c +@@ -45,8 +45,6 @@ static inline bool is_privroot_deh(struc + struct reiserfs_de_head *deh) + { + struct dentry *privroot = REISERFS_SB(dir->d_sb)->priv_root; +- if (reiserfs_expose_privroot(dir->d_sb)) +- return 0; + return (dir == dir->d_parent && privroot->d_inode && + deh->deh_objectid == INODE_PKEY(privroot->d_inode)->k_objectid); + } +--- a/fs/reiserfs/xattr.c ++++ b/fs/reiserfs/xattr.c +@@ -972,21 +972,13 @@ int reiserfs_permission(struct inode *in + return generic_permission(inode, mask, NULL); + } + +-/* This will catch lookups from the fs root to .reiserfs_priv */ +-static int +-xattr_lookup_poison(struct dentry *dentry, struct qstr *q1, struct qstr *name) ++static int xattr_hide_revalidate(struct dentry *dentry, struct nameidata *nd) + { +- struct dentry *priv_root = REISERFS_SB(dentry->d_sb)->priv_root; +- if (container_of(q1, struct dentry, d_name) == priv_root) +- return -ENOENT; +- if (q1->len == name->len && +- !memcmp(q1->name, name->name, name->len)) +- return 0; +- return 1; ++ return -EPERM; + } + + static const struct dentry_operations xattr_lookup_poison_ops = { +- .d_compare = xattr_lookup_poison, ++ .d_revalidate = xattr_hide_revalidate, + }; + + int reiserfs_lookup_privroot(struct super_block *s) +@@ -1000,8 +992,7 @@ int reiserfs_lookup_privroot(struct supe + strlen(PRIVROOT_NAME)); + if (!IS_ERR(dentry)) { + REISERFS_SB(s)->priv_root = dentry; +- if (!reiserfs_expose_privroot(s)) +- s->s_root->d_op = &xattr_lookup_poison_ops; ++ dentry->d_op = &xattr_lookup_poison_ops; + if (dentry->d_inode) + dentry->d_inode->i_flags |= S_PRIVATE; + } else diff --git a/debian/patches/bugfix/all/rndis_host-Poll-status-channel-before-control-channel.patch b/debian/patches/bugfix/all/rndis_host-Poll-status-channel-before-control-channel.patch new file mode 100644 index 000000000..80e4a692f --- /dev/null +++ b/debian/patches/bugfix/all/rndis_host-Poll-status-channel-before-control-channel.patch @@ -0,0 +1,62 @@ +From 1c941691a933e9c2d0314c9b84ea77b6ef2807e1 Mon Sep 17 00:00:00 2001 +From: Ben Hutchings +Date: Fri, 9 Apr 2010 01:55:27 +0100 +Subject: [PATCH] rndis_host: Poll status channel before control channel + +Some RNDIS devices don't respond on the control channel until polled +on the status channel. In particular, this was reported to be the +case for the 2Wire HomePortal 1000SW. + +This is roughly based on a patch by John Carr +which is reported to be needed for use with some Windows Mobile devices +and which is currently applied by Mandriva. + +Reported-by: Mark Glassberg +Signed-off-by: Ben Hutchings +Tested-by: Mark Glassberg +--- + drivers/net/usb/rndis_host.c | 18 ++++++++++++------ + 1 files changed, 12 insertions(+), 6 deletions(-) + +diff --git a/drivers/net/usb/rndis_host.c b/drivers/net/usb/rndis_host.c +index f56dec6..52faca1 100644 +--- a/drivers/net/usb/rndis_host.c ++++ b/drivers/net/usb/rndis_host.c +@@ -103,8 +103,10 @@ static void rndis_msg_indicate(struct usbnet *dev, struct rndis_indicate *msg, + int rndis_command(struct usbnet *dev, struct rndis_msg_hdr *buf, int buflen) + { + struct cdc_state *info = (void *) &dev->data; ++ struct usb_cdc_notification notification; + int master_ifnum; + int retval; ++ int partial; + unsigned count; + __le32 rsp; + u32 xid = 0, msg_len, request_id; +@@ -132,13 +134,17 @@ int rndis_command(struct usbnet *dev, struct rndis_msg_hdr *buf, int buflen) + if (unlikely(retval < 0 || xid == 0)) + return retval; + +- // FIXME Seems like some devices discard responses when +- // we time out and cancel our "get response" requests... +- // so, this is fragile. Probably need to poll for status. ++ /* Some devices don't respond on the control channel until ++ * polled on the status channel, so do that first. */ ++ retval = usb_interrupt_msg( ++ dev->udev, ++ usb_rcvintpipe(dev->udev, dev->status->desc.bEndpointAddress), ++ ¬ification, sizeof(notification), &partial, ++ RNDIS_CONTROL_TIMEOUT_MS); ++ if (unlikely(retval < 0)) ++ return retval; + +- /* ignore status endpoint, just poll the control channel; +- * the request probably completed immediately +- */ ++ /* Poll the control channel; the request probably completed immediately */ + rsp = buf->msg_type | RNDIS_MSG_COMPLETION; + for (count = 0; count < 10; count++) { + memset(buf, 0, CONTROL_BUFFER_SIZE); +-- +1.7.0.3 + diff --git a/debian/patches/bugfix/all/sctp-fix-skb_over_panic-resulting-from-multiple-invalid-parameter-errors.patch b/debian/patches/bugfix/all/sctp-fix-skb_over_panic-resulting-from-multiple-invalid-parameter-errors.patch new file mode 100644 index 000000000..620807f7f --- /dev/null +++ b/debian/patches/bugfix/all/sctp-fix-skb_over_panic-resulting-from-multiple-invalid-parameter-errors.patch @@ -0,0 +1,218 @@ +commit 5fa782c2f5ef6c2e4f04d3e228412c9b4a4c8809 +Author: Neil Horman +Date: Wed Apr 28 10:30:59 2010 +0000 + + sctp: Fix skb_over_panic resulting from multiple invalid parameter errors (CVE-2010-1173) (v4) + + Ok, version 4 + + Change Notes: + 1) Minor cleanups, from Vlads notes + + Summary: + + Hey- + Recently, it was reported to me that the kernel could oops in the + following way: + + <5> kernel BUG at net/core/skbuff.c:91! + <5> invalid operand: 0000 [#1] + <5> Modules linked in: sctp netconsole nls_utf8 autofs4 sunrpc iptable_filter + ip_tables cpufreq_powersave parport_pc lp parport vmblock(U) vsock(U) vmci(U) + vmxnet(U) vmmemctl(U) vmhgfs(U) acpiphp dm_mirror dm_mod button battery ac md5 + ipv6 uhci_hcd ehci_hcd snd_ens1371 snd_rawmidi snd_seq_device snd_pcm_oss + snd_mixer_oss snd_pcm snd_timer snd_page_alloc snd_ac97_codec snd soundcore + pcnet32 mii floppy ext3 jbd ata_piix libata mptscsih mptsas mptspi mptscsi + mptbase sd_mod scsi_mod + <5> CPU: 0 + <5> EIP: 0060:[] Not tainted VLI + <5> EFLAGS: 00010216 (2.6.9-89.0.25.EL) + <5> EIP is at skb_over_panic+0x1f/0x2d + <5> eax: 0000002c ebx: c033f461 ecx: c0357d96 edx: c040fd44 + <5> esi: c033f461 edi: df653280 ebp: 00000000 esp: c040fd40 + <5> ds: 007b es: 007b ss: 0068 + <5> Process swapper (pid: 0, threadinfo=c040f000 task=c0370be0) + <5> Stack: c0357d96 e0c29478 00000084 00000004 c033f461 df653280 d7883180 + e0c2947d + <5> 00000000 00000080 df653490 00000004 de4f1ac0 de4f1ac0 00000004 + df653490 + <5> 00000001 e0c2877a 08000800 de4f1ac0 df653490 00000000 e0c29d2e + 00000004 + <5> Call Trace: + <5> [] sctp_addto_chunk+0xb0/0x128 [sctp] + <5> [] sctp_addto_chunk+0xb5/0x128 [sctp] + <5> [] sctp_init_cause+0x3f/0x47 [sctp] + <5> [] sctp_process_unk_param+0xac/0xb8 [sctp] + <5> [] sctp_verify_init+0xcc/0x134 [sctp] + <5> [] sctp_sf_do_5_1B_init+0x83/0x28e [sctp] + <5> [] sctp_do_sm+0x41/0x77 [sctp] + <5> [] cache_grow+0x140/0x233 + <5> [] sctp_endpoint_bh_rcv+0xc5/0x108 [sctp] + <5> [] sctp_inq_push+0xe/0x10 [sctp] + <5> [] sctp_rcv+0x454/0x509 [sctp] + <5> [] ipt_hook+0x17/0x1c [iptable_filter] + <5> [] nf_iterate+0x40/0x81 + <5> [] ip_local_deliver_finish+0x0/0x151 + <5> [] ip_local_deliver_finish+0xc6/0x151 + <5> [] nf_hook_slow+0x83/0xb5 + <5> [] ip_local_deliver+0x1a2/0x1a9 + <5> [] ip_local_deliver_finish+0x0/0x151 + <5> [] ip_rcv+0x334/0x3b4 + <5> [] netif_receive_skb+0x320/0x35b + <5> [] init_stall_timer+0x67/0x6a [uhci_hcd] + <5> [] process_backlog+0x6c/0xd9 + <5> [] net_rx_action+0xfe/0x1f8 + <5> [] __do_softirq+0x35/0x79 + <5> [] handle_IRQ_event+0x0/0x4f + <5> [] do_softirq+0x46/0x4d + + Its an skb_over_panic BUG halt that results from processing an init chunk in + which too many of its variable length parameters are in some way malformed. + + The problem is in sctp_process_unk_param: + if (NULL == *errp) + *errp = sctp_make_op_error_space(asoc, chunk, + ntohs(chunk->chunk_hdr->length)); + + if (*errp) { + sctp_init_cause(*errp, SCTP_ERROR_UNKNOWN_PARAM, + WORD_ROUND(ntohs(param.p->length))); + sctp_addto_chunk(*errp, + WORD_ROUND(ntohs(param.p->length)), + param.v); + + When we allocate an error chunk, we assume that the worst case scenario requires + that we have chunk_hdr->length data allocated, which would be correct nominally, + given that we call sctp_addto_chunk for the violating parameter. Unfortunately, + we also, in sctp_init_cause insert a sctp_errhdr_t structure into the error + chunk, so the worst case situation in which all parameters are in violation + requires chunk_hdr->length+(sizeof(sctp_errhdr_t)*param_count) bytes of data. + + The result of this error is that a deliberately malformed packet sent to a + listening host can cause a remote DOS, described in CVE-2010-1173: + http://cve.mitre.org/cgi-bin/cvename.cgi?name=2010-1173 + + I've tested the below fix and confirmed that it fixes the issue. We move to a + strategy whereby we allocate a fixed size error chunk and ignore errors we don't + have space to report. Tested by me successfully + + Signed-off-by: Neil Horman + Acked-by: Vlad Yasevich + Signed-off-by: David S. Miller + +diff --git a/include/net/sctp/structs.h b/include/net/sctp/structs.h +index ff30177..597f8e2 100644 +--- a/include/net/sctp/structs.h ++++ b/include/net/sctp/structs.h +@@ -778,6 +778,7 @@ int sctp_user_addto_chunk(struct sctp_chunk *chunk, int off, int len, + struct iovec *data); + void sctp_chunk_free(struct sctp_chunk *); + void *sctp_addto_chunk(struct sctp_chunk *, int len, const void *data); ++void *sctp_addto_chunk_fixed(struct sctp_chunk *, int len, const void *data); + struct sctp_chunk *sctp_chunkify(struct sk_buff *, + const struct sctp_association *, + struct sock *); +diff --git a/net/sctp/sm_make_chunk.c b/net/sctp/sm_make_chunk.c +index 0fd5b4c..30c1767 100644 +--- a/net/sctp/sm_make_chunk.c ++++ b/net/sctp/sm_make_chunk.c +@@ -108,7 +108,7 @@ static const struct sctp_paramhdr prsctp_param = { + cpu_to_be16(sizeof(struct sctp_paramhdr)), + }; + +-/* A helper to initialize to initialize an op error inside a ++/* A helper to initialize an op error inside a + * provided chunk, as most cause codes will be embedded inside an + * abort chunk. + */ +@@ -125,6 +125,29 @@ void sctp_init_cause(struct sctp_chunk *chunk, __be16 cause_code, + chunk->subh.err_hdr = sctp_addto_chunk(chunk, sizeof(sctp_errhdr_t), &err); + } + ++/* A helper to initialize an op error inside a ++ * provided chunk, as most cause codes will be embedded inside an ++ * abort chunk. Differs from sctp_init_cause in that it won't oops ++ * if there isn't enough space in the op error chunk ++ */ ++int sctp_init_cause_fixed(struct sctp_chunk *chunk, __be16 cause_code, ++ size_t paylen) ++{ ++ sctp_errhdr_t err; ++ __u16 len; ++ ++ /* Cause code constants are now defined in network order. */ ++ err.cause = cause_code; ++ len = sizeof(sctp_errhdr_t) + paylen; ++ err.length = htons(len); ++ ++ if (skb_tailroom(chunk->skb) > len) ++ return -ENOSPC; ++ chunk->subh.err_hdr = sctp_addto_chunk_fixed(chunk, ++ sizeof(sctp_errhdr_t), ++ &err); ++ return 0; ++} + /* 3.3.2 Initiation (INIT) (1) + * + * This chunk is used to initiate a SCTP association between two +@@ -1132,6 +1155,24 @@ nodata: + return retval; + } + ++/* Create an Operation Error chunk of a fixed size, ++ * specifically, max(asoc->pathmtu, SCTP_DEFAULT_MAXSEGMENT) ++ * This is a helper function to allocate an error chunk for ++ * for those invalid parameter codes in which we may not want ++ * to report all the errors, if the incomming chunk is large ++ */ ++static inline struct sctp_chunk *sctp_make_op_error_fixed( ++ const struct sctp_association *asoc, ++ const struct sctp_chunk *chunk) ++{ ++ size_t size = asoc ? asoc->pathmtu : 0; ++ ++ if (!size) ++ size = SCTP_DEFAULT_MAXSEGMENT; ++ ++ return sctp_make_op_error_space(asoc, chunk, size); ++} ++ + /* Create an Operation Error chunk. */ + struct sctp_chunk *sctp_make_op_error(const struct sctp_association *asoc, + const struct sctp_chunk *chunk, +@@ -1374,6 +1415,18 @@ void *sctp_addto_chunk(struct sctp_chunk *chunk, int len, const void *data) + return target; + } + ++/* Append bytes to the end of a chunk. Returns NULL if there isn't sufficient ++ * space in the chunk ++ */ ++void *sctp_addto_chunk_fixed(struct sctp_chunk *chunk, ++ int len, const void *data) ++{ ++ if (skb_tailroom(chunk->skb) > len) ++ return sctp_addto_chunk(chunk, len, data); ++ else ++ return NULL; ++} ++ + /* Append bytes from user space to the end of a chunk. Will panic if + * chunk is not big enough. + * Returns a kernel err value. +@@ -1977,13 +2030,12 @@ static sctp_ierror_t sctp_process_unk_param(const struct sctp_association *asoc, + * returning multiple unknown parameters. + */ + if (NULL == *errp) +- *errp = sctp_make_op_error_space(asoc, chunk, +- ntohs(chunk->chunk_hdr->length)); ++ *errp = sctp_make_op_error_fixed(asoc, chunk); + + if (*errp) { +- sctp_init_cause(*errp, SCTP_ERROR_UNKNOWN_PARAM, ++ sctp_init_cause_fixed(*errp, SCTP_ERROR_UNKNOWN_PARAM, + WORD_ROUND(ntohs(param.p->length))); +- sctp_addto_chunk(*errp, ++ sctp_addto_chunk_fixed(*errp, + WORD_ROUND(ntohs(param.p->length)), + param.v); + } else { diff --git a/debian/patches/bugfix/all/thinkpad-acpi-add-x100e.patch b/debian/patches/bugfix/all/thinkpad-acpi-add-x100e.patch new file mode 100644 index 000000000..75d13c546 --- /dev/null +++ b/debian/patches/bugfix/all/thinkpad-acpi-add-x100e.patch @@ -0,0 +1,16 @@ +From: Matthew Garrett +Date: Wed Apr 21 14:13:22 2010 UTC +Subject: Add EC path for Thinkpad X100 + + +diff -up linux-2.6.32.noarch/drivers/platform/x86/thinkpad_acpi.c.mjg linux-2.6.32.noarch/drivers/platform/x86/thinkpad_acpi.c +--- linux-2.6.32.noarch/drivers/platform/x86/thinkpad_acpi.c.mjg 2010-04-21 10:02:53.658034129 -0400 ++++ linux-2.6.32.noarch/drivers/platform/x86/thinkpad_acpi.c 2010-04-21 10:03:30.402030108 -0400 +@@ -491,6 +491,7 @@ TPACPI_HANDLE(ec, root, "\\_SB.PCI0.ISA. + "\\_SB.PCI0.ISA.EC", /* A21e, A2xm/p, T20-22, X20-21 */ + "\\_SB.PCI0.AD4S.EC0", /* i1400, R30 */ + "\\_SB.PCI0.ICH3.EC0", /* R31 */ ++ "\\_SB.PCI0.LPC0.EC", /* X100e */ + "\\_SB.PCI0.LPC.EC", /* all others */ + ); + diff --git a/debian/patches/bugfix/all/tipc-fix-oops-on-send-prior-to-entering-networked-mode.patch b/debian/patches/bugfix/all/tipc-fix-oops-on-send-prior-to-entering-networked-mode.patch new file mode 100644 index 000000000..9f95b59f4 --- /dev/null +++ b/debian/patches/bugfix/all/tipc-fix-oops-on-send-prior-to-entering-networked-mode.patch @@ -0,0 +1,209 @@ +commit d0021b252eaf65ca07ed14f0d66425dd9ccab9a6 +Author: Neil Horman +Date: Wed Mar 3 08:31:23 2010 +0000 + + tipc: Fix oops on send prior to entering networked mode (v3) + + Fix TIPC to disallow sending to remote addresses prior to entering NET_MODE + + user programs can oops the kernel by sending datagrams via AF_TIPC prior to + entering networked mode. The following backtrace has been observed: + + ID: 13459 TASK: ffff810014640040 CPU: 0 COMMAND: "tipc-client" + [exception RIP: tipc_node_select_next_hop+90] + RIP: ffffffff8869d3c3 RSP: ffff81002d9a5ab8 RFLAGS: 00010202 + RAX: 0000000000000001 RBX: 0000000000000001 RCX: 0000000000000001 + RDX: 0000000000000000 RSI: 0000000000000001 RDI: 0000000001001001 + RBP: 0000000001001001 R8: 0074736575716552 R9: 0000000000000000 + R10: ffff81003fbd0680 R11: 00000000000000c8 R12: 0000000000000008 + R13: 0000000000000001 R14: 0000000000000001 R15: ffff810015c6ca00 + ORIG_RAX: ffffffffffffffff CS: 0010 SS: 0018 + RIP: 0000003cbd8d49a3 RSP: 00007fffc84e0be8 RFLAGS: 00010206 + RAX: 000000000000002c RBX: ffffffff8005d116 RCX: 0000000000000000 + RDX: 0000000000000008 RSI: 00007fffc84e0c00 RDI: 0000000000000003 + RBP: 0000000000000000 R8: 00007fffc84e0c10 R9: 0000000000000010 + R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000000 + R13: 00007fffc84e0d10 R14: 0000000000000000 R15: 00007fffc84e0c30 + ORIG_RAX: 000000000000002c CS: 0033 SS: 002b + + What happens is that, when the tipc module in inserted it enters a standalone + node mode in which communication to its own address is allowed <0.0.0> but not + to other addresses, since the appropriate data structures have not been + allocated yet (specifically the tipc_net pointer). There is nothing stopping a + client from trying to send such a message however, and if that happens, we + attempt to dereference tipc_net.zones while the pointer is still NULL, and + explode. The fix is pretty straightforward. Since these oopses all arise from + the dereference of global pointers prior to their assignment to allocated + values, and since these allocations are small (about 2k total), lets convert + these pointers to static arrays of the appropriate size. All the accesses to + these bits consider 0/NULL to be a non match when searching, so all the lookups + still work properly, and there is no longer a chance of a bad dererence + anywhere. As a bonus, this lets us eliminate the setup/teardown routines for + those pointers, and elimnates the need to preform any locking around them to + prevent access while their being allocated/freed. + + I've updated the tipc_net structure to behave this way to fix the exact reported + problem, and also fixed up the tipc_bearers and media_list arrays to fix an + obvious simmilar problem that arises from issuing tipc-config commands to + manipulate bearers/links prior to entering networked mode + + I've tested this for a few hours by running the sanity tests and stress test + with the tipcutils suite, and nothing has fallen over. There have been a few + lockdep warnings, but those were there before, and can be addressed later, as + they didn't actually result in any deadlock. + + Signed-off-by: Neil Horman + CC: Allan Stephens + CC: David S. Miller + CC: tipc-discussion@lists.sourceforge.net + + bearer.c | 37 ++++++------------------------------- + bearer.h | 2 +- + net.c | 25 ++++--------------------- + 3 files changed, 11 insertions(+), 53 deletions(-) + Signed-off-by: David S. Miller + +diff --git a/net/tipc/bearer.c b/net/tipc/bearer.c +index 327011f..7809137 100644 +--- a/net/tipc/bearer.c ++++ b/net/tipc/bearer.c +@@ -45,10 +45,10 @@ + + #define MAX_ADDR_STR 32 + +-static struct media *media_list = NULL; ++static struct media media_list[MAX_MEDIA]; + static u32 media_count = 0; + +-struct bearer *tipc_bearers = NULL; ++struct bearer tipc_bearers[MAX_BEARERS]; + + /** + * media_name_valid - validate media name +@@ -108,9 +108,11 @@ int tipc_register_media(u32 media_type, + int res = -EINVAL; + + write_lock_bh(&tipc_net_lock); +- if (!media_list) +- goto exit; + ++ if (tipc_mode != TIPC_NET_MODE) { ++ warn("Media <%s> rejected, not in networked mode yet\n", name); ++ goto exit; ++ } + if (!media_name_valid(name)) { + warn("Media <%s> rejected, illegal name\n", name); + goto exit; +@@ -660,33 +662,10 @@ int tipc_disable_bearer(const char *name) + + + +-int tipc_bearer_init(void) +-{ +- int res; +- +- write_lock_bh(&tipc_net_lock); +- tipc_bearers = kcalloc(MAX_BEARERS, sizeof(struct bearer), GFP_ATOMIC); +- media_list = kcalloc(MAX_MEDIA, sizeof(struct media), GFP_ATOMIC); +- if (tipc_bearers && media_list) { +- res = 0; +- } else { +- kfree(tipc_bearers); +- kfree(media_list); +- tipc_bearers = NULL; +- media_list = NULL; +- res = -ENOMEM; +- } +- write_unlock_bh(&tipc_net_lock); +- return res; +-} +- + void tipc_bearer_stop(void) + { + u32 i; + +- if (!tipc_bearers) +- return; +- + for (i = 0; i < MAX_BEARERS; i++) { + if (tipc_bearers[i].active) + tipc_bearers[i].publ.blocked = 1; +@@ -695,10 +674,6 @@ void tipc_bearer_stop(void) + if (tipc_bearers[i].active) + bearer_disable(tipc_bearers[i].publ.name); + } +- kfree(tipc_bearers); +- kfree(media_list); +- tipc_bearers = NULL; +- media_list = NULL; + media_count = 0; + } + +diff --git a/net/tipc/bearer.h b/net/tipc/bearer.h +index ca57348..000228e 100644 +--- a/net/tipc/bearer.h ++++ b/net/tipc/bearer.h +@@ -114,7 +114,7 @@ struct bearer_name { + + struct link; + +-extern struct bearer *tipc_bearers; ++extern struct bearer tipc_bearers[]; + + void tipc_media_addr_printf(struct print_buf *pb, struct tipc_media_addr *a); + struct sk_buff *tipc_media_get_names(void); +diff --git a/net/tipc/net.c b/net/tipc/net.c +index 7906608..f25b1cd 100644 +--- a/net/tipc/net.c ++++ b/net/tipc/net.c +@@ -116,7 +116,8 @@ + */ + + DEFINE_RWLOCK(tipc_net_lock); +-struct network tipc_net = { NULL }; ++struct _zone *tipc_zones[256] = { NULL, }; ++struct network tipc_net = { tipc_zones }; + + struct tipc_node *tipc_net_select_remote_node(u32 addr, u32 ref) + { +@@ -158,28 +159,12 @@ void tipc_net_send_external_routes(u32 dest) + } + } + +-static int net_init(void) +-{ +- memset(&tipc_net, 0, sizeof(tipc_net)); +- tipc_net.zones = kcalloc(tipc_max_zones + 1, sizeof(struct _zone *), GFP_ATOMIC); +- if (!tipc_net.zones) { +- return -ENOMEM; +- } +- return 0; +-} +- + static void net_stop(void) + { + u32 z_num; + +- if (!tipc_net.zones) +- return; +- +- for (z_num = 1; z_num <= tipc_max_zones; z_num++) { ++ for (z_num = 1; z_num <= tipc_max_zones; z_num++) + tipc_zone_delete(tipc_net.zones[z_num]); +- } +- kfree(tipc_net.zones); +- tipc_net.zones = NULL; + } + + static void net_route_named_msg(struct sk_buff *buf) +@@ -282,9 +267,7 @@ int tipc_net_start(u32 addr) + tipc_named_reinit(); + tipc_port_reinit(); + +- if ((res = tipc_bearer_init()) || +- (res = net_init()) || +- (res = tipc_cltr_init()) || ++ if ((res = tipc_cltr_init()) || + (res = tipc_bclink_init())) { + return res; + } diff --git a/debian/patches/bugfix/mips/drm-ttm-build-fix.patch b/debian/patches/bugfix/mips/drm-ttm-build-fix.patch new file mode 100644 index 000000000..2e75117c1 --- /dev/null +++ b/debian/patches/bugfix/mips/drm-ttm-build-fix.patch @@ -0,0 +1,25 @@ +drm/ttm: Fix build failure due to missing struct page + +drm/ttm fails to build on MIPS because "struct page" is not known: +| In file included from drivers/gpu/drm/ttm/ttm_memory.c:28: +| include/drm/ttm/ttm_memory.h:154: warning: 'struct page' declared inside parameter list +| include/drm/ttm/ttm_memory.h:154: warning: its scope is only this definition or declaration, which is probably not what you want +| include/drm/ttm/ttm_memory.h:156: warning: 'struct page' declared inside parameter list +| drivers/gpu/drm/ttm/ttm_memory.c:540: error: conflicting types for 'ttm_mem_global_alloc_page' +| include/drm/ttm/ttm_memory.h:154: error: previous declaration of 'ttm_mem_global_alloc_page' was here +| drivers/gpu/drm/ttm/ttm_memory.c:561: error: conflicting types for 'ttm_mem_global_free_page' +| include/drm/ttm/ttm_memory.h:156: error: previous declaration of 'ttm_mem_global_free_page' was here + +Signed-off-by: Martin Michlmayr + +--- a/include/drm/ttm/ttm_memory.h ++++ b/include/drm/ttm/ttm_memory.h +@@ -33,6 +33,7 @@ + #include + #include + #include ++#include + + /** + * struct ttm_mem_shrink - callback to shrink TTM memory usage. + diff --git a/debian/patches/bugfix/mips/enable-pata-platform.patch b/debian/patches/bugfix/mips/enable-pata-platform.patch new file mode 100644 index 000000000..7774ac3ad --- /dev/null +++ b/debian/patches/bugfix/mips/enable-pata-platform.patch @@ -0,0 +1,36 @@ +From: Sebastian Andrzej Siewior +Subject: mips: enable PATA platform on SWARM and LITTLESUR + +according to include/asm/sibyte/swarm.h both systems provide a +platform device for the ide controler. Until now the IDE subsystem was +used which is deprecated by now. The same structure can be used with the +PATA driver. +This was tested on SWARM. + +Signed-off-by: Sebastian Andrzej Siewior +--- + arch/mips/Kconfig | 2 ++ + 1 files changed, 2 insertions(+), 0 deletions(-) + +diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig +index 29e8692..98628ec 100644 +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -499,6 +500,7 @@ config SIBYTE_SWARM + bool "Sibyte BCM91250A-SWARM" + select BOOT_ELF32 + select DMA_COHERENT ++ select HAVE_PATA_PLATFORM + select NR_CPUS_DEFAULT_2 + select SIBYTE_SB1250 + select SWAP_IO_SPACE +@@ -513,6 +514,7 @@ config SIBYTE_LITTLESUR + depends on EXPERIMENTAL + select BOOT_ELF32 + select DMA_COHERENT ++ select HAVE_PATA_PLATFORM + select NR_CPUS_DEFAULT_2 + select SIBYTE_SB1250 + select SWAP_IO_SPACE +-- +1.6.6.1 diff --git a/debian/patches/bugfix/powerpc/kgdb-dont-needlessly-skip-PAGE_USER-test-for-Fsl-booke.patch b/debian/patches/bugfix/powerpc/kgdb-dont-needlessly-skip-PAGE_USER-test-for-Fsl-booke.patch new file mode 100644 index 000000000..758531f43 --- /dev/null +++ b/debian/patches/bugfix/powerpc/kgdb-dont-needlessly-skip-PAGE_USER-test-for-Fsl-booke.patch @@ -0,0 +1,44 @@ +From 56151e753468e34aeb322af4b0309ab727c97d2e Mon Sep 17 00:00:00 2001 +From: Wufei +Date: Wed, 28 Apr 2010 17:42:32 -0400 +Subject: [PATCH] kgdb: don't needlessly skip PAGE_USER test for Fsl booke + +The bypassing of this test is a leftover from 2.4 vintage +kernels, and is no longer appropriate, or even used by KGDB. +Currently KGDB uses probe_kernel_write() for all access to +memory via the KGDB core, so it can simply be deleted. + +This fixes CVE-2010-1446. + +CC: Benjamin Herrenschmidt +CC: Paul Mackerras +CC: Kumar Gala +Signed-off-by: Wufei +Signed-off-by: Jason Wessel +--- + arch/powerpc/mm/fsl_booke_mmu.c | 5 ----- + 1 files changed, 0 insertions(+), 5 deletions(-) + +diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c +index c539472..1ce9dd5 100644 +--- a/arch/powerpc/mm/fsl_booke_mmu.c ++++ b/arch/powerpc/mm/fsl_booke_mmu.c +@@ -155,15 +155,10 @@ static void settlbcam(int index, unsigned long virt, phys_addr_t phys, + if (cur_cpu_spec->cpu_features & MMU_FTR_BIG_PHYS) + TLBCAM[index].MAS7 = (u64)phys >> 32; + +-#ifndef CONFIG_KGDB /* want user access for breakpoints */ + if (flags & _PAGE_USER) { + TLBCAM[index].MAS3 |= MAS3_UX | MAS3_UR; + TLBCAM[index].MAS3 |= ((flags & _PAGE_RW) ? MAS3_UW : 0); + } +-#else +- TLBCAM[index].MAS3 |= MAS3_UX | MAS3_UR; +- TLBCAM[index].MAS3 |= ((flags & _PAGE_RW) ? MAS3_UW : 0); +-#endif + + tlbcam_addrs[index].start = virt; + tlbcam_addrs[index].limit = virt + size - 1; +-- +1.7.0.3 + diff --git a/debian/patches/bugfix/x86/PCI-Disable-MSI-for-MCP55-on-P5N32-E-SLI.patch b/debian/patches/bugfix/x86/PCI-Disable-MSI-for-MCP55-on-P5N32-E-SLI.patch new file mode 100644 index 000000000..caad08aa0 --- /dev/null +++ b/debian/patches/bugfix/x86/PCI-Disable-MSI-for-MCP55-on-P5N32-E-SLI.patch @@ -0,0 +1,42 @@ +From c0613ff21bef2595aebd8f33f36e52a7528e8cb0 Mon Sep 17 00:00:00 2001 +From: Ben Hutchings +Date: Wed, 7 Apr 2010 03:22:51 +0100 +Subject: [PATCH] PCI: Disable MSI for MCP55 on P5N32-E SLI + +As reported in , MSI appears to be +broken for this on-board device. We already have a quirk for the +P5N32-SLI Premium; extend it to cover both variants of the board. + +Reported-by: Romain DEGEZ +Signed-off-by: Ben Hutchings +--- + drivers/pci/quirks.c | 7 ++++--- + 1 files changed, 4 insertions(+), 3 deletions(-) + +diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c +index 27c0e6e..4807825 100644 +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -2218,15 +2218,16 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, + ht_enable_msi_mapping); + +-/* The P5N32-SLI Premium motherboard from Asus has a problem with msi ++/* The P5N32-SLI motherboards from Asus have a problem with msi + * for the MCP55 NIC. It is not yet determined whether the msi problem + * also affects other devices. As for now, turn off msi for this device. + */ + static void __devinit nvenet_msi_disable(struct pci_dev *dev) + { +- if (dmi_name_in_vendors("P5N32-SLI PREMIUM")) { ++ if (dmi_name_in_vendors("P5N32-SLI PREMIUM") || ++ dmi_name_in_vendors("P5N32-E SLI")) { + dev_info(&dev->dev, +- "Disabling msi for MCP55 NIC on P5N32-SLI Premium\n"); ++ "Disabling msi for MCP55 NIC on P5N32-SLI\n"); + dev->no_msi = 1; + } + } +-- +1.7.0.3 + diff --git a/debian/patches/features/all/drm-radeon-evergreen.patch b/debian/patches/features/all/drm-radeon-evergreen.patch new file mode 100644 index 000000000..ac608851e --- /dev/null +++ b/debian/patches/features/all/drm-radeon-evergreen.patch @@ -0,0 +1,11729 @@ +From: Dave Airlie +Date: Thu Apr 8 03:08:33 2010 UTC +Subject: Backport radeon r800 modesetting support +diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile +index 1cc7b93..83c5907 100644 +--- a/drivers/gpu/drm/radeon/Makefile ++++ b/drivers/gpu/drm/radeon/Makefile +@@ -54,7 +54,8 @@ radeon-y += radeon_device.o radeon_kms.o \ + radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \ + rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \ + r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \ +- r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o ++ r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \ ++ evergreen.o + + radeon-$(CONFIG_COMPAT) += radeon_ioc32.o + +diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c +index d75788f..b7fe660 100644 +--- a/drivers/gpu/drm/radeon/atom.c ++++ b/drivers/gpu/drm/radeon/atom.c +@@ -52,15 +52,17 @@ + + typedef struct { + struct atom_context *ctx; +- + uint32_t *ps, *ws; + int ps_shift; + uint16_t start; ++ unsigned last_jump; ++ unsigned long last_jump_jiffies; ++ bool abort; + } atom_exec_context; + + int atom_debug = 0; +-static void atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params); +-void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params); ++static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params); ++int atom_execute_table(struct atom_context *ctx, int index, uint32_t * params); + + static uint32_t atom_arg_mask[8] = + { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000, +@@ -604,12 +606,17 @@ static void atom_op_beep(atom_exec_context *ctx, int *ptr, int arg) + static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg) + { + int idx = U8((*ptr)++); ++ int r = 0; ++ + if (idx < ATOM_TABLE_NAMES_CNT) + SDEBUG(" table: %d (%s)\n", idx, atom_table_names[idx]); + else + SDEBUG(" table: %d\n", idx); + if (U16(ctx->ctx->cmd_table + 4 + 2 * idx)) +- atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift); ++ r = atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift); ++ if (r) { ++ ctx->abort = true; ++ } + } + + static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg) +@@ -673,6 +680,8 @@ static void atom_op_eot(atom_exec_context *ctx, int *ptr, int arg) + static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg) + { + int execute = 0, target = U16(*ptr); ++ unsigned long cjiffies; ++ + (*ptr) += 2; + switch (arg) { + case ATOM_COND_ABOVE: +@@ -700,8 +709,25 @@ static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg) + if (arg != ATOM_COND_ALWAYS) + SDEBUG(" taken: %s\n", execute ? "yes" : "no"); + SDEBUG(" target: 0x%04X\n", target); +- if (execute) ++ if (execute) { ++ if (ctx->last_jump == (ctx->start + target)) { ++ cjiffies = jiffies; ++ if (time_after(cjiffies, ctx->last_jump_jiffies)) { ++ cjiffies -= ctx->last_jump_jiffies; ++ if ((jiffies_to_msecs(cjiffies) > 1000)) { ++ DRM_ERROR("atombios stuck in loop for more than 1sec aborting\n"); ++ ctx->abort = true; ++ } ++ } else { ++ /* jiffies wrap around we will just wait a little longer */ ++ ctx->last_jump_jiffies = jiffies; ++ } ++ } else { ++ ctx->last_jump = ctx->start + target; ++ ctx->last_jump_jiffies = jiffies; ++ } + *ptr = ctx->start + target; ++ } + } + + static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg) +@@ -1104,7 +1130,7 @@ static struct { + atom_op_shr, ATOM_ARG_MC}, { + atom_op_debug, 0},}; + +-static void atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params) ++static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params) + { + int base = CU16(ctx->cmd_table + 4 + 2 * index); + int len, ws, ps, ptr; +@@ -1112,7 +1138,7 @@ static void atom_execute_table_locked(struct atom_context *ctx, int index, uint3 + atom_exec_context ectx; + + if (!base) +- return; ++ return -EINVAL; + + len = CU16(base + ATOM_CT_SIZE_PTR); + ws = CU8(base + ATOM_CT_WS_PTR); +@@ -1125,6 +1151,8 @@ static void atom_execute_table_locked(struct atom_context *ctx, int index, uint3 + ectx.ps_shift = ps / 4; + ectx.start = base; + ectx.ps = params; ++ ectx.abort = false; ++ ectx.last_jump = 0; + if (ws) + ectx.ws = kzalloc(4 * ws, GFP_KERNEL); + else +@@ -1137,6 +1165,11 @@ static void atom_execute_table_locked(struct atom_context *ctx, int index, uint3 + SDEBUG("%s @ 0x%04X\n", atom_op_names[op], ptr - 1); + else + SDEBUG("[%d] @ 0x%04X\n", op, ptr - 1); ++ if (ectx.abort) { ++ DRM_ERROR("atombios stuck executing %04X (len %d, WS %d, PS %d) @ 0x%04X\n", ++ base, len, ws, ps, ptr - 1); ++ return -EINVAL; ++ } + + if (op < ATOM_OP_CNT && op > 0) + opcode_table[op].func(&ectx, &ptr, +@@ -1152,10 +1185,13 @@ static void atom_execute_table_locked(struct atom_context *ctx, int index, uint3 + + if (ws) + kfree(ectx.ws); ++ return 0; + } + +-void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params) ++int atom_execute_table(struct atom_context *ctx, int index, uint32_t * params) + { ++ int r; ++ + mutex_lock(&ctx->mutex); + /* reset reg block */ + ctx->reg_block = 0; +@@ -1163,8 +1199,9 @@ void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params) + ctx->fb_base = 0; + /* reset io mode */ + ctx->io_mode = ATOM_IO_MM; +- atom_execute_table_locked(ctx, index, params); ++ r = atom_execute_table_locked(ctx, index, params); + mutex_unlock(&ctx->mutex); ++ return r; + } + + static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 }; +@@ -1248,9 +1285,7 @@ int atom_asic_init(struct atom_context *ctx) + + if (!CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_INIT)) + return 1; +- atom_execute_table(ctx, ATOM_CMD_INIT, ps); +- +- return 0; ++ return atom_execute_table(ctx, ATOM_CMD_INIT, ps); + } + + void atom_destroy(struct atom_context *ctx) +diff --git a/drivers/gpu/drm/radeon/atom.h b/drivers/gpu/drm/radeon/atom.h +index bc73781..1b26263 100644 +--- a/drivers/gpu/drm/radeon/atom.h ++++ b/drivers/gpu/drm/radeon/atom.h +@@ -140,7 +140,7 @@ struct atom_context { + extern int atom_debug; + + struct atom_context *atom_parse(struct card_info *, void *); +-void atom_execute_table(struct atom_context *, int, uint32_t *); ++int atom_execute_table(struct atom_context *, int, uint32_t *); + int atom_asic_init(struct atom_context *); + void atom_destroy(struct atom_context *); + void atom_parse_data_header(struct atom_context *ctx, int index, uint16_t *size, uint8_t *frev, uint8_t *crev, uint16_t *data_start); +diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h +index 91ad0d1..6732b5d 100644 +--- a/drivers/gpu/drm/radeon/atombios.h ++++ b/drivers/gpu/drm/radeon/atombios.h +@@ -1,5 +1,5 @@ + /* +- * Copyright 2006-2007 Advanced Micro Devices, Inc. ++ * Copyright 2006-2007 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), +@@ -20,10 +20,12 @@ + * OTHER DEALINGS IN THE SOFTWARE. + */ + +-/****************************************************************************/ ++ ++/****************************************************************************/ + /*Portion I: Definitions shared between VBIOS and Driver */ + /****************************************************************************/ + ++ + #ifndef _ATOMBIOS_H + #define _ATOMBIOS_H + +@@ -40,39 +42,46 @@ + #endif + + #ifdef _H2INC +-#ifndef ULONG +-typedef unsigned long ULONG; +-#endif ++ #ifndef ULONG ++ typedef unsigned long ULONG; ++ #endif + +-#ifndef UCHAR +-typedef unsigned char UCHAR; +-#endif ++ #ifndef UCHAR ++ typedef unsigned char UCHAR; ++ #endif + +-#ifndef USHORT +-typedef unsigned short USHORT; +-#endif ++ #ifndef USHORT ++ typedef unsigned short USHORT; ++ #endif + #endif +- +-#define ATOM_DAC_A 0 ++ ++#define ATOM_DAC_A 0 + #define ATOM_DAC_B 1 + #define ATOM_EXT_DAC 2 + + #define ATOM_CRTC1 0 + #define ATOM_CRTC2 1 ++#define ATOM_CRTC3 2 ++#define ATOM_CRTC4 3 ++#define ATOM_CRTC5 4 ++#define ATOM_CRTC6 5 ++#define ATOM_CRTC_INVALID 0xFF + + #define ATOM_DIGA 0 + #define ATOM_DIGB 1 + + #define ATOM_PPLL1 0 + #define ATOM_PPLL2 1 ++#define ATOM_DCPLL 2 ++#define ATOM_PPLL_INVALID 0xFF + + #define ATOM_SCALER1 0 + #define ATOM_SCALER2 1 + +-#define ATOM_SCALER_DISABLE 0 +-#define ATOM_SCALER_CENTER 1 +-#define ATOM_SCALER_EXPANSION 2 +-#define ATOM_SCALER_MULTI_EX 3 ++#define ATOM_SCALER_DISABLE 0 ++#define ATOM_SCALER_CENTER 1 ++#define ATOM_SCALER_EXPANSION 2 ++#define ATOM_SCALER_MULTI_EX 3 + + #define ATOM_DISABLE 0 + #define ATOM_ENABLE 1 +@@ -82,6 +91,7 @@ typedef unsigned short USHORT; + #define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5) + #define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5) + #define ATOM_ENCODER_INIT (ATOM_DISABLE+7) ++#define ATOM_GET_STATUS (ATOM_DISABLE+8) + + #define ATOM_BLANKING 1 + #define ATOM_BLANKING_OFF 0 +@@ -114,7 +124,7 @@ typedef unsigned short USHORT; + #define ATOM_DAC2_CV ATOM_DAC1_CV + #define ATOM_DAC2_NTSC ATOM_DAC1_NTSC + #define ATOM_DAC2_PAL ATOM_DAC1_PAL +- ++ + #define ATOM_PM_ON 0 + #define ATOM_PM_STANDBY 1 + #define ATOM_PM_SUSPEND 2 +@@ -134,6 +144,7 @@ typedef unsigned short USHORT; + #define ATOM_PANEL_MISC_TEMPORAL 0x00000040 + #define ATOM_PANEL_MISC_API_ENABLED 0x00000080 + ++ + #define MEMTYPE_DDR1 "DDR1" + #define MEMTYPE_DDR2 "DDR2" + #define MEMTYPE_DDR3 "DDR3" +@@ -145,19 +156,19 @@ typedef unsigned short USHORT; + + /* Maximum size of that FireGL flag string */ + +-#define ATOM_FIREGL_FLAG_STRING "FGL" /* Flag used to enable FireGL Support */ +-#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 /* sizeof( ATOM_FIREGL_FLAG_STRING ) */ ++#define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support ++#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING ) + +-#define ATOM_FAKE_DESKTOP_STRING "DSK" /* Flag used to enable mobile ASIC on Desktop */ +-#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING ++#define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop ++#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING + +-#define ATOM_M54T_FLAG_STRING "M54T" /* Flag used to enable M54T Support */ +-#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 /* sizeof( ATOM_M54T_FLAG_STRING ) */ ++#define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support ++#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) + + #define HW_ASSISTED_I2C_STATUS_FAILURE 2 + #define HW_ASSISTED_I2C_STATUS_SUCCESS 1 + +-#pragma pack(1) /* BIOS data must use byte aligment */ ++#pragma pack(1) /* BIOS data must use byte aligment */ + + /* Define offset to location of ROM header. */ + +@@ -165,367 +176,410 @@ typedef unsigned short USHORT; + #define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L + + #define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94 +-#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */ ++#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */ + #define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f + #define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e + + /* Common header for all ROM Data tables. +- Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. ++ Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. + And the pointer actually points to this header. */ + +-typedef struct _ATOM_COMMON_TABLE_HEADER { +- USHORT usStructureSize; +- UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */ +- UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */ +- /*Image can't be updated, while Driver needs to carry the new table! */ +-} ATOM_COMMON_TABLE_HEADER; +- +-typedef struct _ATOM_ROM_HEADER { +- ATOM_COMMON_TABLE_HEADER sHeader; +- UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, +- atombios should init it as "ATOM", don't change the position */ +- USHORT usBiosRuntimeSegmentAddress; +- USHORT usProtectedModeInfoOffset; +- USHORT usConfigFilenameOffset; +- USHORT usCRC_BlockOffset; +- USHORT usBIOS_BootupMessageOffset; +- USHORT usInt10Offset; +- USHORT usPciBusDevInitCode; +- USHORT usIoBaseAddress; +- USHORT usSubsystemVendorID; +- USHORT usSubsystemID; +- USHORT usPCI_InfoOffset; +- USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */ +- USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */ +- UCHAR ucExtendedFunctionCode; +- UCHAR ucReserved; +-} ATOM_ROM_HEADER; ++typedef struct _ATOM_COMMON_TABLE_HEADER ++{ ++ USHORT usStructureSize; ++ UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */ ++ UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */ ++ /*Image can't be updated, while Driver needs to carry the new table! */ ++}ATOM_COMMON_TABLE_HEADER; ++ ++typedef struct _ATOM_ROM_HEADER ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, ++ atombios should init it as "ATOM", don't change the position */ ++ USHORT usBiosRuntimeSegmentAddress; ++ USHORT usProtectedModeInfoOffset; ++ USHORT usConfigFilenameOffset; ++ USHORT usCRC_BlockOffset; ++ USHORT usBIOS_BootupMessageOffset; ++ USHORT usInt10Offset; ++ USHORT usPciBusDevInitCode; ++ USHORT usIoBaseAddress; ++ USHORT usSubsystemVendorID; ++ USHORT usSubsystemID; ++ USHORT usPCI_InfoOffset; ++ USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */ ++ USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */ ++ UCHAR ucExtendedFunctionCode; ++ UCHAR ucReserved; ++}ATOM_ROM_HEADER; + + /*==============================Command Table Portion==================================== */ + + #ifdef UEFI_BUILD +-#define UTEMP USHORT +-#define USHORT void* ++ #define UTEMP USHORT ++ #define USHORT void* + #endif + +-typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES { +- USHORT ASIC_Init; /* Function Table, used by various SW components,latest version 1.1 */ +- USHORT GetDisplaySurfaceSize; /* Atomic Table, Used by Bios when enabling HW ICON */ +- USHORT ASIC_RegistersInit; /* Atomic Table, indirectly used by various SW components,called from ASIC_Init */ +- USHORT VRAM_BlockVenderDetection; /* Atomic Table, used only by Bios */ +- USHORT DIGxEncoderControl; /* Only used by Bios */ +- USHORT MemoryControllerInit; /* Atomic Table, indirectly used by various SW components,called from ASIC_Init */ +- USHORT EnableCRTCMemReq; /* Function Table,directly used by various SW components,latest version 2.1 */ +- USHORT MemoryParamAdjust; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed */ +- USHORT DVOEncoderControl; /* Function Table,directly used by various SW components,latest version 1.2 */ +- USHORT GPIOPinControl; /* Atomic Table, only used by Bios */ +- USHORT SetEngineClock; /*Function Table,directly used by various SW components,latest version 1.1 */ +- USHORT SetMemoryClock; /* Function Table,directly used by various SW components,latest version 1.1 */ +- USHORT SetPixelClock; /*Function Table,directly used by various SW components,latest version 1.2 */ +- USHORT DynamicClockGating; /* Atomic Table, indirectly used by various SW components,called from ASIC_Init */ +- USHORT ResetMemoryDLL; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */ +- USHORT ResetMemoryDevice; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */ +- USHORT MemoryPLLInit; +- USHORT AdjustDisplayPll; /* only used by Bios */ +- USHORT AdjustMemoryController; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */ +- USHORT EnableASIC_StaticPwrMgt; /* Atomic Table, only used by Bios */ +- USHORT ASIC_StaticPwrMgtStatusChange; /* Obsolete, only used by Bios */ +- USHORT DAC_LoadDetection; /* Atomic Table, directly used by various SW components,latest version 1.2 */ +- USHORT LVTMAEncoderControl; /* Atomic Table,directly used by various SW components,latest version 1.3 */ +- USHORT LCD1OutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ +- USHORT DAC1EncoderControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ +- USHORT DAC2EncoderControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ +- USHORT DVOOutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ +- USHORT CV1OutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ +- USHORT GetConditionalGoldenSetting; /* only used by Bios */ +- USHORT TVEncoderControl; /* Function Table,directly used by various SW components,latest version 1.1 */ +- USHORT TMDSAEncoderControl; /* Atomic Table, directly used by various SW components,latest version 1.3 */ +- USHORT LVDSEncoderControl; /* Atomic Table, directly used by various SW components,latest version 1.3 */ +- USHORT TV1OutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ +- USHORT EnableScaler; /* Atomic Table, used only by Bios */ +- USHORT BlankCRTC; /* Atomic Table, directly used by various SW components,latest version 1.1 */ +- USHORT EnableCRTC; /* Atomic Table, directly used by various SW components,latest version 1.1 */ +- USHORT GetPixelClock; /* Atomic Table, directly used by various SW components,latest version 1.1 */ +- USHORT EnableVGA_Render; /* Function Table,directly used by various SW components,latest version 1.1 */ +- USHORT EnableVGA_Access; /* Obsolete , only used by Bios */ +- USHORT SetCRTC_Timing; /* Atomic Table, directly used by various SW components,latest version 1.1 */ +- USHORT SetCRTC_OverScan; /* Atomic Table, used by various SW components,latest version 1.1 */ +- USHORT SetCRTC_Replication; /* Atomic Table, used only by Bios */ +- USHORT SelectCRTC_Source; /* Atomic Table, directly used by various SW components,latest version 1.1 */ +- USHORT EnableGraphSurfaces; /* Atomic Table, used only by Bios */ +- USHORT UpdateCRTC_DoubleBufferRegisters; +- USHORT LUT_AutoFill; /* Atomic Table, only used by Bios */ +- USHORT EnableHW_IconCursor; /* Atomic Table, only used by Bios */ +- USHORT GetMemoryClock; /* Atomic Table, directly used by various SW components,latest version 1.1 */ +- USHORT GetEngineClock; /* Atomic Table, directly used by various SW components,latest version 1.1 */ +- USHORT SetCRTC_UsingDTDTiming; /* Atomic Table, directly used by various SW components,latest version 1.1 */ +- USHORT ExternalEncoderControl; /* Atomic Table, directly used by various SW components,latest version 2.1 */ +- USHORT LVTMAOutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ +- USHORT VRAM_BlockDetectionByStrap; /* Atomic Table, used only by Bios */ +- USHORT MemoryCleanUp; /* Atomic Table, only used by Bios */ +- USHORT ProcessI2cChannelTransaction; /* Function Table,only used by Bios */ +- USHORT WriteOneByteToHWAssistedI2C; /* Function Table,indirectly used by various SW components */ +- USHORT ReadHWAssistedI2CStatus; /* Atomic Table, indirectly used by various SW components */ +- USHORT SpeedFanControl; /* Function Table,indirectly used by various SW components,called from ASIC_Init */ +- USHORT PowerConnectorDetection; /* Atomic Table, directly used by various SW components,latest version 1.1 */ +- USHORT MC_Synchronization; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */ +- USHORT ComputeMemoryEnginePLL; /* Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock */ +- USHORT MemoryRefreshConversion; /* Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock */ +- USHORT VRAM_GetCurrentInfoBlock; /* Atomic Table, used only by Bios */ +- USHORT DynamicMemorySettings; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */ +- USHORT MemoryTraining; /* Atomic Table, used only by Bios */ +- USHORT EnableSpreadSpectrumOnPPLL; /* Atomic Table, directly used by various SW components,latest version 1.2 */ +- USHORT TMDSAOutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ +- USHORT SetVoltage; /* Function Table,directly and/or indirectly used by various SW components,latest version 1.1 */ +- USHORT DAC1OutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ +- USHORT DAC2OutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ +- USHORT SetupHWAssistedI2CStatus; /* Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" */ +- USHORT ClockSource; /* Atomic Table, indirectly used by various SW components,called from ASIC_Init */ +- USHORT MemoryDeviceInit; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */ +- USHORT EnableYUV; /* Atomic Table, indirectly used by various SW components,called from EnableVGARender */ +- USHORT DIG1EncoderControl; /* Atomic Table,directly used by various SW components,latest version 1.1 */ +- USHORT DIG2EncoderControl; /* Atomic Table,directly used by various SW components,latest version 1.1 */ +- USHORT DIG1TransmitterControl; /* Atomic Table,directly used by various SW components,latest version 1.1 */ +- USHORT DIG2TransmitterControl; /* Atomic Table,directly used by various SW components,latest version 1.1 */ +- USHORT ProcessAuxChannelTransaction; /* Function Table,only used by Bios */ +- USHORT DPEncoderService; /* Function Table,only used by Bios */ +-} ATOM_MASTER_LIST_OF_COMMAND_TABLES; +- +-/* For backward compatible */ ++typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ ++ USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 ++ USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON ++ USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init ++ USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios ++ USHORT DIGxEncoderControl; //Only used by Bios ++ USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init ++ USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1 ++ USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed ++ USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2 ++ USHORT GPIOPinControl; //Atomic Table, only used by Bios ++ USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1 ++ USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1 ++ USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 ++ USHORT DynamicClockGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init ++ USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock ++ USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock ++ USHORT MemoryPLLInit; ++ USHORT AdjustDisplayPll; //only used by Bios ++ USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock ++ USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios ++ USHORT ASIC_StaticPwrMgtStatusChange; //Obsolete , only used by Bios ++ USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 ++ USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3 ++ USHORT LCD1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead ++ USHORT GetConditionalGoldenSetting; //only used by Bios ++ USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1 ++ USHORT TMDSAEncoderControl; //Atomic Table, directly used by various SW components,latest version 1.3 ++ USHORT LVDSEncoderControl; //Atomic Table, directly used by various SW components,latest version 1.3 ++ USHORT TV1OutputControl; //Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead ++ USHORT EnableScaler; //Atomic Table, used only by Bios ++ USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1 ++ USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios ++ USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 ++ USHORT SetCRTC_Replication; //Atomic Table, used only by Bios ++ USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios ++ USHORT UpdateCRTC_DoubleBufferRegisters; ++ USHORT LUT_AutoFill; //Atomic Table, only used by Bios ++ USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios ++ USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1 ++ USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios ++ USHORT MemoryCleanUp; //Atomic Table, only used by Bios ++ USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios ++ USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components ++ USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components ++ USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init ++ USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock ++ USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock ++ USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock ++ USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios ++ USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock ++ USHORT MemoryTraining; //Atomic Table, used only by Bios ++ USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2 ++ USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1 ++ USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT DAC2OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 ++ USHORT SetupHWAssistedI2CStatus; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" ++ USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init ++ USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock ++ USHORT EnableYUV; //Atomic Table, indirectly used by various SW components,called from EnableVGARender ++ USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 ++ USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 ++ USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 ++ USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 ++ USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios ++ USHORT DPEncoderService; //Function Table,only used by Bios ++}ATOM_MASTER_LIST_OF_COMMAND_TABLES; ++ ++// For backward compatible + #define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction + #define UNIPHYTransmitterControl DIG1TransmitterControl + #define LVTMATransmitterControl DIG2TransmitterControl + #define SetCRTC_DPM_State GetConditionalGoldenSetting + #define SetUniphyInstance ASIC_StaticPwrMgtStatusChange ++#define HPDInterruptService ReadHWAssistedI2CStatus ++#define EnableVGA_Access GetSCLKOverMCLKRatio + +-typedef struct _ATOM_MASTER_COMMAND_TABLE { +- ATOM_COMMON_TABLE_HEADER sHeader; +- ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; +-} ATOM_MASTER_COMMAND_TABLE; +- +-/****************************************************************************/ +-/* Structures used in every command table */ +-/****************************************************************************/ +-typedef struct _ATOM_TABLE_ATTRIBUTE { ++typedef struct _ATOM_MASTER_COMMAND_TABLE ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; ++}ATOM_MASTER_COMMAND_TABLE; ++ ++/****************************************************************************/ ++// Structures used in every command table ++/****************************************************************************/ ++typedef struct _ATOM_TABLE_ATTRIBUTE ++{ + #if ATOM_BIG_ENDIAN +- USHORT UpdatedByUtility:1; /* [15]=Table updated by utility flag */ +- USHORT PS_SizeInBytes:7; /* [14:8]=Size of parameter space in Bytes (multiple of a dword), */ +- USHORT WS_SizeInBytes:8; /* [7:0]=Size of workspace in Bytes (in multiple of a dword), */ ++ USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag ++ USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), ++ USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), + #else +- USHORT WS_SizeInBytes:8; /* [7:0]=Size of workspace in Bytes (in multiple of a dword), */ +- USHORT PS_SizeInBytes:7; /* [14:8]=Size of parameter space in Bytes (multiple of a dword), */ +- USHORT UpdatedByUtility:1; /* [15]=Table updated by utility flag */ ++ USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), ++ USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), ++ USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag + #endif +-} ATOM_TABLE_ATTRIBUTE; +- +-typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS { +- ATOM_TABLE_ATTRIBUTE sbfAccess; +- USHORT susAccess; +-} ATOM_TABLE_ATTRIBUTE_ACCESS; ++}ATOM_TABLE_ATTRIBUTE; + +-/****************************************************************************/ +-/* Common header for all command tables. */ +-/* Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. */ +-/* And the pointer actually points to this header. */ +-/****************************************************************************/ +-typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER { +- ATOM_COMMON_TABLE_HEADER CommonHeader; +- ATOM_TABLE_ATTRIBUTE TableAttribute; +-} ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; ++typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS ++{ ++ ATOM_TABLE_ATTRIBUTE sbfAccess; ++ USHORT susAccess; ++}ATOM_TABLE_ATTRIBUTE_ACCESS; ++ ++/****************************************************************************/ ++// Common header for all command tables. ++// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. ++// And the pointer actually points to this header. ++/****************************************************************************/ ++typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER ++{ ++ ATOM_COMMON_TABLE_HEADER CommonHeader; ++ ATOM_TABLE_ATTRIBUTE TableAttribute; ++}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; + +-/****************************************************************************/ +-/* Structures used by ComputeMemoryEnginePLLTable */ +-/****************************************************************************/ ++/****************************************************************************/ ++// Structures used by ComputeMemoryEnginePLLTable ++/****************************************************************************/ + #define COMPUTE_MEMORY_PLL_PARAM 1 + #define COMPUTE_ENGINE_PLL_PARAM 2 + +-typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS { +- ULONG ulClock; /* When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div */ +- UCHAR ucAction; /* 0:reserved //1:Memory //2:Engine */ +- UCHAR ucReserved; /* may expand to return larger Fbdiv later */ +- UCHAR ucFbDiv; /* return value */ +- UCHAR ucPostDiv; /* return value */ +-} COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; +- +-typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 { +- ULONG ulClock; /* When return, [23:0] return real clock */ +- UCHAR ucAction; /* 0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register */ +- USHORT usFbDiv; /* return Feedback value to be written to register */ +- UCHAR ucPostDiv; /* return post div to be written to register */ +-} COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; ++typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS ++{ ++ ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div ++ UCHAR ucAction; //0:reserved //1:Memory //2:Engine ++ UCHAR ucReserved; //may expand to return larger Fbdiv later ++ UCHAR ucFbDiv; //return value ++ UCHAR ucPostDiv; //return value ++}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; ++ ++typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 ++{ ++ ULONG ulClock; //When return, [23:0] return real clock ++ UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register ++ USHORT usFbDiv; //return Feedback value to be written to register ++ UCHAR ucPostDiv; //return post div to be written to register ++}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; + #define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS + +-#define SET_CLOCK_FREQ_MASK 0x00FFFFFF /* Clock change tables only take bit [23:0] as the requested clock value */ +-#define USE_NON_BUS_CLOCK_MASK 0x01000000 /* Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) */ +-#define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 /* Only applicable to memory clock change, when set, using memory self refresh during clock transition */ +-#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 /* Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change */ +-#define FIRST_TIME_CHANGE_CLOCK 0x08000000 /* Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup */ +-#define SKIP_SW_PROGRAM_PLL 0x10000000 /* Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL */ ++ ++#define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value ++#define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) ++#define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition ++#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change ++#define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup ++#define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL + #define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK + +-#define b3USE_NON_BUS_CLOCK_MASK 0x01 /* Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) */ +-#define b3USE_MEMORY_SELF_REFRESH 0x02 /* Only applicable to memory clock change, when set, using memory self refresh during clock transition */ +-#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 /* Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change */ +-#define b3FIRST_TIME_CHANGE_CLOCK 0x08 /* Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup */ +-#define b3SKIP_SW_PROGRAM_PLL 0x10 /* Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL */ ++#define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) ++#define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition ++#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change ++#define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup ++#define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL + +-typedef struct _ATOM_COMPUTE_CLOCK_FREQ { ++typedef struct _ATOM_COMPUTE_CLOCK_FREQ ++{ + #if ATOM_BIG_ENDIAN +- ULONG ulComputeClockFlag:8; /* =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM */ +- ULONG ulClockFreq:24; /* in unit of 10kHz */ ++ ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM ++ ULONG ulClockFreq:24; // in unit of 10kHz + #else +- ULONG ulClockFreq:24; /* in unit of 10kHz */ +- ULONG ulComputeClockFlag:8; /* =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM */ ++ ULONG ulClockFreq:24; // in unit of 10kHz ++ ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM + #endif +-} ATOM_COMPUTE_CLOCK_FREQ; +- +-typedef struct _ATOM_S_MPLL_FB_DIVIDER { +- USHORT usFbDivFrac; +- USHORT usFbDiv; +-} ATOM_S_MPLL_FB_DIVIDER; ++}ATOM_COMPUTE_CLOCK_FREQ; + +-typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 { +- union { +- ATOM_COMPUTE_CLOCK_FREQ ulClock; /* Input Parameter */ +- ATOM_S_MPLL_FB_DIVIDER ulFbDiv; /* Output Parameter */ +- }; +- UCHAR ucRefDiv; /* Output Parameter */ +- UCHAR ucPostDiv; /* Output Parameter */ +- UCHAR ucCntlFlag; /* Output Parameter */ +- UCHAR ucReserved; +-} COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; ++typedef struct _ATOM_S_MPLL_FB_DIVIDER ++{ ++ USHORT usFbDivFrac; ++ USHORT usFbDiv; ++}ATOM_S_MPLL_FB_DIVIDER; + +-/* ucCntlFlag */ ++typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 ++{ ++ union ++ { ++ ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter ++ ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter ++ }; ++ UCHAR ucRefDiv; //Output Parameter ++ UCHAR ucPostDiv; //Output Parameter ++ UCHAR ucCntlFlag; //Output Parameter ++ UCHAR ucReserved; ++}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; ++ ++// ucCntlFlag + #define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1 + #define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2 + #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4 ++#define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8 + +-typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER { +- ATOM_COMPUTE_CLOCK_FREQ ulClock; +- ULONG ulReserved[2]; +-} DYNAMICE_MEMORY_SETTINGS_PARAMETER; +- +-typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER { +- ATOM_COMPUTE_CLOCK_FREQ ulClock; +- ULONG ulMemoryClock; +- ULONG ulReserved; +-} DYNAMICE_ENGINE_SETTINGS_PARAMETER; +- +-/****************************************************************************/ +-/* Structures used by SetEngineClockTable */ +-/****************************************************************************/ +-typedef struct _SET_ENGINE_CLOCK_PARAMETERS { +- ULONG ulTargetEngineClock; /* In 10Khz unit */ +-} SET_ENGINE_CLOCK_PARAMETERS; + +-typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION { +- ULONG ulTargetEngineClock; /* In 10Khz unit */ +- COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; +-} SET_ENGINE_CLOCK_PS_ALLOCATION; ++// V4 are only used for APU which PLL outside GPU ++typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ++{ ++#if ATOM_BIG_ENDIAN ++ ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly ++ ULONG ulClock:24; //Input= target clock, output = actual clock ++#else ++ ULONG ulClock:24; //Input= target clock, output = actual clock ++ ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly ++#endif ++}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; + +-/****************************************************************************/ +-/* Structures used by SetMemoryClockTable */ +-/****************************************************************************/ +-typedef struct _SET_MEMORY_CLOCK_PARAMETERS { +- ULONG ulTargetMemoryClock; /* In 10Khz unit */ +-} SET_MEMORY_CLOCK_PARAMETERS; ++typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER ++{ ++ ATOM_COMPUTE_CLOCK_FREQ ulClock; ++ ULONG ulReserved[2]; ++}DYNAMICE_MEMORY_SETTINGS_PARAMETER; + +-typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION { +- ULONG ulTargetMemoryClock; /* In 10Khz unit */ +- COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; +-} SET_MEMORY_CLOCK_PS_ALLOCATION; ++typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER ++{ ++ ATOM_COMPUTE_CLOCK_FREQ ulClock; ++ ULONG ulMemoryClock; ++ ULONG ulReserved; ++}DYNAMICE_ENGINE_SETTINGS_PARAMETER; ++ ++/****************************************************************************/ ++// Structures used by SetEngineClockTable ++/****************************************************************************/ ++typedef struct _SET_ENGINE_CLOCK_PARAMETERS ++{ ++ ULONG ulTargetEngineClock; //In 10Khz unit ++}SET_ENGINE_CLOCK_PARAMETERS; + +-/****************************************************************************/ +-/* Structures used by ASIC_Init.ctb */ +-/****************************************************************************/ +-typedef struct _ASIC_INIT_PARAMETERS { +- ULONG ulDefaultEngineClock; /* In 10Khz unit */ +- ULONG ulDefaultMemoryClock; /* In 10Khz unit */ +-} ASIC_INIT_PARAMETERS; ++typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION ++{ ++ ULONG ulTargetEngineClock; //In 10Khz unit ++ COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; ++}SET_ENGINE_CLOCK_PS_ALLOCATION; ++ ++/****************************************************************************/ ++// Structures used by SetMemoryClockTable ++/****************************************************************************/ ++typedef struct _SET_MEMORY_CLOCK_PARAMETERS ++{ ++ ULONG ulTargetMemoryClock; //In 10Khz unit ++}SET_MEMORY_CLOCK_PARAMETERS; + +-typedef struct _ASIC_INIT_PS_ALLOCATION { +- ASIC_INIT_PARAMETERS sASICInitClocks; +- SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; /* Caller doesn't need to init this structure */ +-} ASIC_INIT_PS_ALLOCATION; ++typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION ++{ ++ ULONG ulTargetMemoryClock; //In 10Khz unit ++ COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; ++}SET_MEMORY_CLOCK_PS_ALLOCATION; ++ ++/****************************************************************************/ ++// Structures used by ASIC_Init.ctb ++/****************************************************************************/ ++typedef struct _ASIC_INIT_PARAMETERS ++{ ++ ULONG ulDefaultEngineClock; //In 10Khz unit ++ ULONG ulDefaultMemoryClock; //In 10Khz unit ++}ASIC_INIT_PARAMETERS; + +-/****************************************************************************/ +-/* Structure used by DynamicClockGatingTable.ctb */ +-/****************************************************************************/ +-typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS { +- UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ +- UCHAR ucPadding[3]; +-} DYNAMIC_CLOCK_GATING_PARAMETERS; ++typedef struct _ASIC_INIT_PS_ALLOCATION ++{ ++ ASIC_INIT_PARAMETERS sASICInitClocks; ++ SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure ++}ASIC_INIT_PS_ALLOCATION; ++ ++/****************************************************************************/ ++// Structure used by DynamicClockGatingTable.ctb ++/****************************************************************************/ ++typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS ++{ ++ UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE ++ UCHAR ucPadding[3]; ++}DYNAMIC_CLOCK_GATING_PARAMETERS; + #define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS + +-/****************************************************************************/ +-/* Structure used by EnableASIC_StaticPwrMgtTable.ctb */ +-/****************************************************************************/ +-typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS { +- UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ +- UCHAR ucPadding[3]; +-} ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; ++/****************************************************************************/ ++// Structure used by EnableASIC_StaticPwrMgtTable.ctb ++/****************************************************************************/ ++typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS ++{ ++ UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE ++ UCHAR ucPadding[3]; ++}ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; + #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS + +-/****************************************************************************/ +-/* Structures used by DAC_LoadDetectionTable.ctb */ +-/****************************************************************************/ +-typedef struct _DAC_LOAD_DETECTION_PARAMETERS { +- USHORT usDeviceID; /* {ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} */ +- UCHAR ucDacType; /* {ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} */ +- UCHAR ucMisc; /* Valid only when table revision =1.3 and above */ +-} DAC_LOAD_DETECTION_PARAMETERS; ++/****************************************************************************/ ++// Structures used by DAC_LoadDetectionTable.ctb ++/****************************************************************************/ ++typedef struct _DAC_LOAD_DETECTION_PARAMETERS ++{ ++ USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} ++ UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} ++ UCHAR ucMisc; //Valid only when table revision =1.3 and above ++}DAC_LOAD_DETECTION_PARAMETERS; + +-/* DAC_LOAD_DETECTION_PARAMETERS.ucMisc */ ++// DAC_LOAD_DETECTION_PARAMETERS.ucMisc + #define DAC_LOAD_MISC_YPrPb 0x01 + +-typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION { +- DAC_LOAD_DETECTION_PARAMETERS sDacload; +- ULONG Reserved[2]; /* Don't set this one, allocation for EXT DAC */ +-} DAC_LOAD_DETECTION_PS_ALLOCATION; +- +-/****************************************************************************/ +-/* Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb */ +-/****************************************************************************/ +-typedef struct _DAC_ENCODER_CONTROL_PARAMETERS { +- USHORT usPixelClock; /* in 10KHz; for bios convenient */ +- UCHAR ucDacStandard; /* See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) */ +- UCHAR ucAction; /* 0: turn off encoder */ +- /* 1: setup and turn on encoder */ +- /* 7: ATOM_ENCODER_INIT Initialize DAC */ +-} DAC_ENCODER_CONTROL_PARAMETERS; ++typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION ++{ ++ DAC_LOAD_DETECTION_PARAMETERS sDacload; ++ ULONG Reserved[2];// Don't set this one, allocation for EXT DAC ++}DAC_LOAD_DETECTION_PS_ALLOCATION; ++ ++/****************************************************************************/ ++// Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb ++/****************************************************************************/ ++typedef struct _DAC_ENCODER_CONTROL_PARAMETERS ++{ ++ USHORT usPixelClock; // in 10KHz; for bios convenient ++ UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) ++ UCHAR ucAction; // 0: turn off encoder ++ // 1: setup and turn on encoder ++ // 7: ATOM_ENCODER_INIT Initialize DAC ++}DAC_ENCODER_CONTROL_PARAMETERS; + + #define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS + +-/****************************************************************************/ +-/* Structures used by DIG1EncoderControlTable */ +-/* DIG2EncoderControlTable */ +-/* ExternalEncoderControlTable */ +-/****************************************************************************/ +-typedef struct _DIG_ENCODER_CONTROL_PARAMETERS { +- USHORT usPixelClock; /* in 10KHz; for bios convenient */ +- UCHAR ucConfig; +- /* [2] Link Select: */ +- /* =0: PHY linkA if bfLane<3 */ +- /* =1: PHY linkB if bfLanes<3 */ +- /* =0: PHY linkA+B if bfLanes=3 */ +- /* [3] Transmitter Sel */ +- /* =0: UNIPHY or PCIEPHY */ +- /* =1: LVTMA */ +- UCHAR ucAction; /* =0: turn off encoder */ +- /* =1: turn on encoder */ +- UCHAR ucEncoderMode; +- /* =0: DP encoder */ +- /* =1: LVDS encoder */ +- /* =2: DVI encoder */ +- /* =3: HDMI encoder */ +- /* =4: SDVO encoder */ +- UCHAR ucLaneNum; /* how many lanes to enable */ +- UCHAR ucReserved[2]; +-} DIG_ENCODER_CONTROL_PARAMETERS; ++/****************************************************************************/ ++// Structures used by DIG1EncoderControlTable ++// DIG2EncoderControlTable ++// ExternalEncoderControlTable ++/****************************************************************************/ ++typedef struct _DIG_ENCODER_CONTROL_PARAMETERS ++{ ++ USHORT usPixelClock; // in 10KHz; for bios convenient ++ UCHAR ucConfig; ++ // [2] Link Select: ++ // =0: PHY linkA if bfLane<3 ++ // =1: PHY linkB if bfLanes<3 ++ // =0: PHY linkA+B if bfLanes=3 ++ // [3] Transmitter Sel ++ // =0: UNIPHY or PCIEPHY ++ // =1: LVTMA ++ UCHAR ucAction; // =0: turn off encoder ++ // =1: turn on encoder ++ UCHAR ucEncoderMode; ++ // =0: DP encoder ++ // =1: LVDS encoder ++ // =2: DVI encoder ++ // =3: HDMI encoder ++ // =4: SDVO encoder ++ UCHAR ucLaneNum; // how many lanes to enable ++ UCHAR ucReserved[2]; ++}DIG_ENCODER_CONTROL_PARAMETERS; + #define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS + #define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS + +-/* ucConfig */ ++//ucConfig + #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 + #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 + #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 +@@ -539,52 +593,57 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS { + #define ATOM_ENCODER_CONFIG_LVTMA 0x08 + #define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00 + #define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08 +-#define ATOM_ENCODER_CONFIG_DIGB 0x80 /* VBIOS Internal use, outside SW should set this bit=0 */ +-/* ucAction */ +-/* ATOM_ENABLE: Enable Encoder */ +-/* ATOM_DISABLE: Disable Encoder */ ++#define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0 ++// ucAction ++// ATOM_ENABLE: Enable Encoder ++// ATOM_DISABLE: Disable Encoder + +-/* ucEncoderMode */ ++//ucEncoderMode + #define ATOM_ENCODER_MODE_DP 0 + #define ATOM_ENCODER_MODE_LVDS 1 + #define ATOM_ENCODER_MODE_DVI 2 + #define ATOM_ENCODER_MODE_HDMI 3 + #define ATOM_ENCODER_MODE_SDVO 4 ++#define ATOM_ENCODER_MODE_DP_AUDIO 5 + #define ATOM_ENCODER_MODE_TV 13 + #define ATOM_ENCODER_MODE_CV 14 + #define ATOM_ENCODER_MODE_CRT 15 + +-typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 { ++typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 ++{ + #if ATOM_BIG_ENDIAN +- UCHAR ucReserved1:2; +- UCHAR ucTransmitterSel:2; /* =0: UniphyAB, =1: UniphyCD =2: UniphyEF */ +- UCHAR ucLinkSel:1; /* =0: linkA/C/E =1: linkB/D/F */ +- UCHAR ucReserved:1; +- UCHAR ucDPLinkRate:1; /* =0: 1.62Ghz, =1: 2.7Ghz */ ++ UCHAR ucReserved1:2; ++ UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF ++ UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F ++ UCHAR ucReserved:1; ++ UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz + #else +- UCHAR ucDPLinkRate:1; /* =0: 1.62Ghz, =1: 2.7Ghz */ +- UCHAR ucReserved:1; +- UCHAR ucLinkSel:1; /* =0: linkA/C/E =1: linkB/D/F */ +- UCHAR ucTransmitterSel:2; /* =0: UniphyAB, =1: UniphyCD =2: UniphyEF */ +- UCHAR ucReserved1:2; ++ UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz ++ UCHAR ucReserved:1; ++ UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F ++ UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF ++ UCHAR ucReserved1:2; + #endif +-} ATOM_DIG_ENCODER_CONFIG_V2; ++}ATOM_DIG_ENCODER_CONFIG_V2; + +-typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 { +- USHORT usPixelClock; /* in 10KHz; for bios convenient */ +- ATOM_DIG_ENCODER_CONFIG_V2 acConfig; +- UCHAR ucAction; +- UCHAR ucEncoderMode; +- /* =0: DP encoder */ +- /* =1: LVDS encoder */ +- /* =2: DVI encoder */ +- /* =3: HDMI encoder */ +- /* =4: SDVO encoder */ +- UCHAR ucLaneNum; /* how many lanes to enable */ +- UCHAR ucReserved[2]; +-} DIG_ENCODER_CONTROL_PARAMETERS_V2; + +-/* ucConfig */ ++typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 ++{ ++ USHORT usPixelClock; // in 10KHz; for bios convenient ++ ATOM_DIG_ENCODER_CONFIG_V2 acConfig; ++ UCHAR ucAction; ++ UCHAR ucEncoderMode; ++ // =0: DP encoder ++ // =1: LVDS encoder ++ // =2: DVI encoder ++ // =3: HDMI encoder ++ // =4: SDVO encoder ++ UCHAR ucLaneNum; // how many lanes to enable ++ UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS ++ UCHAR ucReserved; ++}DIG_ENCODER_CONTROL_PARAMETERS_V2; ++ ++//ucConfig + #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01 + #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00 + #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01 +@@ -596,58 +655,122 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 { + #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08 + #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10 + +-/****************************************************************************/ +-/* Structures used by UNIPHYTransmitterControlTable */ +-/* LVTMATransmitterControlTable */ +-/* DVOOutputControlTable */ +-/****************************************************************************/ +-typedef struct _ATOM_DP_VS_MODE { +- UCHAR ucLaneSel; +- UCHAR ucLaneSet; +-} ATOM_DP_VS_MODE; +- +-typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS { +- union { +- USHORT usPixelClock; /* in 10KHz; for bios convenient */ +- USHORT usInitInfo; /* when init uniphy,lower 8bit is used for connector type defined in objectid.h */ +- ATOM_DP_VS_MODE asMode; /* DP Voltage swing mode */ ++// ucAction: ++// ATOM_DISABLE ++// ATOM_ENABLE ++#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08 ++#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09 ++#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a ++#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b ++#define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c ++#define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d ++#define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e ++#define ATOM_ENCODER_CMD_SETUP 0x0f ++ ++// ucStatus ++#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 ++#define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00 ++ ++// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver ++typedef struct _ATOM_DIG_ENCODER_CONFIG_V3 ++{ ++#if ATOM_BIG_ENDIAN ++ UCHAR ucReserved1:1; ++ UCHAR ucDigSel:3; // =0: DIGA/B/C/D/E/F ++ UCHAR ucReserved:3; ++ UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz ++#else ++ UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz ++ UCHAR ucReserved:3; ++ UCHAR ucDigSel:3; // =0: DIGA/B/C/D/E/F ++ UCHAR ucReserved1:1; ++#endif ++}ATOM_DIG_ENCODER_CONFIG_V3; ++ ++#define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70 ++ ++ ++typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 ++{ ++ USHORT usPixelClock; // in 10KHz; for bios convenient ++ ATOM_DIG_ENCODER_CONFIG_V3 acConfig; ++ UCHAR ucAction; ++ UCHAR ucEncoderMode; ++ // =0: DP encoder ++ // =1: LVDS encoder ++ // =2: DVI encoder ++ // =3: HDMI encoder ++ // =4: SDVO encoder ++ // =5: DP audio ++ UCHAR ucLaneNum; // how many lanes to enable ++ UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP ++ UCHAR ucReserved; ++}DIG_ENCODER_CONTROL_PARAMETERS_V3; ++ ++ ++// define ucBitPerColor: ++#define PANEL_BPC_UNDEFINE 0x00 ++#define PANEL_6BIT_PER_COLOR 0x01 ++#define PANEL_8BIT_PER_COLOR 0x02 ++#define PANEL_10BIT_PER_COLOR 0x03 ++#define PANEL_12BIT_PER_COLOR 0x04 ++#define PANEL_16BIT_PER_COLOR 0x05 ++ ++/****************************************************************************/ ++// Structures used by UNIPHYTransmitterControlTable ++// LVTMATransmitterControlTable ++// DVOOutputControlTable ++/****************************************************************************/ ++typedef struct _ATOM_DP_VS_MODE ++{ ++ UCHAR ucLaneSel; ++ UCHAR ucLaneSet; ++}ATOM_DP_VS_MODE; ++ ++typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS ++{ ++ union ++ { ++ USHORT usPixelClock; // in 10KHz; for bios convenient ++ USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h ++ ATOM_DP_VS_MODE asMode; // DP Voltage swing mode + }; +- UCHAR ucConfig; +- /* [0]=0: 4 lane Link, */ +- /* =1: 8 lane Link ( Dual Links TMDS ) */ +- /* [1]=0: InCoherent mode */ +- /* =1: Coherent Mode */ +- /* [2] Link Select: */ +- /* =0: PHY linkA if bfLane<3 */ +- /* =1: PHY linkB if bfLanes<3 */ +- /* =0: PHY linkA+B if bfLanes=3 */ +- /* [5:4]PCIE lane Sel */ +- /* =0: lane 0~3 or 0~7 */ +- /* =1: lane 4~7 */ +- /* =2: lane 8~11 or 8~15 */ +- /* =3: lane 12~15 */ +- UCHAR ucAction; /* =0: turn off encoder */ +- /* =1: turn on encoder */ +- UCHAR ucReserved[4]; +-} DIG_TRANSMITTER_CONTROL_PARAMETERS; +- +-#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS +- +-/* ucInitInfo */ +-#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff +- +-/* ucConfig */ ++ UCHAR ucConfig; ++ // [0]=0: 4 lane Link, ++ // =1: 8 lane Link ( Dual Links TMDS ) ++ // [1]=0: InCoherent mode ++ // =1: Coherent Mode ++ // [2] Link Select: ++ // =0: PHY linkA if bfLane<3 ++ // =1: PHY linkB if bfLanes<3 ++ // =0: PHY linkA+B if bfLanes=3 ++ // [5:4]PCIE lane Sel ++ // =0: lane 0~3 or 0~7 ++ // =1: lane 4~7 ++ // =2: lane 8~11 or 8~15 ++ // =3: lane 12~15 ++ UCHAR ucAction; // =0: turn off encoder ++ // =1: turn on encoder ++ UCHAR ucReserved[4]; ++}DIG_TRANSMITTER_CONTROL_PARAMETERS; ++ ++#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS ++ ++//ucInitInfo ++#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff ++ ++//ucConfig + #define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 + #define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 + #define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 + #define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 + #define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 +-#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 ++#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 + #define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04 + +-#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 /* only used when ATOM_TRANSMITTER_ACTION_ENABLE */ +-#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 /* only used when ATOM_TRANSMITTER_ACTION_ENABLE */ +-#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 /* only used when ATOM_TRANSMITTER_ACTION_ENABLE */ ++#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE ++#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE ++#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE + + #define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30 + #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00 +@@ -661,7 +784,7 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS { + #define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80 + #define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0 + +-/* ucAction */ ++//ucAction + #define ATOM_TRANSMITTER_ACTION_DISABLE 0 + #define ATOM_TRANSMITTER_ACTION_ENABLE 1 + #define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2 +@@ -674,93 +797,168 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS { + #define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9 + #define ATOM_TRANSMITTER_ACTION_SETUP 10 + #define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11 ++#define ATOM_TRANSMITTER_ACTION_POWER_ON 12 ++#define ATOM_TRANSMITTER_ACTION_POWER_OFF 13 + +-/* Following are used for DigTransmitterControlTable ver1.2 */ +-typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 { ++// Following are used for DigTransmitterControlTable ver1.2 ++typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 ++{ + #if ATOM_BIG_ENDIAN +- UCHAR ucTransmitterSel:2; /* bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) */ +- /* =1 Dig Transmitter 2 ( Uniphy CD ) */ +- /* =2 Dig Transmitter 3 ( Uniphy EF ) */ +- UCHAR ucReserved:1; +- UCHAR fDPConnector:1; /* bit4=0: DP connector =1: None DP connector */ +- UCHAR ucEncoderSel:1; /* bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) */ +- UCHAR ucLinkSel:1; /* bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E */ +- /* =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F */ +- +- UCHAR fCoherentMode:1; /* bit1=1: Coherent Mode ( for DVI/HDMI mode ) */ +- UCHAR fDualLinkConnector:1; /* bit0=1: Dual Link DVI connector */ ++ UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) ++ // =1 Dig Transmitter 2 ( Uniphy CD ) ++ // =2 Dig Transmitter 3 ( Uniphy EF ) ++ UCHAR ucReserved:1; ++ UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector ++ UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) ++ UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E ++ // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F ++ ++ UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) ++ UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector + #else +- UCHAR fDualLinkConnector:1; /* bit0=1: Dual Link DVI connector */ +- UCHAR fCoherentMode:1; /* bit1=1: Coherent Mode ( for DVI/HDMI mode ) */ +- UCHAR ucLinkSel:1; /* bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E */ +- /* =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F */ +- UCHAR ucEncoderSel:1; /* bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) */ +- UCHAR fDPConnector:1; /* bit4=0: DP connector =1: None DP connector */ +- UCHAR ucReserved:1; +- UCHAR ucTransmitterSel:2; /* bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) */ +- /* =1 Dig Transmitter 2 ( Uniphy CD ) */ +- /* =2 Dig Transmitter 3 ( Uniphy EF ) */ ++ UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector ++ UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) ++ UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E ++ // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F ++ UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) ++ UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector ++ UCHAR ucReserved:1; ++ UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) ++ // =1 Dig Transmitter 2 ( Uniphy CD ) ++ // =2 Dig Transmitter 3 ( Uniphy EF ) + #endif +-} ATOM_DIG_TRANSMITTER_CONFIG_V2; ++}ATOM_DIG_TRANSMITTER_CONFIG_V2; + +-/* ucConfig */ +-/* Bit0 */ ++//ucConfig ++//Bit0 + #define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01 + +-/* Bit1 */ ++//Bit1 + #define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02 + +-/* Bit2 */ ++//Bit2 + #define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04 +-#define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00 ++#define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00 + #define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04 + +-/* Bit3 */ ++// Bit3 + #define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08 +-#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 /* only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP */ +-#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 /* only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP */ ++#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP ++#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP + +-/* Bit4 */ ++// Bit4 + #define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10 + +-/* Bit7:6 */ ++// Bit7:6 + #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0 +-#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 /* AB */ +-#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 /* CD */ +-#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 /* EF */ +- +-typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 { +- union { +- USHORT usPixelClock; /* in 10KHz; for bios convenient */ +- USHORT usInitInfo; /* when init uniphy,lower 8bit is used for connector type defined in objectid.h */ +- ATOM_DP_VS_MODE asMode; /* DP Voltage swing mode */ ++#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB ++#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD ++#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF ++ ++typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 ++{ ++ union ++ { ++ USHORT usPixelClock; // in 10KHz; for bios convenient ++ USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h ++ ATOM_DP_VS_MODE asMode; // DP Voltage swing mode + }; +- ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig; +- UCHAR ucAction; /* define as ATOM_TRANSMITER_ACTION_XXX */ +- UCHAR ucReserved[4]; +-} DIG_TRANSMITTER_CONTROL_PARAMETERS_V2; ++ ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig; ++ UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX ++ UCHAR ucReserved[4]; ++}DIG_TRANSMITTER_CONTROL_PARAMETERS_V2; + +-/****************************************************************************/ +-/* Structures used by DAC1OuputControlTable */ +-/* DAC2OuputControlTable */ +-/* LVTMAOutputControlTable (Before DEC30) */ +-/* TMDSAOutputControlTable (Before DEC30) */ +-/****************************************************************************/ +-typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS { +- UCHAR ucAction; /* Possible input:ATOM_ENABLE||ATOMDISABLE */ +- /* When the display is LCD, in addition to above: */ +- /* ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| */ +- /* ATOM_LCD_SELFTEST_STOP */ ++typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3 ++{ ++#if ATOM_BIG_ENDIAN ++ UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) ++ // =1 Dig Transmitter 2 ( Uniphy CD ) ++ // =2 Dig Transmitter 3 ( Uniphy EF ) ++ UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 ++ UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F ++ UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E ++ // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F ++ UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) ++ UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector ++#else ++ UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector ++ UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) ++ UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E ++ // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F ++ UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F ++ UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 ++ UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) ++ // =1 Dig Transmitter 2 ( Uniphy CD ) ++ // =2 Dig Transmitter 3 ( Uniphy EF ) ++#endif ++}ATOM_DIG_TRANSMITTER_CONFIG_V3; + +- UCHAR aucPadding[3]; /* padding to DWORD aligned */ +-} DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; ++typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 ++{ ++ union ++ { ++ USHORT usPixelClock; // in 10KHz; for bios convenient ++ USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h ++ ATOM_DP_VS_MODE asMode; // DP Voltage swing mode ++ }; ++ ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig; ++ UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX ++ UCHAR ucLaneNum; ++ UCHAR ucReserved[3]; ++}DIG_TRANSMITTER_CONTROL_PARAMETERS_V3; ++ ++//ucConfig ++//Bit0 ++#define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01 ++ ++//Bit1 ++#define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02 ++ ++//Bit2 ++#define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04 ++#define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00 ++#define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04 ++ ++// Bit3 ++#define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08 ++#define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00 ++#define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08 ++ ++// Bit5:4 ++#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30 ++#define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00 ++#define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10 ++#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20 ++ ++// Bit7:6 ++#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0 ++#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB ++#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD ++#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF ++ ++/****************************************************************************/ ++// Structures used by DAC1OuputControlTable ++// DAC2OuputControlTable ++// LVTMAOutputControlTable (Before DEC30) ++// TMDSAOutputControlTable (Before DEC30) ++/****************************************************************************/ ++typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS ++{ ++ UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE ++ // When the display is LCD, in addition to above: ++ // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| ++ // ATOM_LCD_SELFTEST_STOP ++ ++ UCHAR aucPadding[3]; // padding to DWORD aligned ++}DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; + + #define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS + +-#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS ++ ++#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS + #define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION + +-#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS ++#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS + #define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION + + #define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +@@ -782,397 +980,550 @@ typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS { + #define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION + #define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS + +-/****************************************************************************/ +-/* Structures used by BlankCRTCTable */ +-/****************************************************************************/ +-typedef struct _BLANK_CRTC_PARAMETERS { +- UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ +- UCHAR ucBlanking; /* ATOM_BLANKING or ATOM_BLANKINGOFF */ +- USHORT usBlackColorRCr; +- USHORT usBlackColorGY; +- USHORT usBlackColorBCb; +-} BLANK_CRTC_PARAMETERS; ++/****************************************************************************/ ++// Structures used by BlankCRTCTable ++/****************************************************************************/ ++typedef struct _BLANK_CRTC_PARAMETERS ++{ ++ UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 ++ UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF ++ USHORT usBlackColorRCr; ++ USHORT usBlackColorGY; ++ USHORT usBlackColorBCb; ++}BLANK_CRTC_PARAMETERS; + #define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS + +-/****************************************************************************/ +-/* Structures used by EnableCRTCTable */ +-/* EnableCRTCMemReqTable */ +-/* UpdateCRTC_DoubleBufferRegistersTable */ +-/****************************************************************************/ +-typedef struct _ENABLE_CRTC_PARAMETERS { +- UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ +- UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ +- UCHAR ucPadding[2]; +-} ENABLE_CRTC_PARAMETERS; ++/****************************************************************************/ ++// Structures used by EnableCRTCTable ++// EnableCRTCMemReqTable ++// UpdateCRTC_DoubleBufferRegistersTable ++/****************************************************************************/ ++typedef struct _ENABLE_CRTC_PARAMETERS ++{ ++ UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 ++ UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE ++ UCHAR ucPadding[2]; ++}ENABLE_CRTC_PARAMETERS; + #define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS + +-/****************************************************************************/ +-/* Structures used by SetCRTC_OverScanTable */ +-/****************************************************************************/ +-typedef struct _SET_CRTC_OVERSCAN_PARAMETERS { +- USHORT usOverscanRight; /* right */ +- USHORT usOverscanLeft; /* left */ +- USHORT usOverscanBottom; /* bottom */ +- USHORT usOverscanTop; /* top */ +- UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ +- UCHAR ucPadding[3]; +-} SET_CRTC_OVERSCAN_PARAMETERS; ++/****************************************************************************/ ++// Structures used by SetCRTC_OverScanTable ++/****************************************************************************/ ++typedef struct _SET_CRTC_OVERSCAN_PARAMETERS ++{ ++ USHORT usOverscanRight; // right ++ USHORT usOverscanLeft; // left ++ USHORT usOverscanBottom; // bottom ++ USHORT usOverscanTop; // top ++ UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 ++ UCHAR ucPadding[3]; ++}SET_CRTC_OVERSCAN_PARAMETERS; + #define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS + +-/****************************************************************************/ +-/* Structures used by SetCRTC_ReplicationTable */ +-/****************************************************************************/ +-typedef struct _SET_CRTC_REPLICATION_PARAMETERS { +- UCHAR ucH_Replication; /* horizontal replication */ +- UCHAR ucV_Replication; /* vertical replication */ +- UCHAR usCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ +- UCHAR ucPadding; +-} SET_CRTC_REPLICATION_PARAMETERS; ++/****************************************************************************/ ++// Structures used by SetCRTC_ReplicationTable ++/****************************************************************************/ ++typedef struct _SET_CRTC_REPLICATION_PARAMETERS ++{ ++ UCHAR ucH_Replication; // horizontal replication ++ UCHAR ucV_Replication; // vertical replication ++ UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2 ++ UCHAR ucPadding; ++}SET_CRTC_REPLICATION_PARAMETERS; + #define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS + +-/****************************************************************************/ +-/* Structures used by SelectCRTC_SourceTable */ +-/****************************************************************************/ +-typedef struct _SELECT_CRTC_SOURCE_PARAMETERS { +- UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ +- UCHAR ucDevice; /* ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... */ +- UCHAR ucPadding[2]; +-} SELECT_CRTC_SOURCE_PARAMETERS; ++/****************************************************************************/ ++// Structures used by SelectCRTC_SourceTable ++/****************************************************************************/ ++typedef struct _SELECT_CRTC_SOURCE_PARAMETERS ++{ ++ UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 ++ UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... ++ UCHAR ucPadding[2]; ++}SELECT_CRTC_SOURCE_PARAMETERS; + #define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS + +-typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 { +- UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ +- UCHAR ucEncoderID; /* DAC1/DAC2/TVOUT/DIG1/DIG2/DVO */ +- UCHAR ucEncodeMode; /* Encoding mode, only valid when using DIG1/DIG2/DVO */ +- UCHAR ucPadding; +-} SELECT_CRTC_SOURCE_PARAMETERS_V2; +- +-/* ucEncoderID */ +-/* #define ASIC_INT_DAC1_ENCODER_ID 0x00 */ +-/* #define ASIC_INT_TV_ENCODER_ID 0x02 */ +-/* #define ASIC_INT_DIG1_ENCODER_ID 0x03 */ +-/* #define ASIC_INT_DAC2_ENCODER_ID 0x04 */ +-/* #define ASIC_EXT_TV_ENCODER_ID 0x06 */ +-/* #define ASIC_INT_DVO_ENCODER_ID 0x07 */ +-/* #define ASIC_INT_DIG2_ENCODER_ID 0x09 */ +-/* #define ASIC_EXT_DIG_ENCODER_ID 0x05 */ +- +-/* ucEncodeMode */ +-/* #define ATOM_ENCODER_MODE_DP 0 */ +-/* #define ATOM_ENCODER_MODE_LVDS 1 */ +-/* #define ATOM_ENCODER_MODE_DVI 2 */ +-/* #define ATOM_ENCODER_MODE_HDMI 3 */ +-/* #define ATOM_ENCODER_MODE_SDVO 4 */ +-/* #define ATOM_ENCODER_MODE_TV 13 */ +-/* #define ATOM_ENCODER_MODE_CV 14 */ +-/* #define ATOM_ENCODER_MODE_CRT 15 */ +- +-/****************************************************************************/ +-/* Structures used by SetPixelClockTable */ +-/* GetPixelClockTable */ +-/****************************************************************************/ +-/* Major revision=1., Minor revision=1 */ +-typedef struct _PIXEL_CLOCK_PARAMETERS { +- USHORT usPixelClock; /* in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) */ +- /* 0 means disable PPLL */ +- USHORT usRefDiv; /* Reference divider */ +- USHORT usFbDiv; /* feedback divider */ +- UCHAR ucPostDiv; /* post divider */ +- UCHAR ucFracFbDiv; /* fractional feedback divider */ +- UCHAR ucPpll; /* ATOM_PPLL1 or ATOM_PPL2 */ +- UCHAR ucRefDivSrc; /* ATOM_PJITTER or ATO_NONPJITTER */ +- UCHAR ucCRTC; /* Which CRTC uses this Ppll */ +- UCHAR ucPadding; +-} PIXEL_CLOCK_PARAMETERS; +- +-/* Major revision=1., Minor revision=2, add ucMiscIfno */ +-/* ucMiscInfo: */ ++typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 ++{ ++ UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 ++ UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO ++ UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO ++ UCHAR ucPadding; ++}SELECT_CRTC_SOURCE_PARAMETERS_V2; ++ ++//ucEncoderID ++//#define ASIC_INT_DAC1_ENCODER_ID 0x00 ++//#define ASIC_INT_TV_ENCODER_ID 0x02 ++//#define ASIC_INT_DIG1_ENCODER_ID 0x03 ++//#define ASIC_INT_DAC2_ENCODER_ID 0x04 ++//#define ASIC_EXT_TV_ENCODER_ID 0x06 ++//#define ASIC_INT_DVO_ENCODER_ID 0x07 ++//#define ASIC_INT_DIG2_ENCODER_ID 0x09 ++//#define ASIC_EXT_DIG_ENCODER_ID 0x05 ++ ++//ucEncodeMode ++//#define ATOM_ENCODER_MODE_DP 0 ++//#define ATOM_ENCODER_MODE_LVDS 1 ++//#define ATOM_ENCODER_MODE_DVI 2 ++//#define ATOM_ENCODER_MODE_HDMI 3 ++//#define ATOM_ENCODER_MODE_SDVO 4 ++//#define ATOM_ENCODER_MODE_TV 13 ++//#define ATOM_ENCODER_MODE_CV 14 ++//#define ATOM_ENCODER_MODE_CRT 15 ++ ++/****************************************************************************/ ++// Structures used by SetPixelClockTable ++// GetPixelClockTable ++/****************************************************************************/ ++//Major revision=1., Minor revision=1 ++typedef struct _PIXEL_CLOCK_PARAMETERS ++{ ++ USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) ++ // 0 means disable PPLL ++ USHORT usRefDiv; // Reference divider ++ USHORT usFbDiv; // feedback divider ++ UCHAR ucPostDiv; // post divider ++ UCHAR ucFracFbDiv; // fractional feedback divider ++ UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 ++ UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER ++ UCHAR ucCRTC; // Which CRTC uses this Ppll ++ UCHAR ucPadding; ++}PIXEL_CLOCK_PARAMETERS; ++ ++//Major revision=1., Minor revision=2, add ucMiscIfno ++//ucMiscInfo: + #define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1 + #define MISC_DEVICE_INDEX_MASK 0xF0 + #define MISC_DEVICE_INDEX_SHIFT 4 + +-typedef struct _PIXEL_CLOCK_PARAMETERS_V2 { +- USHORT usPixelClock; /* in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) */ +- /* 0 means disable PPLL */ +- USHORT usRefDiv; /* Reference divider */ +- USHORT usFbDiv; /* feedback divider */ +- UCHAR ucPostDiv; /* post divider */ +- UCHAR ucFracFbDiv; /* fractional feedback divider */ +- UCHAR ucPpll; /* ATOM_PPLL1 or ATOM_PPL2 */ +- UCHAR ucRefDivSrc; /* ATOM_PJITTER or ATO_NONPJITTER */ +- UCHAR ucCRTC; /* Which CRTC uses this Ppll */ +- UCHAR ucMiscInfo; /* Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog */ +-} PIXEL_CLOCK_PARAMETERS_V2; +- +-/* Major revision=1., Minor revision=3, structure/definition change */ +-/* ucEncoderMode: */ +-/* ATOM_ENCODER_MODE_DP */ +-/* ATOM_ENOCDER_MODE_LVDS */ +-/* ATOM_ENOCDER_MODE_DVI */ +-/* ATOM_ENOCDER_MODE_HDMI */ +-/* ATOM_ENOCDER_MODE_SDVO */ +-/* ATOM_ENCODER_MODE_TV 13 */ +-/* ATOM_ENCODER_MODE_CV 14 */ +-/* ATOM_ENCODER_MODE_CRT 15 */ +- +-/* ucDVOConfig */ +-/* #define DVO_ENCODER_CONFIG_RATE_SEL 0x01 */ +-/* #define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 */ +-/* #define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 */ +-/* #define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c */ +-/* #define DVO_ENCODER_CONFIG_LOW12BIT 0x00 */ +-/* #define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 */ +-/* #define DVO_ENCODER_CONFIG_24BIT 0x08 */ +- +-/* ucMiscInfo: also changed, see below */ ++typedef struct _PIXEL_CLOCK_PARAMETERS_V2 ++{ ++ USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) ++ // 0 means disable PPLL ++ USHORT usRefDiv; // Reference divider ++ USHORT usFbDiv; // feedback divider ++ UCHAR ucPostDiv; // post divider ++ UCHAR ucFracFbDiv; // fractional feedback divider ++ UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 ++ UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER ++ UCHAR ucCRTC; // Which CRTC uses this Ppll ++ UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog ++}PIXEL_CLOCK_PARAMETERS_V2; ++ ++//Major revision=1., Minor revision=3, structure/definition change ++//ucEncoderMode: ++//ATOM_ENCODER_MODE_DP ++//ATOM_ENOCDER_MODE_LVDS ++//ATOM_ENOCDER_MODE_DVI ++//ATOM_ENOCDER_MODE_HDMI ++//ATOM_ENOCDER_MODE_SDVO ++//ATOM_ENCODER_MODE_TV 13 ++//ATOM_ENCODER_MODE_CV 14 ++//ATOM_ENCODER_MODE_CRT 15 ++ ++//ucDVOConfig ++//#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 ++//#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 ++//#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 ++//#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c ++//#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 ++//#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 ++//#define DVO_ENCODER_CONFIG_24BIT 0x08 ++ ++//ucMiscInfo: also changed, see below + #define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01 + #define PIXEL_CLOCK_MISC_VGA_MODE 0x02 + #define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04 + #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00 + #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04 + #define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08 ++#define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10 ++// V1.4 for RoadRunner ++#define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10 ++#define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20 + +-typedef struct _PIXEL_CLOCK_PARAMETERS_V3 { +- USHORT usPixelClock; /* in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) */ +- /* 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. */ +- USHORT usRefDiv; /* Reference divider */ +- USHORT usFbDiv; /* feedback divider */ +- UCHAR ucPostDiv; /* post divider */ +- UCHAR ucFracFbDiv; /* fractional feedback divider */ +- UCHAR ucPpll; /* ATOM_PPLL1 or ATOM_PPL2 */ +- UCHAR ucTransmitterId; /* graphic encoder id defined in objectId.h */ +- union { +- UCHAR ucEncoderMode; /* encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ */ +- UCHAR ucDVOConfig; /* when use DVO, need to know SDR/DDR, 12bit or 24bit */ ++typedef struct _PIXEL_CLOCK_PARAMETERS_V3 ++{ ++ USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) ++ // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. ++ USHORT usRefDiv; // Reference divider ++ USHORT usFbDiv; // feedback divider ++ UCHAR ucPostDiv; // post divider ++ UCHAR ucFracFbDiv; // fractional feedback divider ++ UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 ++ UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h ++ union ++ { ++ UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ ++ UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit + }; +- UCHAR ucMiscInfo; /* bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel */ +- /* bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source */ +-} PIXEL_CLOCK_PARAMETERS_V3; ++ UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel ++ // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source ++ // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider ++}PIXEL_CLOCK_PARAMETERS_V3; + + #define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2 + #define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST + +-/****************************************************************************/ +-/* Structures used by AdjustDisplayPllTable */ +-/****************************************************************************/ +-typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS { ++typedef struct _PIXEL_CLOCK_PARAMETERS_V5 ++{ ++ UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to ++ // drive the pixel clock. not used for DCPLL case. ++ union{ ++ UCHAR ucReserved; ++ UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed. ++ }; ++ USHORT usPixelClock; // target the pixel clock to drive the CRTC timing ++ // 0 means disable PPLL/DCPLL. ++ USHORT usFbDiv; // feedback divider integer part. ++ UCHAR ucPostDiv; // post divider. ++ UCHAR ucRefDiv; // Reference divider ++ UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL ++ UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, ++ // indicate which graphic encoder will be used. ++ UCHAR ucEncoderMode; // Encoder mode: ++ UCHAR ucMiscInfo; // bit[0]= Force program PPLL ++ // bit[1]= when VGA timing is used. ++ // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp ++ // bit[4]= RefClock source for PPLL. ++ // =0: XTLAIN( default mode ) ++ // =1: other external clock source, which is pre-defined ++ // by VBIOS depend on the feature required. ++ // bit[7:5]: reserved. ++ ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) ++ ++}PIXEL_CLOCK_PARAMETERS_V5; ++ ++#define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01 ++#define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02 ++#define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c ++#define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00 ++#define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04 ++#define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08 ++#define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10 ++ ++typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 ++{ ++ PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput; ++}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2; ++ ++typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2 ++{ ++ UCHAR ucStatus; ++ UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock ++ UCHAR ucReserved[2]; ++}GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2; ++ ++typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3 ++{ ++ PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput; ++}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3; ++ ++/****************************************************************************/ ++// Structures used by AdjustDisplayPllTable ++/****************************************************************************/ ++typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS ++{ + USHORT usPixelClock; + UCHAR ucTransmitterID; + UCHAR ucEncodeMode; +- union { +- UCHAR ucDVOConfig; /* if DVO, need passing link rate and output 12bitlow or 24bit */ +- UCHAR ucConfig; /* if none DVO, not defined yet */ ++ union ++ { ++ UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit ++ UCHAR ucConfig; //if none DVO, not defined yet + }; + UCHAR ucReserved[3]; +-} ADJUST_DISPLAY_PLL_PARAMETERS; ++}ADJUST_DISPLAY_PLL_PARAMETERS; + + #define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10 +- + #define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS + +-/****************************************************************************/ +-/* Structures used by EnableYUVTable */ +-/****************************************************************************/ +-typedef struct _ENABLE_YUV_PARAMETERS { +- UCHAR ucEnable; /* ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) */ +- UCHAR ucCRTC; /* Which CRTC needs this YUV or RGB format */ +- UCHAR ucPadding[2]; +-} ENABLE_YUV_PARAMETERS; ++typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 ++{ ++ USHORT usPixelClock; // target pixel clock ++ UCHAR ucTransmitterID; // transmitter id defined in objectid.h ++ UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI ++ UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX ++ UCHAR ucReserved[3]; ++}ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3; ++ ++// usDispPllConfig v1.2 for RoadRunner ++#define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO ++#define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO ++#define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO ++#define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO ++#define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO ++#define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO ++#define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO ++#define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS ++#define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI ++#define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS ++ ++ ++typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 ++{ ++ ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc ++ UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given ) ++ UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider ++ UCHAR ucReserved[2]; ++}ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3; ++ ++typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 ++{ ++ union ++ { ++ ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput; ++ ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput; ++ }; ++} ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3; ++ ++/****************************************************************************/ ++// Structures used by EnableYUVTable ++/****************************************************************************/ ++typedef struct _ENABLE_YUV_PARAMETERS ++{ ++ UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) ++ UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format ++ UCHAR ucPadding[2]; ++}ENABLE_YUV_PARAMETERS; + #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS + +-/****************************************************************************/ +-/* Structures used by GetMemoryClockTable */ +-/****************************************************************************/ +-typedef struct _GET_MEMORY_CLOCK_PARAMETERS { +- ULONG ulReturnMemoryClock; /* current memory speed in 10KHz unit */ ++/****************************************************************************/ ++// Structures used by GetMemoryClockTable ++/****************************************************************************/ ++typedef struct _GET_MEMORY_CLOCK_PARAMETERS ++{ ++ ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit + } GET_MEMORY_CLOCK_PARAMETERS; + #define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS + +-/****************************************************************************/ +-/* Structures used by GetEngineClockTable */ +-/****************************************************************************/ +-typedef struct _GET_ENGINE_CLOCK_PARAMETERS { +- ULONG ulReturnEngineClock; /* current engine speed in 10KHz unit */ ++/****************************************************************************/ ++// Structures used by GetEngineClockTable ++/****************************************************************************/ ++typedef struct _GET_ENGINE_CLOCK_PARAMETERS ++{ ++ ULONG ulReturnEngineClock; // current engine speed in 10KHz unit + } GET_ENGINE_CLOCK_PARAMETERS; + #define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS + +-/****************************************************************************/ +-/* Following Structures and constant may be obsolete */ +-/****************************************************************************/ +-/* Maxium 8 bytes,the data read in will be placed in the parameter space. */ +-/* Read operaion successeful when the paramter space is non-zero, otherwise read operation failed */ +-typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS { +- USHORT usPrescale; /* Ratio between Engine clock and I2C clock */ +- USHORT usVRAMAddress; /* Adress in Frame Buffer where to pace raw EDID */ +- USHORT usStatus; /* When use output: lower byte EDID checksum, high byte hardware status */ +- /* WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte */ +- UCHAR ucSlaveAddr; /* Read from which slave */ +- UCHAR ucLineNumber; /* Read from which HW assisted line */ +-} READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; ++/****************************************************************************/ ++// Following Structures and constant may be obsolete ++/****************************************************************************/ ++//Maxium 8 bytes,the data read in will be placed in the parameter space. ++//Read operaion successeful when the paramter space is non-zero, otherwise read operation failed ++typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS ++{ ++ USHORT usPrescale; //Ratio between Engine clock and I2C clock ++ USHORT usVRAMAddress; //Adress in Frame Buffer where to pace raw EDID ++ USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status ++ //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte ++ UCHAR ucSlaveAddr; //Read from which slave ++ UCHAR ucLineNumber; //Read from which HW assisted line ++}READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; + #define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS + ++ + #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0 + #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1 + #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2 + #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3 + #define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4 + +-typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS { +- USHORT usPrescale; /* Ratio between Engine clock and I2C clock */ +- USHORT usByteOffset; /* Write to which byte */ +- /* Upper portion of usByteOffset is Format of data */ +- /* 1bytePS+offsetPS */ +- /* 2bytesPS+offsetPS */ +- /* blockID+offsetPS */ +- /* blockID+offsetID */ +- /* blockID+counterID+offsetID */ +- UCHAR ucData; /* PS data1 */ +- UCHAR ucStatus; /* Status byte 1=success, 2=failure, Also is used as PS data2 */ +- UCHAR ucSlaveAddr; /* Write to which slave */ +- UCHAR ucLineNumber; /* Write from which HW assisted line */ +-} WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; ++typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS ++{ ++ USHORT usPrescale; //Ratio between Engine clock and I2C clock ++ USHORT usByteOffset; //Write to which byte ++ //Upper portion of usByteOffset is Format of data ++ //1bytePS+offsetPS ++ //2bytesPS+offsetPS ++ //blockID+offsetPS ++ //blockID+offsetID ++ //blockID+counterID+offsetID ++ UCHAR ucData; //PS data1 ++ UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2 ++ UCHAR ucSlaveAddr; //Write to which slave ++ UCHAR ucLineNumber; //Write from which HW assisted line ++}WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; + + #define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS + +-typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS { +- USHORT usPrescale; /* Ratio between Engine clock and I2C clock */ +- UCHAR ucSlaveAddr; /* Write to which slave */ +- UCHAR ucLineNumber; /* Write from which HW assisted line */ +-} SET_UP_HW_I2C_DATA_PARAMETERS; ++typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS ++{ ++ USHORT usPrescale; //Ratio between Engine clock and I2C clock ++ UCHAR ucSlaveAddr; //Write to which slave ++ UCHAR ucLineNumber; //Write from which HW assisted line ++}SET_UP_HW_I2C_DATA_PARAMETERS; ++ + + /**************************************************************************/ + #define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS + +-/****************************************************************************/ +-/* Structures used by PowerConnectorDetectionTable */ +-/****************************************************************************/ +-typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS { +- UCHAR ucPowerConnectorStatus; /* Used for return value 0: detected, 1:not detected */ +- UCHAR ucPwrBehaviorId; +- USHORT usPwrBudget; /* how much power currently boot to in unit of watt */ +-} POWER_CONNECTOR_DETECTION_PARAMETERS; +- +-typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION { +- UCHAR ucPowerConnectorStatus; /* Used for return value 0: detected, 1:not detected */ +- UCHAR ucReserved; +- USHORT usPwrBudget; /* how much power currently boot to in unit of watt */ +- WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; +-} POWER_CONNECTOR_DETECTION_PS_ALLOCATION; ++/****************************************************************************/ ++// Structures used by PowerConnectorDetectionTable ++/****************************************************************************/ ++typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS ++{ ++ UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected ++ UCHAR ucPwrBehaviorId; ++ USHORT usPwrBudget; //how much power currently boot to in unit of watt ++}POWER_CONNECTOR_DETECTION_PARAMETERS; ++ ++typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION ++{ ++ UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected ++ UCHAR ucReserved; ++ USHORT usPwrBudget; //how much power currently boot to in unit of watt ++ WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; ++}POWER_CONNECTOR_DETECTION_PS_ALLOCATION; + + /****************************LVDS SS Command Table Definitions**********************/ + +-/****************************************************************************/ +-/* Structures used by EnableSpreadSpectrumOnPPLLTable */ +-/****************************************************************************/ +-typedef struct _ENABLE_LVDS_SS_PARAMETERS { +- USHORT usSpreadSpectrumPercentage; +- UCHAR ucSpreadSpectrumType; /* Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD */ +- UCHAR ucSpreadSpectrumStepSize_Delay; /* bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY */ +- UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ +- UCHAR ucPadding[3]; +-} ENABLE_LVDS_SS_PARAMETERS; +- +-/* ucTableFormatRevision=1,ucTableContentRevision=2 */ +-typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 { +- USHORT usSpreadSpectrumPercentage; +- UCHAR ucSpreadSpectrumType; /* Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD */ +- UCHAR ucSpreadSpectrumStep; /* */ +- UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ +- UCHAR ucSpreadSpectrumDelay; +- UCHAR ucSpreadSpectrumRange; +- UCHAR ucPadding; +-} ENABLE_LVDS_SS_PARAMETERS_V2; +- +-/* This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. */ +-typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL { +- USHORT usSpreadSpectrumPercentage; +- UCHAR ucSpreadSpectrumType; /* Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD */ +- UCHAR ucSpreadSpectrumStep; /* */ +- UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ +- UCHAR ucSpreadSpectrumDelay; +- UCHAR ucSpreadSpectrumRange; +- UCHAR ucPpll; /* ATOM_PPLL1/ATOM_PPLL2 */ +-} ENABLE_SPREAD_SPECTRUM_ON_PPLL; ++/****************************************************************************/ ++// Structures used by EnableSpreadSpectrumOnPPLLTable ++/****************************************************************************/ ++typedef struct _ENABLE_LVDS_SS_PARAMETERS ++{ ++ USHORT usSpreadSpectrumPercentage; ++ UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD ++ UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY ++ UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE ++ UCHAR ucPadding[3]; ++}ENABLE_LVDS_SS_PARAMETERS; ++ ++//ucTableFormatRevision=1,ucTableContentRevision=2 ++typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 ++{ ++ USHORT usSpreadSpectrumPercentage; ++ UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD ++ UCHAR ucSpreadSpectrumStep; // ++ UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE ++ UCHAR ucSpreadSpectrumDelay; ++ UCHAR ucSpreadSpectrumRange; ++ UCHAR ucPadding; ++}ENABLE_LVDS_SS_PARAMETERS_V2; ++ ++//This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. ++typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL ++{ ++ USHORT usSpreadSpectrumPercentage; ++ UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD ++ UCHAR ucSpreadSpectrumStep; // ++ UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE ++ UCHAR ucSpreadSpectrumDelay; ++ UCHAR ucSpreadSpectrumRange; ++ UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2 ++}ENABLE_SPREAD_SPECTRUM_ON_PPLL; ++ ++typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 ++{ ++ USHORT usSpreadSpectrumPercentage; ++ UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. ++ // Bit[1]: 1-Ext. 0-Int. ++ // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL ++ // Bits[7:4] reserved ++ UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE ++ USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] ++ USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC ++}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2; ++ ++#define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00 ++#define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01 ++#define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02 ++#define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c ++#define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00 ++#define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04 ++#define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08 ++#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF ++#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0 ++#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00 ++#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8 + + #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL + + /**************************************************************************/ + +-typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION { +- PIXEL_CLOCK_PARAMETERS sPCLKInput; +- ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved; /* Caller doesn't need to init this portion */ +-} SET_PIXEL_CLOCK_PS_ALLOCATION; ++typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION ++{ ++ PIXEL_CLOCK_PARAMETERS sPCLKInput; ++ ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion ++}SET_PIXEL_CLOCK_PS_ALLOCATION; + + #define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION + +-/****************************************************************************/ +-/* Structures used by ### */ +-/****************************************************************************/ +-typedef struct _MEMORY_TRAINING_PARAMETERS { +- ULONG ulTargetMemoryClock; /* In 10Khz unit */ +-} MEMORY_TRAINING_PARAMETERS; ++/****************************************************************************/ ++// Structures used by ### ++/****************************************************************************/ ++typedef struct _MEMORY_TRAINING_PARAMETERS ++{ ++ ULONG ulTargetMemoryClock; //In 10Khz unit ++}MEMORY_TRAINING_PARAMETERS; + #define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS + ++ + /****************************LVDS and other encoder command table definitions **********************/ + +-/****************************************************************************/ +-/* Structures used by LVDSEncoderControlTable (Before DCE30) */ +-/* LVTMAEncoderControlTable (Before DCE30) */ +-/* TMDSAEncoderControlTable (Before DCE30) */ +-/****************************************************************************/ +-typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS { +- USHORT usPixelClock; /* in 10KHz; for bios convenient */ +- UCHAR ucMisc; /* bit0=0: Enable single link */ +- /* =1: Enable dual link */ +- /* Bit1=0: 666RGB */ +- /* =1: 888RGB */ +- UCHAR ucAction; /* 0: turn off encoder */ +- /* 1: setup and turn on encoder */ +-} LVDS_ENCODER_CONTROL_PARAMETERS; + +-#define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS ++/****************************************************************************/ ++// Structures used by LVDSEncoderControlTable (Before DCE30) ++// LVTMAEncoderControlTable (Before DCE30) ++// TMDSAEncoderControlTable (Before DCE30) ++/****************************************************************************/ ++typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS ++{ ++ USHORT usPixelClock; // in 10KHz; for bios convenient ++ UCHAR ucMisc; // bit0=0: Enable single link ++ // =1: Enable dual link ++ // Bit1=0: 666RGB ++ // =1: 888RGB ++ UCHAR ucAction; // 0: turn off encoder ++ // 1: setup and turn on encoder ++}LVDS_ENCODER_CONTROL_PARAMETERS; + ++#define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS ++ + #define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS + #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS + + #define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS + #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS + +-/* ucTableFormatRevision=1,ucTableContentRevision=2 */ +-typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 { +- USHORT usPixelClock; /* in 10KHz; for bios convenient */ +- UCHAR ucMisc; /* see PANEL_ENCODER_MISC_xx definitions below */ +- UCHAR ucAction; /* 0: turn off encoder */ +- /* 1: setup and turn on encoder */ +- UCHAR ucTruncate; /* bit0=0: Disable truncate */ +- /* =1: Enable truncate */ +- /* bit4=0: 666RGB */ +- /* =1: 888RGB */ +- UCHAR ucSpatial; /* bit0=0: Disable spatial dithering */ +- /* =1: Enable spatial dithering */ +- /* bit4=0: 666RGB */ +- /* =1: 888RGB */ +- UCHAR ucTemporal; /* bit0=0: Disable temporal dithering */ +- /* =1: Enable temporal dithering */ +- /* bit4=0: 666RGB */ +- /* =1: 888RGB */ +- /* bit5=0: Gray level 2 */ +- /* =1: Gray level 4 */ +- UCHAR ucFRC; /* bit4=0: 25FRC_SEL pattern E */ +- /* =1: 25FRC_SEL pattern F */ +- /* bit6:5=0: 50FRC_SEL pattern A */ +- /* =1: 50FRC_SEL pattern B */ +- /* =2: 50FRC_SEL pattern C */ +- /* =3: 50FRC_SEL pattern D */ +- /* bit7=0: 75FRC_SEL pattern E */ +- /* =1: 75FRC_SEL pattern F */ +-} LVDS_ENCODER_CONTROL_PARAMETERS_V2; + +-#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 ++//ucTableFormatRevision=1,ucTableContentRevision=2 ++typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 ++{ ++ USHORT usPixelClock; // in 10KHz; for bios convenient ++ UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below ++ UCHAR ucAction; // 0: turn off encoder ++ // 1: setup and turn on encoder ++ UCHAR ucTruncate; // bit0=0: Disable truncate ++ // =1: Enable truncate ++ // bit4=0: 666RGB ++ // =1: 888RGB ++ UCHAR ucSpatial; // bit0=0: Disable spatial dithering ++ // =1: Enable spatial dithering ++ // bit4=0: 666RGB ++ // =1: 888RGB ++ UCHAR ucTemporal; // bit0=0: Disable temporal dithering ++ // =1: Enable temporal dithering ++ // bit4=0: 666RGB ++ // =1: 888RGB ++ // bit5=0: Gray level 2 ++ // =1: Gray level 4 ++ UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E ++ // =1: 25FRC_SEL pattern F ++ // bit6:5=0: 50FRC_SEL pattern A ++ // =1: 50FRC_SEL pattern B ++ // =2: 50FRC_SEL pattern C ++ // =3: 50FRC_SEL pattern D ++ // bit7=0: 75FRC_SEL pattern E ++ // =1: 75FRC_SEL pattern F ++}LVDS_ENCODER_CONTROL_PARAMETERS_V2; + ++#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 ++ + #define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 + #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 +- ++ + #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 + #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 + +@@ -1185,38 +1536,42 @@ typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 { + #define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 + #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 + +-/****************************************************************************/ +-/* Structures used by ### */ +-/****************************************************************************/ +-typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS { +- UCHAR ucEnable; /* Enable or Disable External TMDS encoder */ +- UCHAR ucMisc; /* Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} */ +- UCHAR ucPadding[2]; +-} ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; +- +-typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION { +- ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; +- WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; /* Caller doesn't need to init this portion */ +-} ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; ++/****************************************************************************/ ++// Structures used by ### ++/****************************************************************************/ ++typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS ++{ ++ UCHAR ucEnable; // Enable or Disable External TMDS encoder ++ UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} ++ UCHAR ucPadding[2]; ++}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; ++ ++typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ++{ ++ ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; ++ WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion ++}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; + + #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 + +-typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 { +- ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; +- WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; /* Caller doesn't need to init this portion */ +-} ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; ++typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 ++{ ++ ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; ++ WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion ++}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; + +-typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION { +- DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder; +- WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; +-} EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; ++typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION ++{ ++ DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder; ++ WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; ++}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; + +-/****************************************************************************/ +-/* Structures used by DVOEncoderControlTable */ +-/****************************************************************************/ +-/* ucTableFormatRevision=1,ucTableContentRevision=3 */ ++/****************************************************************************/ ++// Structures used by DVOEncoderControlTable ++/****************************************************************************/ ++//ucTableFormatRevision=1,ucTableContentRevision=3 + +-/* ucDVOConfig: */ ++//ucDVOConfig: + #define DVO_ENCODER_CONFIG_RATE_SEL 0x01 + #define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 + #define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 +@@ -1225,21 +1580,22 @@ typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION { + #define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 + #define DVO_ENCODER_CONFIG_24BIT 0x08 + +-typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 { +- USHORT usPixelClock; +- UCHAR ucDVOConfig; +- UCHAR ucAction; /* ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT */ +- UCHAR ucReseved[4]; +-} DVO_ENCODER_CONTROL_PARAMETERS_V3; ++typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 ++{ ++ USHORT usPixelClock; ++ UCHAR ucDVOConfig; ++ UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT ++ UCHAR ucReseved[4]; ++}DVO_ENCODER_CONTROL_PARAMETERS_V3; + #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3 + +-/* ucTableFormatRevision=1 */ +-/* ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for */ +-/* bit1=0: non-coherent mode */ +-/* =1: coherent mode */ ++//ucTableFormatRevision=1 ++//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for ++// bit1=0: non-coherent mode ++// =1: coherent mode + +-/* ========================================================================================== */ +-/* Only change is here next time when changing encoder parameter definitions again! */ ++//========================================================================================== ++//Only change is here next time when changing encoder parameter definitions again! + #define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 + #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST + +@@ -1252,7 +1608,7 @@ typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 { + #define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS + #define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION + +-/* ========================================================================================== */ ++//========================================================================================== + #define PANEL_ENCODER_MISC_DUAL 0x01 + #define PANEL_ENCODER_MISC_COHERENT 0x02 + #define PANEL_ENCODER_MISC_TMDS_LINKB 0x04 +@@ -1281,159 +1637,159 @@ typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 { + #define PANEL_ENCODER_75FRC_E 0x00 + #define PANEL_ENCODER_75FRC_F 0x80 + +-/****************************************************************************/ +-/* Structures used by SetVoltageTable */ +-/****************************************************************************/ ++/****************************************************************************/ ++// Structures used by SetVoltageTable ++/****************************************************************************/ + #define SET_VOLTAGE_TYPE_ASIC_VDDC 1 + #define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 + #define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 + #define SET_VOLTAGE_TYPE_ASIC_VDDCI 4 + #define SET_VOLTAGE_INIT_MODE 5 +-#define SET_VOLTAGE_GET_MAX_VOLTAGE 6 /* Gets the Max. voltage for the soldered Asic */ ++#define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic + + #define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1 + #define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2 + #define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4 + + #define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0 +-#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 ++#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 + #define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2 + +-typedef struct _SET_VOLTAGE_PARAMETERS { +- UCHAR ucVoltageType; /* To tell which voltage to set up, VDDC/MVDDC/MVDDQ */ +- UCHAR ucVoltageMode; /* To set all, to set source A or source B or ... */ +- UCHAR ucVoltageIndex; /* An index to tell which voltage level */ +- UCHAR ucReserved; +-} SET_VOLTAGE_PARAMETERS; +- +-typedef struct _SET_VOLTAGE_PARAMETERS_V2 { +- UCHAR ucVoltageType; /* To tell which voltage to set up, VDDC/MVDDC/MVDDQ */ +- UCHAR ucVoltageMode; /* Not used, maybe use for state machine for differen power mode */ +- USHORT usVoltageLevel; /* real voltage level */ +-} SET_VOLTAGE_PARAMETERS_V2; +- +-typedef struct _SET_VOLTAGE_PS_ALLOCATION { +- SET_VOLTAGE_PARAMETERS sASICSetVoltage; +- WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; +-} SET_VOLTAGE_PS_ALLOCATION; +- +-/****************************************************************************/ +-/* Structures used by TVEncoderControlTable */ +-/****************************************************************************/ +-typedef struct _TV_ENCODER_CONTROL_PARAMETERS { +- USHORT usPixelClock; /* in 10KHz; for bios convenient */ +- UCHAR ucTvStandard; /* See definition "ATOM_TV_NTSC ..." */ +- UCHAR ucAction; /* 0: turn off encoder */ +- /* 1: setup and turn on encoder */ +-} TV_ENCODER_CONTROL_PARAMETERS; +- +-typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION { +- TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; +- WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; /* Don't set this one */ +-} TV_ENCODER_CONTROL_PS_ALLOCATION; +- +-/* ==============================Data Table Portion==================================== */ +- +-#ifdef UEFI_BUILD +-#define UTEMP USHORT +-#define USHORT void* +-#endif +- +-/****************************************************************************/ +-/* Structure used in Data.mtb */ +-/****************************************************************************/ +-typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES { +- USHORT UtilityPipeLine; /* Offest for the utility to get parser info,Don't change this position! */ +- USHORT MultimediaCapabilityInfo; /* Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios */ +- USHORT MultimediaConfigInfo; /* Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios */ +- USHORT StandardVESA_Timing; /* Only used by Bios */ +- USHORT FirmwareInfo; /* Shared by various SW components,latest version 1.4 */ +- USHORT DAC_Info; /* Will be obsolete from R600 */ +- USHORT LVDS_Info; /* Shared by various SW components,latest version 1.1 */ +- USHORT TMDS_Info; /* Will be obsolete from R600 */ +- USHORT AnalogTV_Info; /* Shared by various SW components,latest version 1.1 */ +- USHORT SupportedDevicesInfo; /* Will be obsolete from R600 */ +- USHORT GPIO_I2C_Info; /* Shared by various SW components,latest version 1.2 will be used from R600 */ +- USHORT VRAM_UsageByFirmware; /* Shared by various SW components,latest version 1.3 will be used from R600 */ +- USHORT GPIO_Pin_LUT; /* Shared by various SW components,latest version 1.1 */ +- USHORT VESA_ToInternalModeLUT; /* Only used by Bios */ +- USHORT ComponentVideoInfo; /* Shared by various SW components,latest version 2.1 will be used from R600 */ +- USHORT PowerPlayInfo; /* Shared by various SW components,latest version 2.1,new design from R600 */ +- USHORT CompassionateData; /* Will be obsolete from R600 */ +- USHORT SaveRestoreInfo; /* Only used by Bios */ +- USHORT PPLL_SS_Info; /* Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info */ +- USHORT OemInfo; /* Defined and used by external SW, should be obsolete soon */ +- USHORT XTMDS_Info; /* Will be obsolete from R600 */ +- USHORT MclkSS_Info; /* Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used */ +- USHORT Object_Header; /* Shared by various SW components,latest version 1.1 */ +- USHORT IndirectIOAccess; /* Only used by Bios,this table position can't change at all!! */ +- USHORT MC_InitParameter; /* Only used by command table */ +- USHORT ASIC_VDDC_Info; /* Will be obsolete from R600 */ +- USHORT ASIC_InternalSS_Info; /* New tabel name from R600, used to be called "ASIC_MVDDC_Info" */ +- USHORT TV_VideoMode; /* Only used by command table */ +- USHORT VRAM_Info; /* Only used by command table, latest version 1.3 */ +- USHORT MemoryTrainingInfo; /* Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 */ +- USHORT IntegratedSystemInfo; /* Shared by various SW components */ +- USHORT ASIC_ProfilingInfo; /* New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 */ +- USHORT VoltageObjectInfo; /* Shared by various SW components, latest version 1.1 */ +- USHORT PowerSourceInfo; /* Shared by various SW components, latest versoin 1.1 */ +-} ATOM_MASTER_LIST_OF_DATA_TABLES; +- +-#ifdef UEFI_BUILD +-#define USHORT UTEMP +-#endif ++typedef struct _SET_VOLTAGE_PARAMETERS ++{ ++ UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ ++ UCHAR ucVoltageMode; // To set all, to set source A or source B or ... ++ UCHAR ucVoltageIndex; // An index to tell which voltage level ++ UCHAR ucReserved; ++}SET_VOLTAGE_PARAMETERS; + +-typedef struct _ATOM_MASTER_DATA_TABLE { +- ATOM_COMMON_TABLE_HEADER sHeader; +- ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; +-} ATOM_MASTER_DATA_TABLE; ++typedef struct _SET_VOLTAGE_PARAMETERS_V2 ++{ ++ UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ ++ UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode ++ USHORT usVoltageLevel; // real voltage level ++}SET_VOLTAGE_PARAMETERS_V2; + +-/****************************************************************************/ +-/* Structure used in MultimediaCapabilityInfoTable */ +-/****************************************************************************/ +-typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO { +- ATOM_COMMON_TABLE_HEADER sHeader; +- ULONG ulSignature; /* HW info table signature string "$ATI" */ +- UCHAR ucI2C_Type; /* I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) */ +- UCHAR ucTV_OutInfo; /* Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) */ +- UCHAR ucVideoPortInfo; /* Provides the video port capabilities */ +- UCHAR ucHostPortInfo; /* Provides host port configuration information */ +-} ATOM_MULTIMEDIA_CAPABILITY_INFO; ++typedef struct _SET_VOLTAGE_PS_ALLOCATION ++{ ++ SET_VOLTAGE_PARAMETERS sASICSetVoltage; ++ WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; ++}SET_VOLTAGE_PS_ALLOCATION; ++ ++/****************************************************************************/ ++// Structures used by TVEncoderControlTable ++/****************************************************************************/ ++typedef struct _TV_ENCODER_CONTROL_PARAMETERS ++{ ++ USHORT usPixelClock; // in 10KHz; for bios convenient ++ UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..." ++ UCHAR ucAction; // 0: turn off encoder ++ // 1: setup and turn on encoder ++}TV_ENCODER_CONTROL_PARAMETERS; + +-/****************************************************************************/ +-/* Structure used in MultimediaConfigInfoTable */ +-/****************************************************************************/ +-typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO { +- ATOM_COMMON_TABLE_HEADER sHeader; +- ULONG ulSignature; /* MM info table signature sting "$MMT" */ +- UCHAR ucTunerInfo; /* Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) */ +- UCHAR ucAudioChipInfo; /* List the audio chip type (3:0) product type (4) and OEM revision (7:5) */ +- UCHAR ucProductID; /* Defines as OEM ID or ATI board ID dependent on product type setting */ +- UCHAR ucMiscInfo1; /* Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) */ +- UCHAR ucMiscInfo2; /* I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) */ +- UCHAR ucMiscInfo3; /* Video Decoder Type (3:0) Video In Standard/Crystal (7:4) */ +- UCHAR ucMiscInfo4; /* Video Decoder Host Config (2:0) reserved (7:3) */ +- UCHAR ucVideoInput0Info; /* Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) */ +- UCHAR ucVideoInput1Info; /* Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) */ +- UCHAR ucVideoInput2Info; /* Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) */ +- UCHAR ucVideoInput3Info; /* Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) */ +- UCHAR ucVideoInput4Info; /* Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) */ +-} ATOM_MULTIMEDIA_CONFIG_INFO; ++typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION ++{ ++ TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; ++ WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one ++}TV_ENCODER_CONTROL_PS_ALLOCATION; + +-/****************************************************************************/ +-/* Structures used in FirmwareInfoTable */ +-/****************************************************************************/ ++//==============================Data Table Portion==================================== + +-/* usBIOSCapability Definition: */ +-/* Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; */ +-/* Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; */ +-/* Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; */ +-/* Others: Reserved */ ++/****************************************************************************/ ++// Structure used in Data.mtb ++/****************************************************************************/ ++typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES ++{ ++ USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position! ++ USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios ++ USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios ++ USHORT StandardVESA_Timing; // Only used by Bios ++ USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 ++ USHORT DAC_Info; // Will be obsolete from R600 ++ USHORT LVDS_Info; // Shared by various SW components,latest version 1.1 ++ USHORT TMDS_Info; // Will be obsolete from R600 ++ USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 ++ USHORT SupportedDevicesInfo; // Will be obsolete from R600 ++ USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 ++ USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 ++ USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1 ++ USHORT VESA_ToInternalModeLUT; // Only used by Bios ++ USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600 ++ USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600 ++ USHORT CompassionateData; // Will be obsolete from R600 ++ USHORT SaveRestoreInfo; // Only used by Bios ++ USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info ++ USHORT OemInfo; // Defined and used by external SW, should be obsolete soon ++ USHORT XTMDS_Info; // Will be obsolete from R600 ++ USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used ++ USHORT Object_Header; // Shared by various SW components,latest version 1.1 ++ USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!! ++ USHORT MC_InitParameter; // Only used by command table ++ USHORT ASIC_VDDC_Info; // Will be obsolete from R600 ++ USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info" ++ USHORT TV_VideoMode; // Only used by command table ++ USHORT VRAM_Info; // Only used by command table, latest version 1.3 ++ USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 ++ USHORT IntegratedSystemInfo; // Shared by various SW components ++ USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 ++ USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1 ++ USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 ++}ATOM_MASTER_LIST_OF_DATA_TABLES; ++ ++typedef struct _ATOM_MASTER_DATA_TABLE ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; ++}ATOM_MASTER_DATA_TABLE; ++ ++/****************************************************************************/ ++// Structure used in MultimediaCapabilityInfoTable ++/****************************************************************************/ ++typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ULONG ulSignature; // HW info table signature string "$ATI" ++ UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) ++ UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) ++ UCHAR ucVideoPortInfo; // Provides the video port capabilities ++ UCHAR ucHostPortInfo; // Provides host port configuration information ++}ATOM_MULTIMEDIA_CAPABILITY_INFO; ++ ++/****************************************************************************/ ++// Structure used in MultimediaConfigInfoTable ++/****************************************************************************/ ++typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ULONG ulSignature; // MM info table signature sting "$MMT" ++ UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) ++ UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5) ++ UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting ++ UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) ++ UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) ++ UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4) ++ UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3) ++ UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) ++ UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) ++ UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) ++ UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) ++ UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) ++}ATOM_MULTIMEDIA_CONFIG_INFO; ++ ++/****************************************************************************/ ++// Structures used in FirmwareInfoTable ++/****************************************************************************/ ++ ++// usBIOSCapability Defintion: ++// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; ++// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; ++// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; ++// Others: Reserved + #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 + #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 + #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 +-#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 +-#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 ++#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. ++#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. + #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 + #define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 + #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 +@@ -1441,242 +1797,292 @@ typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO { + #define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00 + #define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000 + #define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000 ++#define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip ++#define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip + + #ifndef _H2INC + +-/* Please don't add or expand this bitfield structure below, this one will retire soon.! */ +-typedef struct _ATOM_FIRMWARE_CAPABILITY { ++//Please don't add or expand this bitfield structure below, this one will retire soon.! ++typedef struct _ATOM_FIRMWARE_CAPABILITY ++{ + #if ATOM_BIG_ENDIAN +- USHORT Reserved:3; +- USHORT HyperMemory_Size:4; +- USHORT HyperMemory_Support:1; +- USHORT PPMode_Assigned:1; +- USHORT WMI_SUPPORT:1; +- USHORT GPUControlsBL:1; +- USHORT EngineClockSS_Support:1; +- USHORT MemoryClockSS_Support:1; +- USHORT ExtendedDesktopSupport:1; +- USHORT DualCRTC_Support:1; +- USHORT FirmwarePosted:1; ++ USHORT Reserved:3; ++ USHORT HyperMemory_Size:4; ++ USHORT HyperMemory_Support:1; ++ USHORT PPMode_Assigned:1; ++ USHORT WMI_SUPPORT:1; ++ USHORT GPUControlsBL:1; ++ USHORT EngineClockSS_Support:1; ++ USHORT MemoryClockSS_Support:1; ++ USHORT ExtendedDesktopSupport:1; ++ USHORT DualCRTC_Support:1; ++ USHORT FirmwarePosted:1; + #else +- USHORT FirmwarePosted:1; +- USHORT DualCRTC_Support:1; +- USHORT ExtendedDesktopSupport:1; +- USHORT MemoryClockSS_Support:1; +- USHORT EngineClockSS_Support:1; +- USHORT GPUControlsBL:1; +- USHORT WMI_SUPPORT:1; +- USHORT PPMode_Assigned:1; +- USHORT HyperMemory_Support:1; +- USHORT HyperMemory_Size:4; +- USHORT Reserved:3; ++ USHORT FirmwarePosted:1; ++ USHORT DualCRTC_Support:1; ++ USHORT ExtendedDesktopSupport:1; ++ USHORT MemoryClockSS_Support:1; ++ USHORT EngineClockSS_Support:1; ++ USHORT GPUControlsBL:1; ++ USHORT WMI_SUPPORT:1; ++ USHORT PPMode_Assigned:1; ++ USHORT HyperMemory_Support:1; ++ USHORT HyperMemory_Size:4; ++ USHORT Reserved:3; + #endif +-} ATOM_FIRMWARE_CAPABILITY; ++}ATOM_FIRMWARE_CAPABILITY; + +-typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS { +- ATOM_FIRMWARE_CAPABILITY sbfAccess; +- USHORT susAccess; +-} ATOM_FIRMWARE_CAPABILITY_ACCESS; ++typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS ++{ ++ ATOM_FIRMWARE_CAPABILITY sbfAccess; ++ USHORT susAccess; ++}ATOM_FIRMWARE_CAPABILITY_ACCESS; + + #else + +-typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS { +- USHORT susAccess; +-} ATOM_FIRMWARE_CAPABILITY_ACCESS; ++typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS ++{ ++ USHORT susAccess; ++}ATOM_FIRMWARE_CAPABILITY_ACCESS; + + #endif + +-typedef struct _ATOM_FIRMWARE_INFO { +- ATOM_COMMON_TABLE_HEADER sHeader; +- ULONG ulFirmwareRevision; +- ULONG ulDefaultEngineClock; /* In 10Khz unit */ +- ULONG ulDefaultMemoryClock; /* In 10Khz unit */ +- ULONG ulDriverTargetEngineClock; /* In 10Khz unit */ +- ULONG ulDriverTargetMemoryClock; /* In 10Khz unit */ +- ULONG ulMaxEngineClockPLL_Output; /* In 10Khz unit */ +- ULONG ulMaxMemoryClockPLL_Output; /* In 10Khz unit */ +- ULONG ulMaxPixelClockPLL_Output; /* In 10Khz unit */ +- ULONG ulASICMaxEngineClock; /* In 10Khz unit */ +- ULONG ulASICMaxMemoryClock; /* In 10Khz unit */ +- UCHAR ucASICMaxTemperature; +- UCHAR ucPadding[3]; /* Don't use them */ +- ULONG aulReservedForBIOS[3]; /* Don't use them */ +- USHORT usMinEngineClockPLL_Input; /* In 10Khz unit */ +- USHORT usMaxEngineClockPLL_Input; /* In 10Khz unit */ +- USHORT usMinEngineClockPLL_Output; /* In 10Khz unit */ +- USHORT usMinMemoryClockPLL_Input; /* In 10Khz unit */ +- USHORT usMaxMemoryClockPLL_Input; /* In 10Khz unit */ +- USHORT usMinMemoryClockPLL_Output; /* In 10Khz unit */ +- USHORT usMaxPixelClock; /* In 10Khz unit, Max. Pclk */ +- USHORT usMinPixelClockPLL_Input; /* In 10Khz unit */ +- USHORT usMaxPixelClockPLL_Input; /* In 10Khz unit */ +- USHORT usMinPixelClockPLL_Output; /* In 10Khz unit, the definitions above can't change!!! */ +- ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; +- USHORT usReferenceClock; /* In 10Khz unit */ +- USHORT usPM_RTS_Location; /* RTS PM4 starting location in ROM in 1Kb unit */ +- UCHAR ucPM_RTS_StreamSize; /* RTS PM4 packets in Kb unit */ +- UCHAR ucDesign_ID; /* Indicate what is the board design */ +- UCHAR ucMemoryModule_ID; /* Indicate what is the board design */ +-} ATOM_FIRMWARE_INFO; +- +-typedef struct _ATOM_FIRMWARE_INFO_V1_2 { +- ATOM_COMMON_TABLE_HEADER sHeader; +- ULONG ulFirmwareRevision; +- ULONG ulDefaultEngineClock; /* In 10Khz unit */ +- ULONG ulDefaultMemoryClock; /* In 10Khz unit */ +- ULONG ulDriverTargetEngineClock; /* In 10Khz unit */ +- ULONG ulDriverTargetMemoryClock; /* In 10Khz unit */ +- ULONG ulMaxEngineClockPLL_Output; /* In 10Khz unit */ +- ULONG ulMaxMemoryClockPLL_Output; /* In 10Khz unit */ +- ULONG ulMaxPixelClockPLL_Output; /* In 10Khz unit */ +- ULONG ulASICMaxEngineClock; /* In 10Khz unit */ +- ULONG ulASICMaxMemoryClock; /* In 10Khz unit */ +- UCHAR ucASICMaxTemperature; +- UCHAR ucMinAllowedBL_Level; +- UCHAR ucPadding[2]; /* Don't use them */ +- ULONG aulReservedForBIOS[2]; /* Don't use them */ +- ULONG ulMinPixelClockPLL_Output; /* In 10Khz unit */ +- USHORT usMinEngineClockPLL_Input; /* In 10Khz unit */ +- USHORT usMaxEngineClockPLL_Input; /* In 10Khz unit */ +- USHORT usMinEngineClockPLL_Output; /* In 10Khz unit */ +- USHORT usMinMemoryClockPLL_Input; /* In 10Khz unit */ +- USHORT usMaxMemoryClockPLL_Input; /* In 10Khz unit */ +- USHORT usMinMemoryClockPLL_Output; /* In 10Khz unit */ +- USHORT usMaxPixelClock; /* In 10Khz unit, Max. Pclk */ +- USHORT usMinPixelClockPLL_Input; /* In 10Khz unit */ +- USHORT usMaxPixelClockPLL_Input; /* In 10Khz unit */ +- USHORT usMinPixelClockPLL_Output; /* In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output */ +- ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; +- USHORT usReferenceClock; /* In 10Khz unit */ +- USHORT usPM_RTS_Location; /* RTS PM4 starting location in ROM in 1Kb unit */ +- UCHAR ucPM_RTS_StreamSize; /* RTS PM4 packets in Kb unit */ +- UCHAR ucDesign_ID; /* Indicate what is the board design */ +- UCHAR ucMemoryModule_ID; /* Indicate what is the board design */ +-} ATOM_FIRMWARE_INFO_V1_2; +- +-typedef struct _ATOM_FIRMWARE_INFO_V1_3 { +- ATOM_COMMON_TABLE_HEADER sHeader; +- ULONG ulFirmwareRevision; +- ULONG ulDefaultEngineClock; /* In 10Khz unit */ +- ULONG ulDefaultMemoryClock; /* In 10Khz unit */ +- ULONG ulDriverTargetEngineClock; /* In 10Khz unit */ +- ULONG ulDriverTargetMemoryClock; /* In 10Khz unit */ +- ULONG ulMaxEngineClockPLL_Output; /* In 10Khz unit */ +- ULONG ulMaxMemoryClockPLL_Output; /* In 10Khz unit */ +- ULONG ulMaxPixelClockPLL_Output; /* In 10Khz unit */ +- ULONG ulASICMaxEngineClock; /* In 10Khz unit */ +- ULONG ulASICMaxMemoryClock; /* In 10Khz unit */ +- UCHAR ucASICMaxTemperature; +- UCHAR ucMinAllowedBL_Level; +- UCHAR ucPadding[2]; /* Don't use them */ +- ULONG aulReservedForBIOS; /* Don't use them */ +- ULONG ul3DAccelerationEngineClock; /* In 10Khz unit */ +- ULONG ulMinPixelClockPLL_Output; /* In 10Khz unit */ +- USHORT usMinEngineClockPLL_Input; /* In 10Khz unit */ +- USHORT usMaxEngineClockPLL_Input; /* In 10Khz unit */ +- USHORT usMinEngineClockPLL_Output; /* In 10Khz unit */ +- USHORT usMinMemoryClockPLL_Input; /* In 10Khz unit */ +- USHORT usMaxMemoryClockPLL_Input; /* In 10Khz unit */ +- USHORT usMinMemoryClockPLL_Output; /* In 10Khz unit */ +- USHORT usMaxPixelClock; /* In 10Khz unit, Max. Pclk */ +- USHORT usMinPixelClockPLL_Input; /* In 10Khz unit */ +- USHORT usMaxPixelClockPLL_Input; /* In 10Khz unit */ +- USHORT usMinPixelClockPLL_Output; /* In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output */ +- ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; +- USHORT usReferenceClock; /* In 10Khz unit */ +- USHORT usPM_RTS_Location; /* RTS PM4 starting location in ROM in 1Kb unit */ +- UCHAR ucPM_RTS_StreamSize; /* RTS PM4 packets in Kb unit */ +- UCHAR ucDesign_ID; /* Indicate what is the board design */ +- UCHAR ucMemoryModule_ID; /* Indicate what is the board design */ +-} ATOM_FIRMWARE_INFO_V1_3; +- +-typedef struct _ATOM_FIRMWARE_INFO_V1_4 { +- ATOM_COMMON_TABLE_HEADER sHeader; +- ULONG ulFirmwareRevision; +- ULONG ulDefaultEngineClock; /* In 10Khz unit */ +- ULONG ulDefaultMemoryClock; /* In 10Khz unit */ +- ULONG ulDriverTargetEngineClock; /* In 10Khz unit */ +- ULONG ulDriverTargetMemoryClock; /* In 10Khz unit */ +- ULONG ulMaxEngineClockPLL_Output; /* In 10Khz unit */ +- ULONG ulMaxMemoryClockPLL_Output; /* In 10Khz unit */ +- ULONG ulMaxPixelClockPLL_Output; /* In 10Khz unit */ +- ULONG ulASICMaxEngineClock; /* In 10Khz unit */ +- ULONG ulASICMaxMemoryClock; /* In 10Khz unit */ +- UCHAR ucASICMaxTemperature; +- UCHAR ucMinAllowedBL_Level; +- USHORT usBootUpVDDCVoltage; /* In MV unit */ +- USHORT usLcdMinPixelClockPLL_Output; /* In MHz unit */ +- USHORT usLcdMaxPixelClockPLL_Output; /* In MHz unit */ +- ULONG ul3DAccelerationEngineClock; /* In 10Khz unit */ +- ULONG ulMinPixelClockPLL_Output; /* In 10Khz unit */ +- USHORT usMinEngineClockPLL_Input; /* In 10Khz unit */ +- USHORT usMaxEngineClockPLL_Input; /* In 10Khz unit */ +- USHORT usMinEngineClockPLL_Output; /* In 10Khz unit */ +- USHORT usMinMemoryClockPLL_Input; /* In 10Khz unit */ +- USHORT usMaxMemoryClockPLL_Input; /* In 10Khz unit */ +- USHORT usMinMemoryClockPLL_Output; /* In 10Khz unit */ +- USHORT usMaxPixelClock; /* In 10Khz unit, Max. Pclk */ +- USHORT usMinPixelClockPLL_Input; /* In 10Khz unit */ +- USHORT usMaxPixelClockPLL_Input; /* In 10Khz unit */ +- USHORT usMinPixelClockPLL_Output; /* In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output */ +- ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; +- USHORT usReferenceClock; /* In 10Khz unit */ +- USHORT usPM_RTS_Location; /* RTS PM4 starting location in ROM in 1Kb unit */ +- UCHAR ucPM_RTS_StreamSize; /* RTS PM4 packets in Kb unit */ +- UCHAR ucDesign_ID; /* Indicate what is the board design */ +- UCHAR ucMemoryModule_ID; /* Indicate what is the board design */ +-} ATOM_FIRMWARE_INFO_V1_4; +- +-#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V1_4 +- +-/****************************************************************************/ +-/* Structures used in IntegratedSystemInfoTable */ +-/****************************************************************************/ ++typedef struct _ATOM_FIRMWARE_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ULONG ulFirmwareRevision; ++ ULONG ulDefaultEngineClock; //In 10Khz unit ++ ULONG ulDefaultMemoryClock; //In 10Khz unit ++ ULONG ulDriverTargetEngineClock; //In 10Khz unit ++ ULONG ulDriverTargetMemoryClock; //In 10Khz unit ++ ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit ++ ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit ++ ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit ++ ULONG ulASICMaxEngineClock; //In 10Khz unit ++ ULONG ulASICMaxMemoryClock; //In 10Khz unit ++ UCHAR ucASICMaxTemperature; ++ UCHAR ucPadding[3]; //Don't use them ++ ULONG aulReservedForBIOS[3]; //Don't use them ++ USHORT usMinEngineClockPLL_Input; //In 10Khz unit ++ USHORT usMaxEngineClockPLL_Input; //In 10Khz unit ++ USHORT usMinEngineClockPLL_Output; //In 10Khz unit ++ USHORT usMinMemoryClockPLL_Input; //In 10Khz unit ++ USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit ++ USHORT usMinMemoryClockPLL_Output; //In 10Khz unit ++ USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk ++ USHORT usMinPixelClockPLL_Input; //In 10Khz unit ++ USHORT usMaxPixelClockPLL_Input; //In 10Khz unit ++ USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!! ++ ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; ++ USHORT usReferenceClock; //In 10Khz unit ++ USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit ++ UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit ++ UCHAR ucDesign_ID; //Indicate what is the board design ++ UCHAR ucMemoryModule_ID; //Indicate what is the board design ++}ATOM_FIRMWARE_INFO; ++ ++typedef struct _ATOM_FIRMWARE_INFO_V1_2 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ULONG ulFirmwareRevision; ++ ULONG ulDefaultEngineClock; //In 10Khz unit ++ ULONG ulDefaultMemoryClock; //In 10Khz unit ++ ULONG ulDriverTargetEngineClock; //In 10Khz unit ++ ULONG ulDriverTargetMemoryClock; //In 10Khz unit ++ ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit ++ ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit ++ ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit ++ ULONG ulASICMaxEngineClock; //In 10Khz unit ++ ULONG ulASICMaxMemoryClock; //In 10Khz unit ++ UCHAR ucASICMaxTemperature; ++ UCHAR ucMinAllowedBL_Level; ++ UCHAR ucPadding[2]; //Don't use them ++ ULONG aulReservedForBIOS[2]; //Don't use them ++ ULONG ulMinPixelClockPLL_Output; //In 10Khz unit ++ USHORT usMinEngineClockPLL_Input; //In 10Khz unit ++ USHORT usMaxEngineClockPLL_Input; //In 10Khz unit ++ USHORT usMinEngineClockPLL_Output; //In 10Khz unit ++ USHORT usMinMemoryClockPLL_Input; //In 10Khz unit ++ USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit ++ USHORT usMinMemoryClockPLL_Output; //In 10Khz unit ++ USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk ++ USHORT usMinPixelClockPLL_Input; //In 10Khz unit ++ USHORT usMaxPixelClockPLL_Input; //In 10Khz unit ++ USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output ++ ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; ++ USHORT usReferenceClock; //In 10Khz unit ++ USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit ++ UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit ++ UCHAR ucDesign_ID; //Indicate what is the board design ++ UCHAR ucMemoryModule_ID; //Indicate what is the board design ++}ATOM_FIRMWARE_INFO_V1_2; ++ ++typedef struct _ATOM_FIRMWARE_INFO_V1_3 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ULONG ulFirmwareRevision; ++ ULONG ulDefaultEngineClock; //In 10Khz unit ++ ULONG ulDefaultMemoryClock; //In 10Khz unit ++ ULONG ulDriverTargetEngineClock; //In 10Khz unit ++ ULONG ulDriverTargetMemoryClock; //In 10Khz unit ++ ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit ++ ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit ++ ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit ++ ULONG ulASICMaxEngineClock; //In 10Khz unit ++ ULONG ulASICMaxMemoryClock; //In 10Khz unit ++ UCHAR ucASICMaxTemperature; ++ UCHAR ucMinAllowedBL_Level; ++ UCHAR ucPadding[2]; //Don't use them ++ ULONG aulReservedForBIOS; //Don't use them ++ ULONG ul3DAccelerationEngineClock;//In 10Khz unit ++ ULONG ulMinPixelClockPLL_Output; //In 10Khz unit ++ USHORT usMinEngineClockPLL_Input; //In 10Khz unit ++ USHORT usMaxEngineClockPLL_Input; //In 10Khz unit ++ USHORT usMinEngineClockPLL_Output; //In 10Khz unit ++ USHORT usMinMemoryClockPLL_Input; //In 10Khz unit ++ USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit ++ USHORT usMinMemoryClockPLL_Output; //In 10Khz unit ++ USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk ++ USHORT usMinPixelClockPLL_Input; //In 10Khz unit ++ USHORT usMaxPixelClockPLL_Input; //In 10Khz unit ++ USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output ++ ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; ++ USHORT usReferenceClock; //In 10Khz unit ++ USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit ++ UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit ++ UCHAR ucDesign_ID; //Indicate what is the board design ++ UCHAR ucMemoryModule_ID; //Indicate what is the board design ++}ATOM_FIRMWARE_INFO_V1_3; ++ ++typedef struct _ATOM_FIRMWARE_INFO_V1_4 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ULONG ulFirmwareRevision; ++ ULONG ulDefaultEngineClock; //In 10Khz unit ++ ULONG ulDefaultMemoryClock; //In 10Khz unit ++ ULONG ulDriverTargetEngineClock; //In 10Khz unit ++ ULONG ulDriverTargetMemoryClock; //In 10Khz unit ++ ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit ++ ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit ++ ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit ++ ULONG ulASICMaxEngineClock; //In 10Khz unit ++ ULONG ulASICMaxMemoryClock; //In 10Khz unit ++ UCHAR ucASICMaxTemperature; ++ UCHAR ucMinAllowedBL_Level; ++ USHORT usBootUpVDDCVoltage; //In MV unit ++ USHORT usLcdMinPixelClockPLL_Output; // In MHz unit ++ USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit ++ ULONG ul3DAccelerationEngineClock;//In 10Khz unit ++ ULONG ulMinPixelClockPLL_Output; //In 10Khz unit ++ USHORT usMinEngineClockPLL_Input; //In 10Khz unit ++ USHORT usMaxEngineClockPLL_Input; //In 10Khz unit ++ USHORT usMinEngineClockPLL_Output; //In 10Khz unit ++ USHORT usMinMemoryClockPLL_Input; //In 10Khz unit ++ USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit ++ USHORT usMinMemoryClockPLL_Output; //In 10Khz unit ++ USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk ++ USHORT usMinPixelClockPLL_Input; //In 10Khz unit ++ USHORT usMaxPixelClockPLL_Input; //In 10Khz unit ++ USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output ++ ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; ++ USHORT usReferenceClock; //In 10Khz unit ++ USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit ++ UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit ++ UCHAR ucDesign_ID; //Indicate what is the board design ++ UCHAR ucMemoryModule_ID; //Indicate what is the board design ++}ATOM_FIRMWARE_INFO_V1_4; ++ ++//the structure below to be used from Cypress ++typedef struct _ATOM_FIRMWARE_INFO_V2_1 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ULONG ulFirmwareRevision; ++ ULONG ulDefaultEngineClock; //In 10Khz unit ++ ULONG ulDefaultMemoryClock; //In 10Khz unit ++ ULONG ulReserved1; ++ ULONG ulReserved2; ++ ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit ++ ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit ++ ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit ++ ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ++ ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit ++ UCHAR ucReserved1; //Was ucASICMaxTemperature; ++ UCHAR ucMinAllowedBL_Level; ++ USHORT usBootUpVDDCVoltage; //In MV unit ++ USHORT usLcdMinPixelClockPLL_Output; // In MHz unit ++ USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit ++ ULONG ulReserved4; //Was ulAsicMaximumVoltage ++ ULONG ulMinPixelClockPLL_Output; //In 10Khz unit ++ USHORT usMinEngineClockPLL_Input; //In 10Khz unit ++ USHORT usMaxEngineClockPLL_Input; //In 10Khz unit ++ USHORT usMinEngineClockPLL_Output; //In 10Khz unit ++ USHORT usMinMemoryClockPLL_Input; //In 10Khz unit ++ USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit ++ USHORT usMinMemoryClockPLL_Output; //In 10Khz unit ++ USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk ++ USHORT usMinPixelClockPLL_Input; //In 10Khz unit ++ USHORT usMaxPixelClockPLL_Input; //In 10Khz unit ++ USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output ++ ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; ++ USHORT usCoreReferenceClock; //In 10Khz unit ++ USHORT usMemoryReferenceClock; //In 10Khz unit ++ USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock ++ UCHAR ucMemoryModule_ID; //Indicate what is the board design ++ UCHAR ucReserved4[3]; ++}ATOM_FIRMWARE_INFO_V2_1; ++ ++ ++#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_1 ++ ++/****************************************************************************/ ++// Structures used in IntegratedSystemInfoTable ++/****************************************************************************/ + #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 + #define IGP_CAP_FLAG_AC_CARD 0x4 + #define IGP_CAP_FLAG_SDVO_CARD 0x8 + #define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10 + +-typedef struct _ATOM_INTEGRATED_SYSTEM_INFO { +- ATOM_COMMON_TABLE_HEADER sHeader; +- ULONG ulBootUpEngineClock; /* in 10kHz unit */ +- ULONG ulBootUpMemoryClock; /* in 10kHz unit */ +- ULONG ulMaxSystemMemoryClock; /* in 10kHz unit */ +- ULONG ulMinSystemMemoryClock; /* in 10kHz unit */ +- UCHAR ucNumberOfCyclesInPeriodHi; +- UCHAR ucLCDTimingSel; /* =0:not valid.!=0 sel this timing descriptor from LCD EDID. */ +- USHORT usReserved1; +- USHORT usInterNBVoltageLow; /* An intermidiate PMW value to set the voltage */ +- USHORT usInterNBVoltageHigh; /* Another intermidiate PMW value to set the voltage */ +- ULONG ulReserved[2]; +- +- USHORT usFSBClock; /* In MHz unit */ +- USHORT usCapabilityFlag; /* Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable */ +- /* Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card */ +- /* Bit[4]==1: P/2 mode, ==0: P/1 mode */ +- USHORT usPCIENBCfgReg7; /* bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal */ +- USHORT usK8MemoryClock; /* in MHz unit */ +- USHORT usK8SyncStartDelay; /* in 0.01 us unit */ +- USHORT usK8DataReturnTime; /* in 0.01 us unit */ +- UCHAR ucMaxNBVoltage; +- UCHAR ucMinNBVoltage; +- UCHAR ucMemoryType; /* [7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved */ +- UCHAR ucNumberOfCyclesInPeriod; /* CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod */ +- UCHAR ucStartingPWM_HighTime; /* CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime */ +- UCHAR ucHTLinkWidth; /* 16 bit vs. 8 bit */ +- UCHAR ucMaxNBVoltageHigh; +- UCHAR ucMinNBVoltageHigh; +-} ATOM_INTEGRATED_SYSTEM_INFO; ++typedef struct _ATOM_INTEGRATED_SYSTEM_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ULONG ulBootUpEngineClock; //in 10kHz unit ++ ULONG ulBootUpMemoryClock; //in 10kHz unit ++ ULONG ulMaxSystemMemoryClock; //in 10kHz unit ++ ULONG ulMinSystemMemoryClock; //in 10kHz unit ++ UCHAR ucNumberOfCyclesInPeriodHi; ++ UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID. ++ USHORT usReserved1; ++ USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage ++ USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage ++ ULONG ulReserved[2]; ++ ++ USHORT usFSBClock; //In MHz unit ++ USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable ++ //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card ++ //Bit[4]==1: P/2 mode, ==0: P/1 mode ++ USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal ++ USHORT usK8MemoryClock; //in MHz unit ++ USHORT usK8SyncStartDelay; //in 0.01 us unit ++ USHORT usK8DataReturnTime; //in 0.01 us unit ++ UCHAR ucMaxNBVoltage; ++ UCHAR ucMinNBVoltage; ++ UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved ++ UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod ++ UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime ++ UCHAR ucHTLinkWidth; //16 bit vs. 8 bit ++ UCHAR ucMaxNBVoltageHigh; ++ UCHAR ucMinNBVoltageHigh; ++}ATOM_INTEGRATED_SYSTEM_INFO; + + /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO +-ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock ++ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock + For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock + ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 + For AMD IGP,for now this can be 0 +-ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 ++ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 + For AMD IGP,for now this can be 0 + +-usFSBClock: For Intel IGP,it's FSB Freq ++usFSBClock: For Intel IGP,it's FSB Freq + For AMD IGP,it's HT Link Speed + + usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 +@@ -1687,98 +2093,113 @@ VC:Voltage Control + ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. + ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. + +-ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. +-ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 ++ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. ++ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 + + ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. + ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. + ++ + usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. + usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. + */ + ++ + /* + The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; +-Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. ++Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. + The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. + + SW components can access the IGP system infor structure in the same way as before + */ + +-typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 { +- ATOM_COMMON_TABLE_HEADER sHeader; +- ULONG ulBootUpEngineClock; /* in 10kHz unit */ +- ULONG ulReserved1[2]; /* must be 0x0 for the reserved */ +- ULONG ulBootUpUMAClock; /* in 10kHz unit */ +- ULONG ulBootUpSidePortClock; /* in 10kHz unit */ +- ULONG ulMinSidePortClock; /* in 10kHz unit */ +- ULONG ulReserved2[6]; /* must be 0x0 for the reserved */ +- ULONG ulSystemConfig; /* see explanation below */ +- ULONG ulBootUpReqDisplayVector; +- ULONG ulOtherDisplayMisc; +- ULONG ulDDISlot1Config; +- ULONG ulDDISlot2Config; +- UCHAR ucMemoryType; /* [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved */ +- UCHAR ucUMAChannelNumber; +- UCHAR ucDockingPinBit; +- UCHAR ucDockingPinPolarity; +- ULONG ulDockingPinCFGInfo; +- ULONG ulCPUCapInfo; +- USHORT usNumberOfCyclesInPeriod; +- USHORT usMaxNBVoltage; +- USHORT usMinNBVoltage; +- USHORT usBootUpNBVoltage; +- ULONG ulHTLinkFreq; /* in 10Khz */ +- USHORT usMinHTLinkWidth; +- USHORT usMaxHTLinkWidth; +- USHORT usUMASyncStartDelay; +- USHORT usUMADataReturnTime; +- USHORT usLinkStatusZeroTime; +- USHORT usReserved; +- ULONG ulHighVoltageHTLinkFreq; /* in 10Khz */ +- ULONG ulLowVoltageHTLinkFreq; /* in 10Khz */ +- USHORT usMaxUpStreamHTLinkWidth; +- USHORT usMaxDownStreamHTLinkWidth; +- USHORT usMinUpStreamHTLinkWidth; +- USHORT usMinDownStreamHTLinkWidth; +- ULONG ulReserved3[97]; /* must be 0x0 */ +-} ATOM_INTEGRATED_SYSTEM_INFO_V2; ++ ++typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ULONG ulBootUpEngineClock; //in 10kHz unit ++ ULONG ulReserved1[2]; //must be 0x0 for the reserved ++ ULONG ulBootUpUMAClock; //in 10kHz unit ++ ULONG ulBootUpSidePortClock; //in 10kHz unit ++ ULONG ulMinSidePortClock; //in 10kHz unit ++ ULONG ulReserved2[6]; //must be 0x0 for the reserved ++ ULONG ulSystemConfig; //see explanation below ++ ULONG ulBootUpReqDisplayVector; ++ ULONG ulOtherDisplayMisc; ++ ULONG ulDDISlot1Config; ++ ULONG ulDDISlot2Config; ++ UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved ++ UCHAR ucUMAChannelNumber; ++ UCHAR ucDockingPinBit; ++ UCHAR ucDockingPinPolarity; ++ ULONG ulDockingPinCFGInfo; ++ ULONG ulCPUCapInfo; ++ USHORT usNumberOfCyclesInPeriod; ++ USHORT usMaxNBVoltage; ++ USHORT usMinNBVoltage; ++ USHORT usBootUpNBVoltage; ++ ULONG ulHTLinkFreq; //in 10Khz ++ USHORT usMinHTLinkWidth; ++ USHORT usMaxHTLinkWidth; ++ USHORT usUMASyncStartDelay; ++ USHORT usUMADataReturnTime; ++ USHORT usLinkStatusZeroTime; ++ USHORT usDACEfuse; //for storing badgap value (for RS880 only) ++ ULONG ulHighVoltageHTLinkFreq; // in 10Khz ++ ULONG ulLowVoltageHTLinkFreq; // in 10Khz ++ USHORT usMaxUpStreamHTLinkWidth; ++ USHORT usMaxDownStreamHTLinkWidth; ++ USHORT usMinUpStreamHTLinkWidth; ++ USHORT usMinDownStreamHTLinkWidth; ++ USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW. ++ USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us. ++ ULONG ulReserved3[96]; //must be 0x0 ++}ATOM_INTEGRATED_SYSTEM_INFO_V2; + + /* + ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; + ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present + ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock + +-ulSystemConfig: +-Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; ++ulSystemConfig: ++Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; + Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state + =0: system boots up at driver control state. Power state depends on PowerPlay table. + Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used. + Bit[3]=1: Only one power state(Performance) will be supported. + =0: Multiple power states supported from PowerPlay table. +-Bit[4]=1: CLMC is supported and enabled on current system. +- =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. +-Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. ++Bit[4]=1: CLMC is supported and enabled on current system. ++ =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. ++Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. + =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. + Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored. + =0: Voltage settings is determined by powerplay table. + Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. + =0: Enable CLMC as regular mode, CDLD and CILR will be enabled. ++Bit[8]=1: CDLF is supported and enabled on current system. ++ =0: CDLF is not supported or enabled on current system. ++Bit[9]=1: DLL Shut Down feature is enabled on current system. ++ =0: DLL Shut Down feature is not enabled or supported on current system. + + ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions. + + ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion; +- [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition; ++ [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSupportedStd definition; + + ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design). + [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) +- [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) +- [15:8] - Lane configuration attribute; ++ [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12) ++ When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time. ++ in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example: ++ one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2. ++ ++ [15:8] - Lane configuration attribute; + [23:16]- Connector type, possible value: + CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D + CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D + CONNECTOR_OBJECT_ID_HDMI_TYPE_A + CONNECTOR_OBJECT_ID_DISPLAYPORT ++ CONNECTOR_OBJECT_ID_eDP + [31:24]- Reserved + + ulDDISlot2Config: Same as Slot1. +@@ -1787,29 +2208,31 @@ For IGP, Hypermemory is the only memory type showed in CCC. + + ucUMAChannelNumber: how many channels for the UMA; + +-ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin ++ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin + ucDockingPinBit: which bit in this register to read the pin status; + ucDockingPinPolarity:Polarity of the pin when docked; + + ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, other bits reserved for now and must be 0x0 + + usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. +-usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. ++ ++usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. + usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. + GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0 + PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1 + GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE ++ + usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value. + + ulHTLinkFreq: Bootup HT link Frequency in 10Khz. +-usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. +- If CDLW enabled, both upstream and downstream width should be the same during bootup. +-usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. ++usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. + If CDLW enabled, both upstream and downstream width should be the same during bootup. ++usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. ++ If CDLW enabled, both upstream and downstream width should be the same during bootup. + +-usUMASyncStartDelay: Memory access latency, required for watermark calculation ++usUMASyncStartDelay: Memory access latency, required for watermark calculation + usUMADataReturnTime: Memory access latency, required for watermark calculation +-usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us ++usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us + for Griffin or Greyhound. SBIOS needs to convert to actual time by: + if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us) + if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) +@@ -1817,7 +2240,7 @@ for Griffin or Greyhound. SBIOS needs to convert to actual time by: + if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us) + + ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0. +- This must be less than or equal to ulHTLinkFreq(bootup frequency). ++ This must be less than or equal to ulHTLinkFreq(bootup frequency). + ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0. + This must be less than or equal to ulHighVoltageHTLinkFreq. + +@@ -1827,14 +2250,17 @@ usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to rep + usMinDownStreamHTLinkWidth: same as above. + */ + ++ + #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 + #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 +-#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 ++#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 + #define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008 + #define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010 + #define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020 + #define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040 + #define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080 ++#define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100 ++#define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200 + + #define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF + +@@ -1851,6 +2277,41 @@ usMinDownStreamHTLinkWidth: same as above. + + #define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000 + ++// IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR ++typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ULONG ulBootUpEngineClock; //in 10kHz unit ++ ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK. ++ ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge ++ ULONG ulBootUpUMAClock; //in 10kHz unit ++ ULONG ulReserved1[8]; //must be 0x0 for the reserved ++ ULONG ulBootUpReqDisplayVector; ++ ULONG ulOtherDisplayMisc; ++ ULONG ulReserved2[4]; //must be 0x0 for the reserved ++ ULONG ulSystemConfig; //TBD ++ ULONG ulCPUCapInfo; //TBD ++ USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; ++ USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; ++ USHORT usBootUpNBVoltage; //boot up NB voltage ++ UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD ++ UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD ++ ULONG ulReserved3[4]; //must be 0x0 for the reserved ++ ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition ++ ULONG ulDDISlot2Config; ++ ULONG ulDDISlot3Config; ++ ULONG ulDDISlot4Config; ++ ULONG ulReserved4[4]; //must be 0x0 for the reserved ++ UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved ++ UCHAR ucUMAChannelNumber; ++ USHORT usReserved; ++ ULONG ulReserved5[4]; //must be 0x0 for the reserved ++ ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default ++ ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback ++ ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications ++ ULONG ulReserved6[61]; //must be 0x0 ++}ATOM_INTEGRATED_SYSTEM_INFO_V5; ++ + #define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 + #define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 + #define ATOM_TV_INT_ENCODER1_INDEX 0x00000002 +@@ -1866,8 +2327,8 @@ usMinDownStreamHTLinkWidth: same as above. + #define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C + #define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D + +-/* define ASIC internal encoder id ( bit vector ) */ +-#define ASIC_INT_DAC1_ENCODER_ID 0x00 ++// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable ++#define ASIC_INT_DAC1_ENCODER_ID 0x00 + #define ASIC_INT_TV_ENCODER_ID 0x02 + #define ASIC_INT_DIG1_ENCODER_ID 0x03 + #define ASIC_INT_DAC2_ENCODER_ID 0x04 +@@ -1875,10 +2336,24 @@ usMinDownStreamHTLinkWidth: same as above. + #define ASIC_INT_DVO_ENCODER_ID 0x07 + #define ASIC_INT_DIG2_ENCODER_ID 0x09 + #define ASIC_EXT_DIG_ENCODER_ID 0x05 ++#define ASIC_EXT_DIG2_ENCODER_ID 0x08 ++#define ASIC_INT_DIG3_ENCODER_ID 0x0a ++#define ASIC_INT_DIG4_ENCODER_ID 0x0b ++#define ASIC_INT_DIG5_ENCODER_ID 0x0c ++#define ASIC_INT_DIG6_ENCODER_ID 0x0d + +-/* define Encoder attribute */ ++//define Encoder attribute + #define ATOM_ANALOG_ENCODER 0 +-#define ATOM_DIGITAL_ENCODER 1 ++#define ATOM_DIGITAL_ENCODER 1 ++#define ATOM_DP_ENCODER 2 ++ ++#define ATOM_ENCODER_ENUM_MASK 0x70 ++#define ATOM_ENCODER_ENUM_ID1 0x00 ++#define ATOM_ENCODER_ENUM_ID2 0x10 ++#define ATOM_ENCODER_ENUM_ID3 0x20 ++#define ATOM_ENCODER_ENUM_ID4 0x30 ++#define ATOM_ENCODER_ENUM_ID5 0x40 ++#define ATOM_ENCODER_ENUM_ID6 0x50 + + #define ATOM_DEVICE_CRT1_INDEX 0x00000000 + #define ATOM_DEVICE_LCD1_INDEX 0x00000001 +@@ -1886,45 +2361,40 @@ usMinDownStreamHTLinkWidth: same as above. + #define ATOM_DEVICE_DFP1_INDEX 0x00000003 + #define ATOM_DEVICE_CRT2_INDEX 0x00000004 + #define ATOM_DEVICE_LCD2_INDEX 0x00000005 +-#define ATOM_DEVICE_TV2_INDEX 0x00000006 ++#define ATOM_DEVICE_DFP6_INDEX 0x00000006 + #define ATOM_DEVICE_DFP2_INDEX 0x00000007 + #define ATOM_DEVICE_CV_INDEX 0x00000008 +-#define ATOM_DEVICE_DFP3_INDEX 0x00000009 +-#define ATOM_DEVICE_DFP4_INDEX 0x0000000A +-#define ATOM_DEVICE_DFP5_INDEX 0x0000000B ++#define ATOM_DEVICE_DFP3_INDEX 0x00000009 ++#define ATOM_DEVICE_DFP4_INDEX 0x0000000A ++#define ATOM_DEVICE_DFP5_INDEX 0x0000000B ++ + #define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C + #define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D + #define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E + #define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F + #define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1) + #define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO +-#define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1) ++#define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 ) + + #define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1) + +-#define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX) +-#define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX) +-#define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX) +-#define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX) +-#define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX) +-#define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX) +-#define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX) +-#define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX) +-#define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX) +-#define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX) +-#define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX ) +-#define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX) +- +-#define ATOM_DEVICE_CRT_SUPPORT \ +- (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT) +-#define ATOM_DEVICE_DFP_SUPPORT \ +- (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | \ +- ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | \ +- ATOM_DEVICE_DFP5_SUPPORT) +-#define ATOM_DEVICE_TV_SUPPORT \ +- (ATOM_DEVICE_TV1_SUPPORT | ATOM_DEVICE_TV2_SUPPORT) +-#define ATOM_DEVICE_LCD_SUPPORT \ +- (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT) ++#define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX ) ++#define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX ) ++#define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX ) ++#define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX ) ++#define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX ) ++#define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX ) ++#define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX ) ++#define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX ) ++#define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX ) ++#define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX ) ++#define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX ) ++#define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX ) ++ ++#define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT) ++#define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT) ++#define ATOM_DEVICE_TV_SUPPORT (ATOM_DEVICE_TV1_SUPPORT) ++#define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT) + + #define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0 + #define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004 +@@ -1942,6 +2412,7 @@ usMinDownStreamHTLinkWidth: same as above. + #define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E + #define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F + ++ + #define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F + #define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000 + #define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000 +@@ -1958,139 +2429,150 @@ usMinDownStreamHTLinkWidth: same as above. + #define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004 + #define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001 + #define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002 +-#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 /* For IGP RS600 */ +-#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 /* For IGP RS690 */ ++#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600 ++#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690 + + #define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080 + #define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007 + #define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000 + #define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001 + +-/* usDeviceSupport: */ +-/* Bits0 = 0 - no CRT1 support= 1- CRT1 is supported */ +-/* Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported */ +-/* Bit 2 = 0 - no TV1 support= 1- TV1 is supported */ +-/* Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported */ +-/* Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported */ +-/* Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported */ +-/* Bit 6 = 0 - no TV2 support= 1- TV2 is supported */ +-/* Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported */ +-/* Bit 8 = 0 - no CV support= 1- CV is supported */ +-/* Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported */ +-/* Byte1 (Supported Device Info) */ +-/* Bit 0 = = 0 - no CV support= 1- CV is supported */ +-/* */ +-/* */ +- +-/* ucI2C_ConfigID */ +-/* [7:0] - I2C LINE Associate ID */ +-/* = 0 - no I2C */ +-/* [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) */ +-/* = 0, [6:0]=SW assisted I2C ID */ +-/* [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use */ +-/* = 2, HW engine for Multimedia use */ +-/* = 3-7 Reserved for future I2C engines */ +-/* [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C */ +- +-typedef struct _ATOM_I2C_ID_CONFIG { +-#if ATOM_BIG_ENDIAN +- UCHAR bfHW_Capable:1; +- UCHAR bfHW_EngineID:3; +- UCHAR bfI2C_LineMux:4; +-#else +- UCHAR bfI2C_LineMux:4; +- UCHAR bfHW_EngineID:3; +- UCHAR bfHW_Capable:1; +-#endif +-} ATOM_I2C_ID_CONFIG; +- +-typedef union _ATOM_I2C_ID_CONFIG_ACCESS { +- ATOM_I2C_ID_CONFIG sbfAccess; +- UCHAR ucAccess; +-} ATOM_I2C_ID_CONFIG_ACCESS; ++// usDeviceSupport: ++// Bits0 = 0 - no CRT1 support= 1- CRT1 is supported ++// Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported ++// Bit 2 = 0 - no TV1 support= 1- TV1 is supported ++// Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported ++// Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported ++// Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported ++// Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported ++// Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported ++// Bit 8 = 0 - no CV support= 1- CV is supported ++// Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported ++// Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported ++// Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported ++// ++// + + /****************************************************************************/ +-/* Structure used in GPIO_I2C_InfoTable */ ++/* Structure used in MclkSS_InfoTable */ + /****************************************************************************/ +-typedef struct _ATOM_GPIO_I2C_ASSIGMENT { +- USHORT usClkMaskRegisterIndex; +- USHORT usClkEnRegisterIndex; +- USHORT usClkY_RegisterIndex; +- USHORT usClkA_RegisterIndex; +- USHORT usDataMaskRegisterIndex; +- USHORT usDataEnRegisterIndex; +- USHORT usDataY_RegisterIndex; +- USHORT usDataA_RegisterIndex; +- ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; +- UCHAR ucClkMaskShift; +- UCHAR ucClkEnShift; +- UCHAR ucClkY_Shift; +- UCHAR ucClkA_Shift; +- UCHAR ucDataMaskShift; +- UCHAR ucDataEnShift; +- UCHAR ucDataY_Shift; +- UCHAR ucDataA_Shift; +- UCHAR ucReserved1; +- UCHAR ucReserved2; +-} ATOM_GPIO_I2C_ASSIGMENT; +- +-typedef struct _ATOM_GPIO_I2C_INFO { +- ATOM_COMMON_TABLE_HEADER sHeader; +- ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; +-} ATOM_GPIO_I2C_INFO; ++// ucI2C_ConfigID ++// [7:0] - I2C LINE Associate ID ++// = 0 - no I2C ++// [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) ++// = 0, [6:0]=SW assisted I2C ID ++// [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use ++// = 2, HW engine for Multimedia use ++// = 3-7 Reserved for future I2C engines ++// [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C ++ ++typedef struct _ATOM_I2C_ID_CONFIG ++{ ++#if ATOM_BIG_ENDIAN ++ UCHAR bfHW_Capable:1; ++ UCHAR bfHW_EngineID:3; ++ UCHAR bfI2C_LineMux:4; ++#else ++ UCHAR bfI2C_LineMux:4; ++ UCHAR bfHW_EngineID:3; ++ UCHAR bfHW_Capable:1; ++#endif ++}ATOM_I2C_ID_CONFIG; + +-/****************************************************************************/ +-/* Common Structure used in other structures */ +-/****************************************************************************/ ++typedef union _ATOM_I2C_ID_CONFIG_ACCESS ++{ ++ ATOM_I2C_ID_CONFIG sbfAccess; ++ UCHAR ucAccess; ++}ATOM_I2C_ID_CONFIG_ACCESS; ++ ++ ++/****************************************************************************/ ++// Structure used in GPIO_I2C_InfoTable ++/****************************************************************************/ ++typedef struct _ATOM_GPIO_I2C_ASSIGMENT ++{ ++ USHORT usClkMaskRegisterIndex; ++ USHORT usClkEnRegisterIndex; ++ USHORT usClkY_RegisterIndex; ++ USHORT usClkA_RegisterIndex; ++ USHORT usDataMaskRegisterIndex; ++ USHORT usDataEnRegisterIndex; ++ USHORT usDataY_RegisterIndex; ++ USHORT usDataA_RegisterIndex; ++ ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; ++ UCHAR ucClkMaskShift; ++ UCHAR ucClkEnShift; ++ UCHAR ucClkY_Shift; ++ UCHAR ucClkA_Shift; ++ UCHAR ucDataMaskShift; ++ UCHAR ucDataEnShift; ++ UCHAR ucDataY_Shift; ++ UCHAR ucDataA_Shift; ++ UCHAR ucReserved1; ++ UCHAR ucReserved2; ++}ATOM_GPIO_I2C_ASSIGMENT; ++ ++typedef struct _ATOM_GPIO_I2C_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; ++}ATOM_GPIO_I2C_INFO; ++ ++/****************************************************************************/ ++// Common Structure used in other structures ++/****************************************************************************/ + + #ifndef _H2INC +- +-/* Please don't add or expand this bitfield structure below, this one will retire soon.! */ +-typedef struct _ATOM_MODE_MISC_INFO { ++ ++//Please don't add or expand this bitfield structure below, this one will retire soon.! ++typedef struct _ATOM_MODE_MISC_INFO ++{ + #if ATOM_BIG_ENDIAN +- USHORT Reserved:6; +- USHORT RGB888:1; +- USHORT DoubleClock:1; +- USHORT Interlace:1; +- USHORT CompositeSync:1; +- USHORT V_ReplicationBy2:1; +- USHORT H_ReplicationBy2:1; +- USHORT VerticalCutOff:1; +- USHORT VSyncPolarity:1; /* 0=Active High, 1=Active Low */ +- USHORT HSyncPolarity:1; /* 0=Active High, 1=Active Low */ +- USHORT HorizontalCutOff:1; ++ USHORT Reserved:6; ++ USHORT RGB888:1; ++ USHORT DoubleClock:1; ++ USHORT Interlace:1; ++ USHORT CompositeSync:1; ++ USHORT V_ReplicationBy2:1; ++ USHORT H_ReplicationBy2:1; ++ USHORT VerticalCutOff:1; ++ USHORT VSyncPolarity:1; //0=Active High, 1=Active Low ++ USHORT HSyncPolarity:1; //0=Active High, 1=Active Low ++ USHORT HorizontalCutOff:1; + #else +- USHORT HorizontalCutOff:1; +- USHORT HSyncPolarity:1; /* 0=Active High, 1=Active Low */ +- USHORT VSyncPolarity:1; /* 0=Active High, 1=Active Low */ +- USHORT VerticalCutOff:1; +- USHORT H_ReplicationBy2:1; +- USHORT V_ReplicationBy2:1; +- USHORT CompositeSync:1; +- USHORT Interlace:1; +- USHORT DoubleClock:1; +- USHORT RGB888:1; +- USHORT Reserved:6; ++ USHORT HorizontalCutOff:1; ++ USHORT HSyncPolarity:1; //0=Active High, 1=Active Low ++ USHORT VSyncPolarity:1; //0=Active High, 1=Active Low ++ USHORT VerticalCutOff:1; ++ USHORT H_ReplicationBy2:1; ++ USHORT V_ReplicationBy2:1; ++ USHORT CompositeSync:1; ++ USHORT Interlace:1; ++ USHORT DoubleClock:1; ++ USHORT RGB888:1; ++ USHORT Reserved:6; + #endif +-} ATOM_MODE_MISC_INFO; +- +-typedef union _ATOM_MODE_MISC_INFO_ACCESS { +- ATOM_MODE_MISC_INFO sbfAccess; +- USHORT usAccess; +-} ATOM_MODE_MISC_INFO_ACCESS; +- ++}ATOM_MODE_MISC_INFO; ++ ++typedef union _ATOM_MODE_MISC_INFO_ACCESS ++{ ++ ATOM_MODE_MISC_INFO sbfAccess; ++ USHORT usAccess; ++}ATOM_MODE_MISC_INFO_ACCESS; ++ + #else +- +-typedef union _ATOM_MODE_MISC_INFO_ACCESS { +- USHORT usAccess; +-} ATOM_MODE_MISC_INFO_ACCESS; +- ++ ++typedef union _ATOM_MODE_MISC_INFO_ACCESS ++{ ++ USHORT usAccess; ++}ATOM_MODE_MISC_INFO_ACCESS; ++ + #endif + +-/* usModeMiscInfo- */ ++// usModeMiscInfo- + #define ATOM_H_CUTOFF 0x01 +-#define ATOM_HSYNC_POLARITY 0x02 /* 0=Active High, 1=Active Low */ +-#define ATOM_VSYNC_POLARITY 0x04 /* 0=Active High, 1=Active Low */ ++#define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low ++#define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low + #define ATOM_V_CUTOFF 0x08 + #define ATOM_H_REPLICATIONBY2 0x10 + #define ATOM_V_REPLICATIONBY2 0x20 +@@ -2099,10 +2581,10 @@ typedef union _ATOM_MODE_MISC_INFO_ACCESS { + #define ATOM_DOUBLE_CLOCK_MODE 0x100 + #define ATOM_RGB888_MODE 0x200 + +-/* usRefreshRate- */ ++//usRefreshRate- + #define ATOM_REFRESH_43 43 + #define ATOM_REFRESH_47 47 +-#define ATOM_REFRESH_56 56 ++#define ATOM_REFRESH_56 56 + #define ATOM_REFRESH_60 60 + #define ATOM_REFRESH_65 65 + #define ATOM_REFRESH_70 70 +@@ -2110,192 +2592,233 @@ typedef union _ATOM_MODE_MISC_INFO_ACCESS { + #define ATOM_REFRESH_75 75 + #define ATOM_REFRESH_85 85 + +-/* ATOM_MODE_TIMING data are exactly the same as VESA timing data. */ +-/* Translation from EDID to ATOM_MODE_TIMING, use the following formula. */ +-/* */ +-/* VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK */ +-/* = EDID_HA + EDID_HBL */ +-/* VESA_HDISP = VESA_ACTIVE = EDID_HA */ +-/* VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH */ +-/* = EDID_HA + EDID_HSO */ +-/* VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW */ +-/* VESA_BORDER = EDID_BORDER */ +- +-/****************************************************************************/ +-/* Structure used in SetCRTC_UsingDTDTimingTable */ +-/****************************************************************************/ +-typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS { +- USHORT usH_Size; +- USHORT usH_Blanking_Time; +- USHORT usV_Size; +- USHORT usV_Blanking_Time; +- USHORT usH_SyncOffset; +- USHORT usH_SyncWidth; +- USHORT usV_SyncOffset; +- USHORT usV_SyncWidth; +- ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; +- UCHAR ucH_Border; /* From DFP EDID */ +- UCHAR ucV_Border; +- UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ +- UCHAR ucPadding[3]; +-} SET_CRTC_USING_DTD_TIMING_PARAMETERS; +- +-/****************************************************************************/ +-/* Structure used in SetCRTC_TimingTable */ +-/****************************************************************************/ +-typedef struct _SET_CRTC_TIMING_PARAMETERS { +- USHORT usH_Total; /* horizontal total */ +- USHORT usH_Disp; /* horizontal display */ +- USHORT usH_SyncStart; /* horozontal Sync start */ +- USHORT usH_SyncWidth; /* horizontal Sync width */ +- USHORT usV_Total; /* vertical total */ +- USHORT usV_Disp; /* vertical display */ +- USHORT usV_SyncStart; /* vertical Sync start */ +- USHORT usV_SyncWidth; /* vertical Sync width */ +- ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; +- UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ +- UCHAR ucOverscanRight; /* right */ +- UCHAR ucOverscanLeft; /* left */ +- UCHAR ucOverscanBottom; /* bottom */ +- UCHAR ucOverscanTop; /* top */ +- UCHAR ucReserved; +-} SET_CRTC_TIMING_PARAMETERS; ++// ATOM_MODE_TIMING data are exactly the same as VESA timing data. ++// Translation from EDID to ATOM_MODE_TIMING, use the following formula. ++// ++// VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK ++// = EDID_HA + EDID_HBL ++// VESA_HDISP = VESA_ACTIVE = EDID_HA ++// VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH ++// = EDID_HA + EDID_HSO ++// VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW ++// VESA_BORDER = EDID_BORDER ++ ++/****************************************************************************/ ++// Structure used in SetCRTC_UsingDTDTimingTable ++/****************************************************************************/ ++typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS ++{ ++ USHORT usH_Size; ++ USHORT usH_Blanking_Time; ++ USHORT usV_Size; ++ USHORT usV_Blanking_Time; ++ USHORT usH_SyncOffset; ++ USHORT usH_SyncWidth; ++ USHORT usV_SyncOffset; ++ USHORT usV_SyncWidth; ++ ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; ++ UCHAR ucH_Border; // From DFP EDID ++ UCHAR ucV_Border; ++ UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 ++ UCHAR ucPadding[3]; ++}SET_CRTC_USING_DTD_TIMING_PARAMETERS; ++ ++/****************************************************************************/ ++// Structure used in SetCRTC_TimingTable ++/****************************************************************************/ ++typedef struct _SET_CRTC_TIMING_PARAMETERS ++{ ++ USHORT usH_Total; // horizontal total ++ USHORT usH_Disp; // horizontal display ++ USHORT usH_SyncStart; // horozontal Sync start ++ USHORT usH_SyncWidth; // horizontal Sync width ++ USHORT usV_Total; // vertical total ++ USHORT usV_Disp; // vertical display ++ USHORT usV_SyncStart; // vertical Sync start ++ USHORT usV_SyncWidth; // vertical Sync width ++ ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; ++ UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 ++ UCHAR ucOverscanRight; // right ++ UCHAR ucOverscanLeft; // left ++ UCHAR ucOverscanBottom; // bottom ++ UCHAR ucOverscanTop; // top ++ UCHAR ucReserved; ++}SET_CRTC_TIMING_PARAMETERS; + #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS + +-/****************************************************************************/ +-/* Structure used in StandardVESA_TimingTable */ +-/* AnalogTV_InfoTable */ +-/* ComponentVideoInfoTable */ +-/****************************************************************************/ +-typedef struct _ATOM_MODE_TIMING { +- USHORT usCRTC_H_Total; +- USHORT usCRTC_H_Disp; +- USHORT usCRTC_H_SyncStart; +- USHORT usCRTC_H_SyncWidth; +- USHORT usCRTC_V_Total; +- USHORT usCRTC_V_Disp; +- USHORT usCRTC_V_SyncStart; +- USHORT usCRTC_V_SyncWidth; +- USHORT usPixelClock; /* in 10Khz unit */ +- ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; +- USHORT usCRTC_OverscanRight; +- USHORT usCRTC_OverscanLeft; +- USHORT usCRTC_OverscanBottom; +- USHORT usCRTC_OverscanTop; +- USHORT usReserve; +- UCHAR ucInternalModeNumber; +- UCHAR ucRefreshRate; +-} ATOM_MODE_TIMING; +- +-typedef struct _ATOM_DTD_FORMAT { +- USHORT usPixClk; +- USHORT usHActive; +- USHORT usHBlanking_Time; +- USHORT usVActive; +- USHORT usVBlanking_Time; +- USHORT usHSyncOffset; +- USHORT usHSyncWidth; +- USHORT usVSyncOffset; +- USHORT usVSyncWidth; +- USHORT usImageHSize; +- USHORT usImageVSize; +- UCHAR ucHBorder; +- UCHAR ucVBorder; +- ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; +- UCHAR ucInternalModeNumber; +- UCHAR ucRefreshRate; +-} ATOM_DTD_FORMAT; +- +-/****************************************************************************/ +-/* Structure used in LVDS_InfoTable */ +-/* * Need a document to describe this table */ +-/****************************************************************************/ ++/****************************************************************************/ ++// Structure used in StandardVESA_TimingTable ++// AnalogTV_InfoTable ++// ComponentVideoInfoTable ++/****************************************************************************/ ++typedef struct _ATOM_MODE_TIMING ++{ ++ USHORT usCRTC_H_Total; ++ USHORT usCRTC_H_Disp; ++ USHORT usCRTC_H_SyncStart; ++ USHORT usCRTC_H_SyncWidth; ++ USHORT usCRTC_V_Total; ++ USHORT usCRTC_V_Disp; ++ USHORT usCRTC_V_SyncStart; ++ USHORT usCRTC_V_SyncWidth; ++ USHORT usPixelClock; //in 10Khz unit ++ ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; ++ USHORT usCRTC_OverscanRight; ++ USHORT usCRTC_OverscanLeft; ++ USHORT usCRTC_OverscanBottom; ++ USHORT usCRTC_OverscanTop; ++ USHORT usReserve; ++ UCHAR ucInternalModeNumber; ++ UCHAR ucRefreshRate; ++}ATOM_MODE_TIMING; ++ ++typedef struct _ATOM_DTD_FORMAT ++{ ++ USHORT usPixClk; ++ USHORT usHActive; ++ USHORT usHBlanking_Time; ++ USHORT usVActive; ++ USHORT usVBlanking_Time; ++ USHORT usHSyncOffset; ++ USHORT usHSyncWidth; ++ USHORT usVSyncOffset; ++ USHORT usVSyncWidth; ++ USHORT usImageHSize; ++ USHORT usImageVSize; ++ UCHAR ucHBorder; ++ UCHAR ucVBorder; ++ ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; ++ UCHAR ucInternalModeNumber; ++ UCHAR ucRefreshRate; ++}ATOM_DTD_FORMAT; ++ ++/****************************************************************************/ ++// Structure used in LVDS_InfoTable ++// * Need a document to describe this table ++/****************************************************************************/ + #define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 + #define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 + #define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 + #define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 + +-/* Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. */ +-/* Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL */ +-#define LCDPANEL_CAP_READ_EDID 0x1 +- +-/* ucTableFormatRevision=1 */ +-/* ucTableContentRevision=1 */ +-typedef struct _ATOM_LVDS_INFO { +- ATOM_COMMON_TABLE_HEADER sHeader; +- ATOM_DTD_FORMAT sLCDTiming; +- USHORT usModePatchTableOffset; +- USHORT usSupportedRefreshRate; /* Refer to panel info table in ATOMBIOS extension Spec. */ +- USHORT usOffDelayInMs; +- UCHAR ucPowerSequenceDigOntoDEin10Ms; +- UCHAR ucPowerSequenceDEtoBLOnin10Ms; +- UCHAR ucLVDS_Misc; /* Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} */ +- /* Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} */ +- /* Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} */ +- /* Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} */ +- UCHAR ucPanelDefaultRefreshRate; +- UCHAR ucPanelIdentification; +- UCHAR ucSS_Id; +-} ATOM_LVDS_INFO; +- +-/* ucTableFormatRevision=1 */ +-/* ucTableContentRevision=2 */ +-typedef struct _ATOM_LVDS_INFO_V12 { +- ATOM_COMMON_TABLE_HEADER sHeader; +- ATOM_DTD_FORMAT sLCDTiming; +- USHORT usExtInfoTableOffset; +- USHORT usSupportedRefreshRate; /* Refer to panel info table in ATOMBIOS extension Spec. */ +- USHORT usOffDelayInMs; +- UCHAR ucPowerSequenceDigOntoDEin10Ms; +- UCHAR ucPowerSequenceDEtoBLOnin10Ms; +- UCHAR ucLVDS_Misc; /* Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} */ +- /* Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} */ +- /* Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} */ +- /* Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} */ +- UCHAR ucPanelDefaultRefreshRate; +- UCHAR ucPanelIdentification; +- UCHAR ucSS_Id; +- USHORT usLCDVenderID; +- USHORT usLCDProductID; +- UCHAR ucLCDPanel_SpecialHandlingCap; +- UCHAR ucPanelInfoSize; /* start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable */ +- UCHAR ucReserved[2]; +-} ATOM_LVDS_INFO_V12; ++//ucTableFormatRevision=1 ++//ucTableContentRevision=1 ++typedef struct _ATOM_LVDS_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_DTD_FORMAT sLCDTiming; ++ USHORT usModePatchTableOffset; ++ USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. ++ USHORT usOffDelayInMs; ++ UCHAR ucPowerSequenceDigOntoDEin10Ms; ++ UCHAR ucPowerSequenceDEtoBLOnin10Ms; ++ UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} ++ // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} ++ // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} ++ // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} ++ UCHAR ucPanelDefaultRefreshRate; ++ UCHAR ucPanelIdentification; ++ UCHAR ucSS_Id; ++}ATOM_LVDS_INFO; ++ ++//ucTableFormatRevision=1 ++//ucTableContentRevision=2 ++typedef struct _ATOM_LVDS_INFO_V12 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_DTD_FORMAT sLCDTiming; ++ USHORT usExtInfoTableOffset; ++ USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. ++ USHORT usOffDelayInMs; ++ UCHAR ucPowerSequenceDigOntoDEin10Ms; ++ UCHAR ucPowerSequenceDEtoBLOnin10Ms; ++ UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} ++ // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} ++ // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} ++ // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} ++ UCHAR ucPanelDefaultRefreshRate; ++ UCHAR ucPanelIdentification; ++ UCHAR ucSS_Id; ++ USHORT usLCDVenderID; ++ USHORT usLCDProductID; ++ UCHAR ucLCDPanel_SpecialHandlingCap; ++ UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable ++ UCHAR ucReserved[2]; ++}ATOM_LVDS_INFO_V12; ++ ++//Definitions for ucLCDPanel_SpecialHandlingCap: ++ ++//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. ++//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL ++#define LCDPANEL_CAP_READ_EDID 0x1 ++ ++//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together ++//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static ++//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 ++#define LCDPANEL_CAP_DRR_SUPPORTED 0x2 ++ ++//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. ++#define LCDPANEL_CAP_eDP 0x4 ++ ++ ++//Color Bit Depth definition in EDID V1.4 @BYTE 14h ++//Bit 6 5 4 ++ // 0 0 0 - Color bit depth is undefined ++ // 0 0 1 - 6 Bits per Primary Color ++ // 0 1 0 - 8 Bits per Primary Color ++ // 0 1 1 - 10 Bits per Primary Color ++ // 1 0 0 - 12 Bits per Primary Color ++ // 1 0 1 - 14 Bits per Primary Color ++ // 1 1 0 - 16 Bits per Primary Color ++ // 1 1 1 - Reserved ++ ++#define PANEL_COLOR_BIT_DEPTH_MASK 0x70 ++ ++// Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} ++#define PANEL_RANDOM_DITHER 0x80 ++#define PANEL_RANDOM_DITHER_MASK 0x80 ++ + + #define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 + +-typedef struct _ATOM_PATCH_RECORD_MODE { +- UCHAR ucRecordType; +- USHORT usHDisp; +- USHORT usVDisp; +-} ATOM_PATCH_RECORD_MODE; ++typedef struct _ATOM_PATCH_RECORD_MODE ++{ ++ UCHAR ucRecordType; ++ USHORT usHDisp; ++ USHORT usVDisp; ++}ATOM_PATCH_RECORD_MODE; + +-typedef struct _ATOM_LCD_RTS_RECORD { +- UCHAR ucRecordType; +- UCHAR ucRTSValue; +-} ATOM_LCD_RTS_RECORD; ++typedef struct _ATOM_LCD_RTS_RECORD ++{ ++ UCHAR ucRecordType; ++ UCHAR ucRTSValue; ++}ATOM_LCD_RTS_RECORD; + +-/* !! If the record below exits, it shoud always be the first record for easy use in command table!!! */ +-typedef struct _ATOM_LCD_MODE_CONTROL_CAP { +- UCHAR ucRecordType; +- USHORT usLCDCap; +-} ATOM_LCD_MODE_CONTROL_CAP; ++//!! If the record below exits, it shoud always be the first record for easy use in command table!!! ++// The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead. ++typedef struct _ATOM_LCD_MODE_CONTROL_CAP ++{ ++ UCHAR ucRecordType; ++ USHORT usLCDCap; ++}ATOM_LCD_MODE_CONTROL_CAP; + + #define LCD_MODE_CAP_BL_OFF 1 + #define LCD_MODE_CAP_CRTC_OFF 2 + #define LCD_MODE_CAP_PANEL_OFF 4 + +-typedef struct _ATOM_FAKE_EDID_PATCH_RECORD { +- UCHAR ucRecordType; +- UCHAR ucFakeEDIDLength; +- UCHAR ucFakeEDIDString[1]; /* This actually has ucFakeEdidLength elements. */ ++typedef struct _ATOM_FAKE_EDID_PATCH_RECORD ++{ ++ UCHAR ucRecordType; ++ UCHAR ucFakeEDIDLength; ++ UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements. + } ATOM_FAKE_EDID_PATCH_RECORD; + +-typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD { +- UCHAR ucRecordType; +- USHORT usHSize; +- USHORT usVSize; +-} ATOM_PANEL_RESOLUTION_PATCH_RECORD; ++typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD ++{ ++ UCHAR ucRecordType; ++ USHORT usHSize; ++ USHORT usVSize; ++}ATOM_PANEL_RESOLUTION_PATCH_RECORD; + + #define LCD_MODE_PATCH_RECORD_MODE_TYPE 1 + #define LCD_RTS_RECORD_TYPE 2 +@@ -2306,21 +2829,25 @@ typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD { + + /****************************Spread Spectrum Info Table Definitions **********************/ + +-/* ucTableFormatRevision=1 */ +-/* ucTableContentRevision=2 */ +-typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT { +- USHORT usSpreadSpectrumPercentage; +- UCHAR ucSpreadSpectrumType; /* Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD */ +- UCHAR ucSS_Step; +- UCHAR ucSS_Delay; +- UCHAR ucSS_Id; +- UCHAR ucRecommendedRef_Div; +- UCHAR ucSS_Range; /* it was reserved for V11 */ +-} ATOM_SPREAD_SPECTRUM_ASSIGNMENT; ++//ucTableFormatRevision=1 ++//ucTableContentRevision=2 ++typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT ++{ ++ USHORT usSpreadSpectrumPercentage; ++ UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD ++ UCHAR ucSS_Step; ++ UCHAR ucSS_Delay; ++ UCHAR ucSS_Id; ++ UCHAR ucRecommendedRef_Div; ++ UCHAR ucSS_Range; //it was reserved for V11 ++}ATOM_SPREAD_SPECTRUM_ASSIGNMENT; + + #define ATOM_MAX_SS_ENTRY 16 +-#define ATOM_DP_SS_ID1 0x0f1 /* SS modulation freq=30k */ +-#define ATOM_DP_SS_ID2 0x0f2 /* SS modulation freq=33k */ ++#define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well. ++#define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable. ++#define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz ++#define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz ++ + + #define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 + #define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 +@@ -2329,29 +2856,30 @@ typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT { + #define ATOM_INTERNAL_SS_MASK 0x00000000 + #define ATOM_EXTERNAL_SS_MASK 0x00000002 + #define EXEC_SS_STEP_SIZE_SHIFT 2 +-#define EXEC_SS_DELAY_SHIFT 4 ++#define EXEC_SS_DELAY_SHIFT 4 + #define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4 + +-typedef struct _ATOM_SPREAD_SPECTRUM_INFO { +- ATOM_COMMON_TABLE_HEADER sHeader; +- ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; +-} ATOM_SPREAD_SPECTRUM_INFO; +- +-/****************************************************************************/ +-/* Structure used in AnalogTV_InfoTable (Top level) */ +-/****************************************************************************/ +-/* ucTVBootUpDefaultStd definiton: */ +- +-/* ATOM_TV_NTSC 1 */ +-/* ATOM_TV_NTSCJ 2 */ +-/* ATOM_TV_PAL 3 */ +-/* ATOM_TV_PALM 4 */ +-/* ATOM_TV_PALCN 5 */ +-/* ATOM_TV_PALN 6 */ +-/* ATOM_TV_PAL60 7 */ +-/* ATOM_TV_SECAM 8 */ +- +-/* ucTVSuppportedStd definition: */ ++typedef struct _ATOM_SPREAD_SPECTRUM_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; ++}ATOM_SPREAD_SPECTRUM_INFO; ++ ++/****************************************************************************/ ++// Structure used in AnalogTV_InfoTable (Top level) ++/****************************************************************************/ ++//ucTVBootUpDefaultStd definiton: ++ ++//ATOM_TV_NTSC 1 ++//ATOM_TV_NTSCJ 2 ++//ATOM_TV_PAL 3 ++//ATOM_TV_PALM 4 ++//ATOM_TV_PALCN 5 ++//ATOM_TV_PALN 6 ++//ATOM_TV_PAL60 7 ++//ATOM_TV_SECAM 8 ++ ++//ucTVSupportedStd definition: + #define NTSC_SUPPORT 0x1 + #define NTSCJ_SUPPORT 0x2 + +@@ -2364,46 +2892,58 @@ typedef struct _ATOM_SPREAD_SPECTRUM_INFO { + + #define MAX_SUPPORTED_TV_TIMING 2 + +-typedef struct _ATOM_ANALOG_TV_INFO { +- ATOM_COMMON_TABLE_HEADER sHeader; +- UCHAR ucTV_SupportedStandard; +- UCHAR ucTV_BootUpDefaultStandard; +- UCHAR ucExt_TV_ASIC_ID; +- UCHAR ucExt_TV_ASIC_SlaveAddr; +- /*ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING]; */ +- ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING]; +-} ATOM_ANALOG_TV_INFO; ++typedef struct _ATOM_ANALOG_TV_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ UCHAR ucTV_SupportedStandard; ++ UCHAR ucTV_BootUpDefaultStandard; ++ UCHAR ucExt_TV_ASIC_ID; ++ UCHAR ucExt_TV_ASIC_SlaveAddr; ++ /*ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];*/ ++ ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING]; ++}ATOM_ANALOG_TV_INFO; + + #define MAX_SUPPORTED_TV_TIMING_V1_2 3 + +-typedef struct _ATOM_ANALOG_TV_INFO_V1_2 { +- ATOM_COMMON_TABLE_HEADER sHeader; +- UCHAR ucTV_SupportedStandard; +- UCHAR ucTV_BootUpDefaultStandard; +- UCHAR ucExt_TV_ASIC_ID; +- UCHAR ucExt_TV_ASIC_SlaveAddr; +- ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING]; +-} ATOM_ANALOG_TV_INFO_V1_2; ++typedef struct _ATOM_ANALOG_TV_INFO_V1_2 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ UCHAR ucTV_SupportedStandard; ++ UCHAR ucTV_BootUpDefaultStandard; ++ UCHAR ucExt_TV_ASIC_ID; ++ UCHAR ucExt_TV_ASIC_SlaveAddr; ++ ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING]; ++}ATOM_ANALOG_TV_INFO_V1_2; ++ ++typedef struct _ATOM_DPCD_INFO ++{ ++ UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1 ++ UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane ++ UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP ++ UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec) ++}ATOM_DPCD_INFO; ++ ++#define ATOM_DPCD_MAX_LANE_MASK 0x1F + + /**************************************************************************/ +-/* VRAM usage and their definitions */ ++// VRAM usage and their defintions + +-/* One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. */ +-/* Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. */ +-/* All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! */ +-/* To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR */ +-/* To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX */ ++// One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. ++// Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. ++// All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! ++// To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR ++// To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX + + #ifndef VESA_MEMORY_IN_64K_BLOCK +-#define VESA_MEMORY_IN_64K_BLOCK 0x100 /* 256*64K=16Mb (Max. VESA memory is 16Mb!) */ ++#define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) + #endif + +-#define ATOM_EDID_RAW_DATASIZE 256 /* In Bytes */ +-#define ATOM_HWICON_SURFACE_SIZE 4096 /* In Bytes */ ++#define ATOM_EDID_RAW_DATASIZE 256 //In Bytes ++#define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes + #define ATOM_HWICON_INFOTABLE_SIZE 32 + #define MAX_DTD_MODE_IN_VRAM 6 +-#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) /* 28= (SIZEOF ATOM_DTD_FORMAT) */ +-#define ATOM_STD_MODE_SUPPORT_TBL_SIZE (32*8) /* 32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) */ ++#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) ++#define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) + #define DFP_ENCODER_TYPE_OFFSET 0x80 + #define DP_ENCODER_LANE_NUM_OFFSET 0x84 + #define DP_ENCODER_LINK_RATE_OFFSET 0x88 +@@ -2417,7 +2957,7 @@ typedef struct _ATOM_ANALOG_TV_INFO_V1_2 { + + #define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) + #define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) +-#define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) ++#define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + + #define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) + +@@ -2431,13 +2971,13 @@ typedef struct _ATOM_ANALOG_TV_INFO_V1_2 { + + #define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) + #define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) +-#define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) ++#define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + +-#define ATOM_TV2_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) +-#define ATOM_TV2_DTD_MODE_TBL_ADDR (ATOM_TV2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) +-#define ATOM_TV2_STD_MODE_TBL_ADDR (ATOM_TV2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) ++#define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) ++#define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) ++#define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + +-#define ATOM_DFP2_EDID_ADDR (ATOM_TV2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) ++#define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) + #define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) + #define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + +@@ -2457,533 +2997,850 @@ typedef struct _ATOM_ANALOG_TV_INFO_V1_2 { + #define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) + #define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) + +-#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR+ATOM_STD_MODE_SUPPORT_TBL_SIZE) ++#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR+ATOM_STD_MODE_SUPPORT_TBL_SIZE) + +-#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 256) +-#define ATOM_STACK_STORAGE_END (ATOM_STACK_STORAGE_START + 512) ++#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR+256) ++#define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START+512 + +-/* The size below is in Kb! */ ++//The size below is in Kb! + #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) +- ++ + #define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L + #define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 + #define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 + #define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 + +-/***********************************************************************************/ +-/* Structure used in VRAM_UsageByFirmwareTable */ +-/* Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm */ +-/* at running time. */ +-/* note2: From RV770, the memory is more than 32bit addressable, so we will change */ +-/* ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains */ +-/* exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware */ +-/* (in offset to start of memory address) is KB aligned instead of byte aligend. */ +-/***********************************************************************************/ ++/***********************************************************************************/ ++// Structure used in VRAM_UsageByFirmwareTable ++// Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm ++// at running time. ++// note2: From RV770, the memory is more than 32bit addressable, so we will change ++// ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains ++// exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware ++// (in offset to start of memory address) is KB aligned instead of byte aligend. ++/***********************************************************************************/ ++// Note3: ++/* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged constant across VGA or non VGA adapter, ++for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have: ++ ++If (ulStartAddrUsedByFirmware!=0) ++FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB; ++Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose ++else //Non VGA case ++ if (FB_Size<=2Gb) ++ FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB; ++ else ++ FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB ++ ++CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/ ++ + #define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1 + +-typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO { +- ULONG ulStartAddrUsedByFirmware; +- USHORT usFirmwareUseInKb; +- USHORT usReserved; +-} ATOM_FIRMWARE_VRAM_RESERVE_INFO; ++typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO ++{ ++ ULONG ulStartAddrUsedByFirmware; ++ USHORT usFirmwareUseInKb; ++ USHORT usReserved; ++}ATOM_FIRMWARE_VRAM_RESERVE_INFO; + +-typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE { +- ATOM_COMMON_TABLE_HEADER sHeader; +- ATOM_FIRMWARE_VRAM_RESERVE_INFO +- asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; +-} ATOM_VRAM_USAGE_BY_FIRMWARE; ++typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; ++}ATOM_VRAM_USAGE_BY_FIRMWARE; + +-/****************************************************************************/ +-/* Structure used in GPIO_Pin_LUTTable */ +-/****************************************************************************/ +-typedef struct _ATOM_GPIO_PIN_ASSIGNMENT { +- USHORT usGpioPin_AIndex; +- UCHAR ucGpioPinBitShift; +- UCHAR ucGPIO_ID; +-} ATOM_GPIO_PIN_ASSIGNMENT; ++// change verion to 1.5, when allow driver to allocate the vram area for command table access. ++typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 ++{ ++ ULONG ulStartAddrUsedByFirmware; ++ USHORT usFirmwareUseInKb; ++ USHORT usFBUsedByDrvInKb; ++}ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5; + +-typedef struct _ATOM_GPIO_PIN_LUT { +- ATOM_COMMON_TABLE_HEADER sHeader; +- ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1]; +-} ATOM_GPIO_PIN_LUT; ++typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; ++}ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5; ++ ++/****************************************************************************/ ++// Structure used in GPIO_Pin_LUTTable ++/****************************************************************************/ ++typedef struct _ATOM_GPIO_PIN_ASSIGNMENT ++{ ++ USHORT usGpioPin_AIndex; ++ UCHAR ucGpioPinBitShift; ++ UCHAR ucGPIO_ID; ++}ATOM_GPIO_PIN_ASSIGNMENT; + +-/****************************************************************************/ +-/* Structure used in ComponentVideoInfoTable */ +-/****************************************************************************/ ++typedef struct _ATOM_GPIO_PIN_LUT ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1]; ++}ATOM_GPIO_PIN_LUT; ++ ++/****************************************************************************/ ++// Structure used in ComponentVideoInfoTable ++/****************************************************************************/ + #define GPIO_PIN_ACTIVE_HIGH 0x1 + + #define MAX_SUPPORTED_CV_STANDARDS 5 + +-/* definitions for ATOM_D_INFO.ucSettings */ +-#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F /* [4:0] */ +-#define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 /* [6:5] = must be zeroed out */ +-#define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 /* [7] */ ++// definitions for ATOM_D_INFO.ucSettings ++#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0] ++#define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out ++#define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7] + +-typedef struct _ATOM_GPIO_INFO { +- USHORT usAOffset; +- UCHAR ucSettings; +- UCHAR ucReserved; +-} ATOM_GPIO_INFO; ++typedef struct _ATOM_GPIO_INFO ++{ ++ USHORT usAOffset; ++ UCHAR ucSettings; ++ UCHAR ucReserved; ++}ATOM_GPIO_INFO; + +-/* definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) */ ++// definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) + #define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2 + +-/* definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i */ +-#define ATOM_GPIO_DEFAULT_MODE_EN 0x80 /* [7]; */ +-#define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F /* [6:0] */ +- +-/* definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode */ +-/* Line 3 out put 5V. */ +-#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 /* represent gpio 3 state for 16:9 */ +-#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 /* represent gpio 4 state for 16:9 */ +-#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 +- +-/* Line 3 out put 2.2V */ +-#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 /* represent gpio 3 state for 4:3 Letter box */ +-#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 /* represent gpio 4 state for 4:3 Letter box */ +-#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 +- +-/* Line 3 out put 0V */ +-#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 /* represent gpio 3 state for 4:3 */ +-#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 /* represent gpio 4 state for 4:3 */ +-#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 +- +-#define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F /* bit [5:0] */ +- +-#define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 /* bit 7 */ +- +-/* GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. */ +-#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 /* bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. */ +-#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 /* bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. */ +- +-typedef struct _ATOM_COMPONENT_VIDEO_INFO { +- ATOM_COMMON_TABLE_HEADER sHeader; +- USHORT usMask_PinRegisterIndex; +- USHORT usEN_PinRegisterIndex; +- USHORT usY_PinRegisterIndex; +- USHORT usA_PinRegisterIndex; +- UCHAR ucBitShift; +- UCHAR ucPinActiveState; /* ucPinActiveState: Bit0=1 active high, =0 active low */ +- ATOM_DTD_FORMAT sReserved; /* must be zeroed out */ +- UCHAR ucMiscInfo; +- UCHAR uc480i; +- UCHAR uc480p; +- UCHAR uc720p; +- UCHAR uc1080i; +- UCHAR ucLetterBoxMode; +- UCHAR ucReserved[3]; +- UCHAR ucNumOfWbGpioBlocks; /* For Component video D-Connector support. If zere, NTSC type connector */ +- ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; +- ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; +-} ATOM_COMPONENT_VIDEO_INFO; +- +-/* ucTableFormatRevision=2 */ +-/* ucTableContentRevision=1 */ +-typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 { +- ATOM_COMMON_TABLE_HEADER sHeader; +- UCHAR ucMiscInfo; +- UCHAR uc480i; +- UCHAR uc480p; +- UCHAR uc720p; +- UCHAR uc1080i; +- UCHAR ucReserved; +- UCHAR ucLetterBoxMode; +- UCHAR ucNumOfWbGpioBlocks; /* For Component video D-Connector support. If zere, NTSC type connector */ +- ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; +- ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; +-} ATOM_COMPONENT_VIDEO_INFO_V21; ++// definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i ++#define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7]; ++#define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0] ++ ++// definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode ++//Line 3 out put 5V. ++#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9 ++#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9 ++#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 ++ ++//Line 3 out put 2.2V ++#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box ++#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box ++#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 ++ ++//Line 3 out put 0V ++#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3 ++#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3 ++#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 ++ ++#define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0] ++ ++#define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7 ++ ++//GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. ++#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. ++#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. ++ ++ ++typedef struct _ATOM_COMPONENT_VIDEO_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT usMask_PinRegisterIndex; ++ USHORT usEN_PinRegisterIndex; ++ USHORT usY_PinRegisterIndex; ++ USHORT usA_PinRegisterIndex; ++ UCHAR ucBitShift; ++ UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low ++ ATOM_DTD_FORMAT sReserved; // must be zeroed out ++ UCHAR ucMiscInfo; ++ UCHAR uc480i; ++ UCHAR uc480p; ++ UCHAR uc720p; ++ UCHAR uc1080i; ++ UCHAR ucLetterBoxMode; ++ UCHAR ucReserved[3]; ++ UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector ++ ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; ++ ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; ++}ATOM_COMPONENT_VIDEO_INFO; ++ ++//ucTableFormatRevision=2 ++//ucTableContentRevision=1 ++typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ UCHAR ucMiscInfo; ++ UCHAR uc480i; ++ UCHAR uc480p; ++ UCHAR uc720p; ++ UCHAR uc1080i; ++ UCHAR ucReserved; ++ UCHAR ucLetterBoxMode; ++ UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector ++ ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; ++ ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; ++}ATOM_COMPONENT_VIDEO_INFO_V21; + + #define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21 + +-/****************************************************************************/ +-/* Structure used in object_InfoTable */ +-/****************************************************************************/ +-typedef struct _ATOM_OBJECT_HEADER { +- ATOM_COMMON_TABLE_HEADER sHeader; +- USHORT usDeviceSupport; +- USHORT usConnectorObjectTableOffset; +- USHORT usRouterObjectTableOffset; +- USHORT usEncoderObjectTableOffset; +- USHORT usProtectionObjectTableOffset; /* only available when Protection block is independent. */ +- USHORT usDisplayPathTableOffset; +-} ATOM_OBJECT_HEADER; +- +-typedef struct _ATOM_DISPLAY_OBJECT_PATH { +- USHORT usDeviceTag; /* supported device */ +- USHORT usSize; /* the size of ATOM_DISPLAY_OBJECT_PATH */ +- USHORT usConnObjectId; /* Connector Object ID */ +- USHORT usGPUObjectId; /* GPU ID */ +- USHORT usGraphicObjIds[1]; /* 1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. */ +-} ATOM_DISPLAY_OBJECT_PATH; +- +-typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE { +- UCHAR ucNumOfDispPath; +- UCHAR ucVersion; +- UCHAR ucPadding[2]; +- ATOM_DISPLAY_OBJECT_PATH asDispPath[1]; +-} ATOM_DISPLAY_OBJECT_PATH_TABLE; +- +-typedef struct _ATOM_OBJECT /* each object has this structure */ +-{ +- USHORT usObjectID; +- USHORT usSrcDstTableOffset; +- USHORT usRecordOffset; /* this pointing to a bunch of records defined below */ +- USHORT usReserved; +-} ATOM_OBJECT; +- +-typedef struct _ATOM_OBJECT_TABLE /* Above 4 object table offset pointing to a bunch of objects all have this structure */ +-{ +- UCHAR ucNumberOfObjects; +- UCHAR ucPadding[3]; +- ATOM_OBJECT asObjects[1]; +-} ATOM_OBJECT_TABLE; +- +-typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT /* usSrcDstTableOffset pointing to this structure */ +-{ +- UCHAR ucNumberOfSrc; +- USHORT usSrcObjectID[1]; +- UCHAR ucNumberOfDst; +- USHORT usDstObjectID[1]; +-} ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; +- +-/* Related definitions, all records are differnt but they have a commond header */ +-typedef struct _ATOM_COMMON_RECORD_HEADER { +- UCHAR ucRecordType; /* An emun to indicate the record type */ +- UCHAR ucRecordSize; /* The size of the whole record in byte */ +-} ATOM_COMMON_RECORD_HEADER; +- +-#define ATOM_I2C_RECORD_TYPE 1 ++/****************************************************************************/ ++// Structure used in object_InfoTable ++/****************************************************************************/ ++typedef struct _ATOM_OBJECT_HEADER ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT usDeviceSupport; ++ USHORT usConnectorObjectTableOffset; ++ USHORT usRouterObjectTableOffset; ++ USHORT usEncoderObjectTableOffset; ++ USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. ++ USHORT usDisplayPathTableOffset; ++}ATOM_OBJECT_HEADER; ++ ++typedef struct _ATOM_OBJECT_HEADER_V3 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT usDeviceSupport; ++ USHORT usConnectorObjectTableOffset; ++ USHORT usRouterObjectTableOffset; ++ USHORT usEncoderObjectTableOffset; ++ USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. ++ USHORT usDisplayPathTableOffset; ++ USHORT usMiscObjectTableOffset; ++}ATOM_OBJECT_HEADER_V3; ++ ++typedef struct _ATOM_DISPLAY_OBJECT_PATH ++{ ++ USHORT usDeviceTag; //supported device ++ USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH ++ USHORT usConnObjectId; //Connector Object ID ++ USHORT usGPUObjectId; //GPU ID ++ USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. ++}ATOM_DISPLAY_OBJECT_PATH; ++ ++typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE ++{ ++ UCHAR ucNumOfDispPath; ++ UCHAR ucVersion; ++ UCHAR ucPadding[2]; ++ ATOM_DISPLAY_OBJECT_PATH asDispPath[1]; ++}ATOM_DISPLAY_OBJECT_PATH_TABLE; ++ ++ ++typedef struct _ATOM_OBJECT //each object has this structure ++{ ++ USHORT usObjectID; ++ USHORT usSrcDstTableOffset; ++ USHORT usRecordOffset; //this pointing to a bunch of records defined below ++ USHORT usReserved; ++}ATOM_OBJECT; ++ ++typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure ++{ ++ UCHAR ucNumberOfObjects; ++ UCHAR ucPadding[3]; ++ ATOM_OBJECT asObjects[1]; ++}ATOM_OBJECT_TABLE; ++ ++typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure ++{ ++ UCHAR ucNumberOfSrc; ++ USHORT usSrcObjectID[1]; ++ UCHAR ucNumberOfDst; ++ USHORT usDstObjectID[1]; ++}ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; ++ ++ ++//Two definitions below are for OPM on MXM module designs ++ ++#define EXT_HPDPIN_LUTINDEX_0 0 ++#define EXT_HPDPIN_LUTINDEX_1 1 ++#define EXT_HPDPIN_LUTINDEX_2 2 ++#define EXT_HPDPIN_LUTINDEX_3 3 ++#define EXT_HPDPIN_LUTINDEX_4 4 ++#define EXT_HPDPIN_LUTINDEX_5 5 ++#define EXT_HPDPIN_LUTINDEX_6 6 ++#define EXT_HPDPIN_LUTINDEX_7 7 ++#define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1) ++ ++#define EXT_AUXDDC_LUTINDEX_0 0 ++#define EXT_AUXDDC_LUTINDEX_1 1 ++#define EXT_AUXDDC_LUTINDEX_2 2 ++#define EXT_AUXDDC_LUTINDEX_3 3 ++#define EXT_AUXDDC_LUTINDEX_4 4 ++#define EXT_AUXDDC_LUTINDEX_5 5 ++#define EXT_AUXDDC_LUTINDEX_6 6 ++#define EXT_AUXDDC_LUTINDEX_7 7 ++#define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) ++ ++typedef struct _EXT_DISPLAY_PATH ++{ ++ USHORT usDeviceTag; //A bit vector to show what devices are supported ++ USHORT usDeviceACPIEnum; //16bit device ACPI id. ++ USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions ++ UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT ++ UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT ++ USHORT usExtEncoderObjId; //external encoder object id ++ USHORT usReserved[3]; ++}EXT_DISPLAY_PATH; ++ ++#define NUMBER_OF_UCHAR_FOR_GUID 16 ++#define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7 ++ ++typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string ++ EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. ++ UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. ++ UCHAR Reserved [7]; // for potential expansion ++}ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; ++ ++//Related definitions, all records are differnt but they have a commond header ++typedef struct _ATOM_COMMON_RECORD_HEADER ++{ ++ UCHAR ucRecordType; //An emun to indicate the record type ++ UCHAR ucRecordSize; //The size of the whole record in byte ++}ATOM_COMMON_RECORD_HEADER; ++ ++ ++#define ATOM_I2C_RECORD_TYPE 1 + #define ATOM_HPD_INT_RECORD_TYPE 2 + #define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 + #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 +-#define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 /* Obsolete, switch to use GPIO_CNTL_RECORD_TYPE */ +-#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 /* Obsolete, switch to use GPIO_CNTL_RECORD_TYPE */ ++#define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE ++#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE + #define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7 +-#define ATOM_JTAG_RECORD_TYPE 8 /* Obsolete, switch to use GPIO_CNTL_RECORD_TYPE */ ++#define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE + #define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9 + #define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10 + #define ATOM_CONNECTOR_CF_RECORD_TYPE 11 + #define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12 + #define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13 +-#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 +-#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 +- +-/* Must be updated when new record type is added,equal to that record definition! */ +-#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_CF_RECORD_TYPE +- +-typedef struct _ATOM_I2C_RECORD { +- ATOM_COMMON_RECORD_HEADER sheader; +- ATOM_I2C_ID_CONFIG sucI2cId; +- UCHAR ucI2CAddr; /* The slave address, it's 0 when the record is attached to connector for DDC */ +-} ATOM_I2C_RECORD; +- +-typedef struct _ATOM_HPD_INT_RECORD { +- ATOM_COMMON_RECORD_HEADER sheader; +- UCHAR ucHPDIntGPIOID; /* Corresponding block in GPIO_PIN_INFO table gives the pin info */ +- UCHAR ucPlugged_PinState; +-} ATOM_HPD_INT_RECORD; +- +-typedef struct _ATOM_OUTPUT_PROTECTION_RECORD { +- ATOM_COMMON_RECORD_HEADER sheader; +- UCHAR ucProtectionFlag; +- UCHAR ucReserved; +-} ATOM_OUTPUT_PROTECTION_RECORD; +- +-typedef struct _ATOM_CONNECTOR_DEVICE_TAG { +- ULONG ulACPIDeviceEnum; /* Reserved for now */ +- USHORT usDeviceID; /* This Id is same as "ATOM_DEVICE_XXX_SUPPORT" */ +- USHORT usPadding; +-} ATOM_CONNECTOR_DEVICE_TAG; +- +-typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD { +- ATOM_COMMON_RECORD_HEADER sheader; +- UCHAR ucNumberOfDevice; +- UCHAR ucReserved; +- ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; /* This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation */ +-} ATOM_CONNECTOR_DEVICE_TAG_RECORD; +- +-typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD { +- ATOM_COMMON_RECORD_HEADER sheader; +- UCHAR ucConfigGPIOID; +- UCHAR ucConfigGPIOState; /* Set to 1 when it's active high to enable external flow in */ +- UCHAR ucFlowinGPIPID; +- UCHAR ucExtInGPIPID; +-} ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; +- +-typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD { +- ATOM_COMMON_RECORD_HEADER sheader; +- UCHAR ucCTL1GPIO_ID; +- UCHAR ucCTL1GPIOState; /* Set to 1 when it's active high */ +- UCHAR ucCTL2GPIO_ID; +- UCHAR ucCTL2GPIOState; /* Set to 1 when it's active high */ +- UCHAR ucCTL3GPIO_ID; +- UCHAR ucCTL3GPIOState; /* Set to 1 when it's active high */ +- UCHAR ucCTLFPGA_IN_ID; +- UCHAR ucPadding[3]; +-} ATOM_ENCODER_FPGA_CONTROL_RECORD; +- +-typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD { +- ATOM_COMMON_RECORD_HEADER sheader; +- UCHAR ucGPIOID; /* Corresponding block in GPIO_PIN_INFO table gives the pin info */ +- UCHAR ucTVActiveState; /* Indicating when the pin==0 or 1 when TV is connected */ +-} ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; +- +-typedef struct _ATOM_JTAG_RECORD { +- ATOM_COMMON_RECORD_HEADER sheader; +- UCHAR ucTMSGPIO_ID; +- UCHAR ucTMSGPIOState; /* Set to 1 when it's active high */ +- UCHAR ucTCKGPIO_ID; +- UCHAR ucTCKGPIOState; /* Set to 1 when it's active high */ +- UCHAR ucTDOGPIO_ID; +- UCHAR ucTDOGPIOState; /* Set to 1 when it's active high */ +- UCHAR ucTDIGPIO_ID; +- UCHAR ucTDIGPIOState; /* Set to 1 when it's active high */ +- UCHAR ucPadding[2]; +-} ATOM_JTAG_RECORD; +- +-/* The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually */ +-typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR { +- UCHAR ucGPIOID; /* GPIO_ID, find the corresponding ID in GPIO_LUT table */ +- UCHAR ucGPIO_PinState; /* Pin state showing how to set-up the pin */ +-} ATOM_GPIO_PIN_CONTROL_PAIR; +- +-typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD { +- ATOM_COMMON_RECORD_HEADER sheader; +- UCHAR ucFlags; /* Future expnadibility */ +- UCHAR ucNumberOfPins; /* Number of GPIO pins used to control the object */ +- ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; /* the real gpio pin pair determined by number of pins ucNumberOfPins */ +-} ATOM_OBJECT_GPIO_CNTL_RECORD; +- +-/* Definitions for GPIO pin state */ ++#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 ++#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 ++#define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table ++#define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table ++#define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record ++#define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 ++ ++ ++//Must be updated when new record type is added,equal to that record definition! ++#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE ++ ++typedef struct _ATOM_I2C_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ ATOM_I2C_ID_CONFIG sucI2cId; ++ UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC ++}ATOM_I2C_RECORD; ++ ++typedef struct _ATOM_HPD_INT_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info ++ UCHAR ucPlugged_PinState; ++}ATOM_HPD_INT_RECORD; ++ ++ ++typedef struct _ATOM_OUTPUT_PROTECTION_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ UCHAR ucProtectionFlag; ++ UCHAR ucReserved; ++}ATOM_OUTPUT_PROTECTION_RECORD; ++ ++typedef struct _ATOM_CONNECTOR_DEVICE_TAG ++{ ++ ULONG ulACPIDeviceEnum; //Reserved for now ++ USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT" ++ USHORT usPadding; ++}ATOM_CONNECTOR_DEVICE_TAG; ++ ++typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ UCHAR ucNumberOfDevice; ++ UCHAR ucReserved; ++ ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation ++}ATOM_CONNECTOR_DEVICE_TAG_RECORD; ++ ++ ++typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ UCHAR ucConfigGPIOID; ++ UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in ++ UCHAR ucFlowinGPIPID; ++ UCHAR ucExtInGPIPID; ++}ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; ++ ++typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ UCHAR ucCTL1GPIO_ID; ++ UCHAR ucCTL1GPIOState; //Set to 1 when it's active high ++ UCHAR ucCTL2GPIO_ID; ++ UCHAR ucCTL2GPIOState; //Set to 1 when it's active high ++ UCHAR ucCTL3GPIO_ID; ++ UCHAR ucCTL3GPIOState; //Set to 1 when it's active high ++ UCHAR ucCTLFPGA_IN_ID; ++ UCHAR ucPadding[3]; ++}ATOM_ENCODER_FPGA_CONTROL_RECORD; ++ ++typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info ++ UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected ++}ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; ++ ++typedef struct _ATOM_JTAG_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ UCHAR ucTMSGPIO_ID; ++ UCHAR ucTMSGPIOState; //Set to 1 when it's active high ++ UCHAR ucTCKGPIO_ID; ++ UCHAR ucTCKGPIOState; //Set to 1 when it's active high ++ UCHAR ucTDOGPIO_ID; ++ UCHAR ucTDOGPIOState; //Set to 1 when it's active high ++ UCHAR ucTDIGPIO_ID; ++ UCHAR ucTDIGPIOState; //Set to 1 when it's active high ++ UCHAR ucPadding[2]; ++}ATOM_JTAG_RECORD; ++ ++ ++//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually ++typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR ++{ ++ UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table ++ UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin ++}ATOM_GPIO_PIN_CONTROL_PAIR; ++ ++typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ UCHAR ucFlags; // Future expnadibility ++ UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object ++ ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins ++}ATOM_OBJECT_GPIO_CNTL_RECORD; ++ ++//Definitions for GPIO pin state + #define GPIO_PIN_TYPE_INPUT 0x00 + #define GPIO_PIN_TYPE_OUTPUT 0x10 + #define GPIO_PIN_TYPE_HW_CONTROL 0x20 + +-/* For GPIO_PIN_TYPE_OUTPUT the following is defined */ ++//For GPIO_PIN_TYPE_OUTPUT the following is defined + #define GPIO_PIN_OUTPUT_STATE_MASK 0x01 + #define GPIO_PIN_OUTPUT_STATE_SHIFT 0 + #define GPIO_PIN_STATE_ACTIVE_LOW 0x0 + #define GPIO_PIN_STATE_ACTIVE_HIGH 0x1 + +-typedef struct _ATOM_ENCODER_DVO_CF_RECORD { +- ATOM_COMMON_RECORD_HEADER sheader; +- ULONG ulStrengthControl; /* DVOA strength control for CF */ +- UCHAR ucPadding[2]; +-} ATOM_ENCODER_DVO_CF_RECORD; ++// Indexes to GPIO array in GLSync record ++#define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0 ++#define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1 ++#define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2 ++#define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3 ++#define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4 ++#define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5 ++#define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6 ++#define ATOM_GPIO_INDEX_GLSYNC_MAX 7 ++ ++typedef struct _ATOM_ENCODER_DVO_CF_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ ULONG ulStrengthControl; // DVOA strength control for CF ++ UCHAR ucPadding[2]; ++}ATOM_ENCODER_DVO_CF_RECORD; + +-/* value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle */ ++// value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle + #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 + #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 + +-typedef struct _ATOM_CONNECTOR_CF_RECORD { +- ATOM_COMMON_RECORD_HEADER sheader; +- USHORT usMaxPixClk; +- UCHAR ucFlowCntlGpioId; +- UCHAR ucSwapCntlGpioId; +- UCHAR ucConnectedDvoBundle; +- UCHAR ucPadding; +-} ATOM_CONNECTOR_CF_RECORD; +- +-typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD { +- ATOM_COMMON_RECORD_HEADER sheader; +- ATOM_DTD_FORMAT asTiming; +-} ATOM_CONNECTOR_HARDCODE_DTD_RECORD; +- +-typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD { +- ATOM_COMMON_RECORD_HEADER sheader; /* ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE */ +- UCHAR ucSubConnectorType; /* CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A */ +- UCHAR ucReserved; +-} ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; +- +-typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD { +- ATOM_COMMON_RECORD_HEADER sheader; +- UCHAR ucMuxType; /* decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state */ +- UCHAR ucMuxControlPin; +- UCHAR ucMuxState[2]; /* for alligment purpose */ +-} ATOM_ROUTER_DDC_PATH_SELECT_RECORD; +- +-typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD { +- ATOM_COMMON_RECORD_HEADER sheader; +- UCHAR ucMuxType; +- UCHAR ucMuxControlPin; +- UCHAR ucMuxState[2]; /* for alligment purpose */ +-} ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; +- +-/* define ucMuxType */ ++typedef struct _ATOM_CONNECTOR_CF_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ USHORT usMaxPixClk; ++ UCHAR ucFlowCntlGpioId; ++ UCHAR ucSwapCntlGpioId; ++ UCHAR ucConnectedDvoBundle; ++ UCHAR ucPadding; ++}ATOM_CONNECTOR_CF_RECORD; ++ ++typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ ATOM_DTD_FORMAT asTiming; ++}ATOM_CONNECTOR_HARDCODE_DTD_RECORD; ++ ++typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE ++ UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A ++ UCHAR ucReserved; ++}ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; ++ ++ ++typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state ++ UCHAR ucMuxControlPin; ++ UCHAR ucMuxState[2]; //for alligment purpose ++}ATOM_ROUTER_DDC_PATH_SELECT_RECORD; ++ ++typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ UCHAR ucMuxType; ++ UCHAR ucMuxControlPin; ++ UCHAR ucMuxState[2]; //for alligment purpose ++}ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; ++ ++// define ucMuxType + #define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f + #define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01 + +-/****************************************************************************/ +-/* ASIC voltage data table */ +-/****************************************************************************/ +-typedef struct _ATOM_VOLTAGE_INFO_HEADER { +- USHORT usVDDCBaseLevel; /* In number of 50mv unit */ +- USHORT usReserved; /* For possible extension table offset */ +- UCHAR ucNumOfVoltageEntries; +- UCHAR ucBytesPerVoltageEntry; +- UCHAR ucVoltageStep; /* Indicating in how many mv increament is one step, 0.5mv unit */ +- UCHAR ucDefaultVoltageEntry; +- UCHAR ucVoltageControlI2cLine; +- UCHAR ucVoltageControlAddress; +- UCHAR ucVoltageControlOffset; +-} ATOM_VOLTAGE_INFO_HEADER; +- +-typedef struct _ATOM_VOLTAGE_INFO { +- ATOM_COMMON_TABLE_HEADER sHeader; +- ATOM_VOLTAGE_INFO_HEADER viHeader; +- UCHAR ucVoltageEntries[64]; /* 64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry */ +-} ATOM_VOLTAGE_INFO; +- +-typedef struct _ATOM_VOLTAGE_FORMULA { +- USHORT usVoltageBaseLevel; /* In number of 1mv unit */ +- USHORT usVoltageStep; /* Indicating in how many mv increament is one step, 1mv unit */ +- UCHAR ucNumOfVoltageEntries; /* Number of Voltage Entry, which indicate max Voltage */ +- UCHAR ucFlag; /* bit0=0 :step is 1mv =1 0.5mv */ +- UCHAR ucBaseVID; /* if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep */ +- UCHAR ucReserved; +- UCHAR ucVIDAdjustEntries[32]; /* 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries */ +-} ATOM_VOLTAGE_FORMULA; +- +-typedef struct _ATOM_VOLTAGE_CONTROL { +- UCHAR ucVoltageControlId; /* Indicate it is controlled by I2C or GPIO or HW state machine */ +- UCHAR ucVoltageControlI2cLine; +- UCHAR ucVoltageControlAddress; +- UCHAR ucVoltageControlOffset; +- USHORT usGpioPin_AIndex; /* GPIO_PAD register index */ +- UCHAR ucGpioPinBitShift[9]; /* at most 8 pin support 255 VIDs, termintate with 0xff */ +- UCHAR ucReserved; +-} ATOM_VOLTAGE_CONTROL; +- +-/* Define ucVoltageControlId */ ++typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table ++}ATOM_CONNECTOR_HPDPIN_LUT_RECORD; ++ ++typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID ++}ATOM_CONNECTOR_AUXDDC_LUT_RECORD; ++ ++typedef struct _ATOM_OBJECT_LINK_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ USHORT usObjectID; //could be connector, encorder or other object in object.h ++}ATOM_OBJECT_LINK_RECORD; ++ ++typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD ++{ ++ ATOM_COMMON_RECORD_HEADER sheader; ++ USHORT usReserved; ++}ATOM_CONNECTOR_REMOTE_CAP_RECORD; ++ ++/****************************************************************************/ ++// ASIC voltage data table ++/****************************************************************************/ ++typedef struct _ATOM_VOLTAGE_INFO_HEADER ++{ ++ USHORT usVDDCBaseLevel; //In number of 50mv unit ++ USHORT usReserved; //For possible extension table offset ++ UCHAR ucNumOfVoltageEntries; ++ UCHAR ucBytesPerVoltageEntry; ++ UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit ++ UCHAR ucDefaultVoltageEntry; ++ UCHAR ucVoltageControlI2cLine; ++ UCHAR ucVoltageControlAddress; ++ UCHAR ucVoltageControlOffset; ++}ATOM_VOLTAGE_INFO_HEADER; ++ ++typedef struct _ATOM_VOLTAGE_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_VOLTAGE_INFO_HEADER viHeader; ++ UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry ++}ATOM_VOLTAGE_INFO; ++ ++ ++typedef struct _ATOM_VOLTAGE_FORMULA ++{ ++ USHORT usVoltageBaseLevel; // In number of 1mv unit ++ USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit ++ UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage ++ UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv ++ UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep ++ UCHAR ucReserved; ++ UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries ++}ATOM_VOLTAGE_FORMULA; ++ ++typedef struct _VOLTAGE_LUT_ENTRY ++{ ++ USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code ++ USHORT usVoltageValue; // The corresponding Voltage Value, in mV ++}VOLTAGE_LUT_ENTRY; ++ ++typedef struct _ATOM_VOLTAGE_FORMULA_V2 ++{ ++ UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage ++ UCHAR ucReserved[3]; ++ VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries ++}ATOM_VOLTAGE_FORMULA_V2; ++ ++typedef struct _ATOM_VOLTAGE_CONTROL ++{ ++ UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine ++ UCHAR ucVoltageControlI2cLine; ++ UCHAR ucVoltageControlAddress; ++ UCHAR ucVoltageControlOffset; ++ USHORT usGpioPin_AIndex; //GPIO_PAD register index ++ UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff ++ UCHAR ucReserved; ++}ATOM_VOLTAGE_CONTROL; ++ ++// Define ucVoltageControlId + #define VOLTAGE_CONTROLLED_BY_HW 0x00 + #define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F + #define VOLTAGE_CONTROLLED_BY_GPIO 0x80 +-#define VOLTAGE_CONTROL_ID_LM64 0x01 /* I2C control, used for R5xx Core Voltage */ +-#define VOLTAGE_CONTROL_ID_DAC 0x02 /* I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI */ +-#define VOLTAGE_CONTROL_ID_VT116xM 0x03 /* I2C control, used for R6xx Core Voltage */ +-#define VOLTAGE_CONTROL_ID_DS4402 0x04 +- +-typedef struct _ATOM_VOLTAGE_OBJECT { +- UCHAR ucVoltageType; /* Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI */ +- UCHAR ucSize; /* Size of Object */ +- ATOM_VOLTAGE_CONTROL asControl; /* describ how to control */ +- ATOM_VOLTAGE_FORMULA asFormula; /* Indicate How to convert real Voltage to VID */ +-} ATOM_VOLTAGE_OBJECT; +- +-typedef struct _ATOM_VOLTAGE_OBJECT_INFO { +- ATOM_COMMON_TABLE_HEADER sHeader; +- ATOM_VOLTAGE_OBJECT asVoltageObj[3]; /* Info for Voltage control */ +-} ATOM_VOLTAGE_OBJECT_INFO; +- +-typedef struct _ATOM_LEAKID_VOLTAGE { +- UCHAR ucLeakageId; +- UCHAR ucReserved; +- USHORT usVoltage; +-} ATOM_LEAKID_VOLTAGE; +- +-typedef struct _ATOM_ASIC_PROFILE_VOLTAGE { +- UCHAR ucProfileId; +- UCHAR ucReserved; +- USHORT usSize; +- USHORT usEfuseSpareStartAddr; +- USHORT usFuseIndex[8]; /* from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, */ +- ATOM_LEAKID_VOLTAGE asLeakVol[2]; /* Leakid and relatd voltage */ +-} ATOM_ASIC_PROFILE_VOLTAGE; +- +-/* ucProfileId */ +-#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 ++#define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage ++#define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI ++#define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage ++#define VOLTAGE_CONTROL_ID_DS4402 0x04 ++ ++typedef struct _ATOM_VOLTAGE_OBJECT ++{ ++ UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI ++ UCHAR ucSize; //Size of Object ++ ATOM_VOLTAGE_CONTROL asControl; //describ how to control ++ ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID ++}ATOM_VOLTAGE_OBJECT; ++ ++typedef struct _ATOM_VOLTAGE_OBJECT_V2 ++{ ++ UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI ++ UCHAR ucSize; //Size of Object ++ ATOM_VOLTAGE_CONTROL asControl; //describ how to control ++ ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID ++}ATOM_VOLTAGE_OBJECT_V2; ++ ++typedef struct _ATOM_VOLTAGE_OBJECT_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control ++}ATOM_VOLTAGE_OBJECT_INFO; ++ ++typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control ++}ATOM_VOLTAGE_OBJECT_INFO_V2; ++ ++typedef struct _ATOM_LEAKID_VOLTAGE ++{ ++ UCHAR ucLeakageId; ++ UCHAR ucReserved; ++ USHORT usVoltage; ++}ATOM_LEAKID_VOLTAGE; ++ ++typedef struct _ATOM_ASIC_PROFILE_VOLTAGE ++{ ++ UCHAR ucProfileId; ++ UCHAR ucReserved; ++ USHORT usSize; ++ USHORT usEfuseSpareStartAddr; ++ USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, ++ ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage ++}ATOM_ASIC_PROFILE_VOLTAGE; ++ ++//ucProfileId ++#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 + #define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1 + #define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2 + +-typedef struct _ATOM_ASIC_PROFILING_INFO { +- ATOM_COMMON_TABLE_HEADER asHeader; +- ATOM_ASIC_PROFILE_VOLTAGE asVoltage; +-} ATOM_ASIC_PROFILING_INFO; +- +-typedef struct _ATOM_POWER_SOURCE_OBJECT { +- UCHAR ucPwrSrcId; /* Power source */ +- UCHAR ucPwrSensorType; /* GPIO, I2C or none */ +- UCHAR ucPwrSensId; /* if GPIO detect, it is GPIO id, if I2C detect, it is I2C id */ +- UCHAR ucPwrSensSlaveAddr; /* Slave address if I2C detect */ +- UCHAR ucPwrSensRegIndex; /* I2C register Index if I2C detect */ +- UCHAR ucPwrSensRegBitMask; /* detect which bit is used if I2C detect */ +- UCHAR ucPwrSensActiveState; /* high active or low active */ +- UCHAR ucReserve[3]; /* reserve */ +- USHORT usSensPwr; /* in unit of watt */ +-} ATOM_POWER_SOURCE_OBJECT; +- +-typedef struct _ATOM_POWER_SOURCE_INFO { +- ATOM_COMMON_TABLE_HEADER asHeader; +- UCHAR asPwrbehave[16]; +- ATOM_POWER_SOURCE_OBJECT asPwrObj[1]; +-} ATOM_POWER_SOURCE_INFO; +- +-/* Define ucPwrSrcId */ ++typedef struct _ATOM_ASIC_PROFILING_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER asHeader; ++ ATOM_ASIC_PROFILE_VOLTAGE asVoltage; ++}ATOM_ASIC_PROFILING_INFO; ++ ++typedef struct _ATOM_POWER_SOURCE_OBJECT ++{ ++ UCHAR ucPwrSrcId; // Power source ++ UCHAR ucPwrSensorType; // GPIO, I2C or none ++ UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id ++ UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect ++ UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect ++ UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect ++ UCHAR ucPwrSensActiveState; // high active or low active ++ UCHAR ucReserve[3]; // reserve ++ USHORT usSensPwr; // in unit of watt ++}ATOM_POWER_SOURCE_OBJECT; ++ ++typedef struct _ATOM_POWER_SOURCE_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER asHeader; ++ UCHAR asPwrbehave[16]; ++ ATOM_POWER_SOURCE_OBJECT asPwrObj[1]; ++}ATOM_POWER_SOURCE_INFO; ++ ++ ++//Define ucPwrSrcId + #define POWERSOURCE_PCIE_ID1 0x00 + #define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01 + #define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02 + #define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04 + #define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08 + +-/* define ucPwrSensorId */ ++//define ucPwrSensorId + #define POWER_SENSOR_ALWAYS 0x00 + #define POWER_SENSOR_GPIO 0x01 + #define POWER_SENSOR_I2C 0x02 + ++typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ULONG ulBootUpEngineClock; ++ ULONG ulDentistVCOFreq; ++ ULONG ulBootUpUMAClock; ++ ULONG ulReserved1[8]; ++ ULONG ulBootUpReqDisplayVector; ++ ULONG ulOtherDisplayMisc; ++ ULONG ulGPUCapInfo; ++ ULONG ulReserved2[3]; ++ ULONG ulSystemConfig; ++ ULONG ulCPUCapInfo; ++ USHORT usMaxNBVoltage; ++ USHORT usMinNBVoltage; ++ USHORT usBootUpNBVoltage; ++ USHORT usExtDispConnInfoOffset; ++ UCHAR ucHtcTmpLmt; ++ UCHAR ucTjOffset; ++ UCHAR ucMemoryType; ++ UCHAR ucUMAChannelNumber; ++ ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; ++ ULONG ulCSR_M3_ARB_CNTL_UVD[10]; ++ ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; ++ ULONG ulReserved3[42]; ++ ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; ++}ATOM_INTEGRATED_SYSTEM_INFO_V6; ++ ++/********************************************************************************************************************** ++// ATOM_INTEGRATED_SYSTEM_INFO_V6 Description ++//ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. ++//ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. ++//ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. ++//ulReserved1[8] Reserved by now, must be 0x0. ++//ulBootUpReqDisplayVector VBIOS boot up display IDs ++// ATOM_DEVICE_CRT1_SUPPORT 0x0001 ++// ATOM_DEVICE_CRT2_SUPPORT 0x0010 ++// ATOM_DEVICE_DFP1_SUPPORT 0x0008 ++// ATOM_DEVICE_DFP6_SUPPORT 0x0040 ++// ATOM_DEVICE_DFP2_SUPPORT 0x0080 ++// ATOM_DEVICE_DFP3_SUPPORT 0x0200 ++// ATOM_DEVICE_DFP4_SUPPORT 0x0400 ++// ATOM_DEVICE_DFP5_SUPPORT 0x0800 ++// ATOM_DEVICE_LCD1_SUPPORT 0x0002 ++//ulOtherDisplayMisc Other display related flags, not defined yet. ++//ulGPUCapInfo TBD ++//ulReserved2[3] must be 0x0 for the reserved. ++//ulSystemConfig TBD ++//ulCPUCapInfo TBD ++//usMaxNBVoltage High NB voltage in unit of mv, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse. ++//usMinNBVoltage Low NB voltage in unit of mv, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse. ++//usBootUpNBVoltage Boot up NB voltage in unit of mv. ++//ucHtcTmpLmt Bit [22:16] of D24F3x64 Thermal Control (HTC) Register. ++//ucTjOffset Bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed. ++//ucMemoryType [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. ++//ucUMAChannelNumber System memory channel numbers. ++//usExtDispConnectionInfoOffset ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO offset relative to beginning of this table. ++//ulCSR_M3_ARB_CNTL_DEFAULT[10] Arrays with values for CSR M3 arbiter for default ++//ulCSR_M3_ARB_CNTL_UVD[10] Arrays with values for CSR M3 arbiter for UVD playback. ++//ulCSR_M3_ARB_CNTL_FS3D[10] Arrays with values for CSR M3 arbiter for Full Screen 3D applications. ++**********************************************************************************************************************/ ++ + /**************************************************************************/ +-/* This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design */ +-/* Memory SS Info Table */ +-/* Define Memory Clock SS chip ID */ ++// This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design ++//Memory SS Info Table ++//Define Memory Clock SS chip ID + #define ICS91719 1 + #define ICS91720 2 + +-/* Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol */ +-typedef struct _ATOM_I2C_DATA_RECORD { +- UCHAR ucNunberOfBytes; /* Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" */ +- UCHAR ucI2CData[1]; /* I2C data in bytes, should be less than 16 bytes usually */ +-} ATOM_I2C_DATA_RECORD; +- +-/* Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information */ +-typedef struct _ATOM_I2C_DEVICE_SETUP_INFO { +- ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; /* I2C line and HW/SW assisted cap. */ +- UCHAR ucSSChipID; /* SS chip being used */ +- UCHAR ucSSChipSlaveAddr; /* Slave Address to set up this SS chip */ +- UCHAR ucNumOfI2CDataRecords; /* number of data block */ +- ATOM_I2C_DATA_RECORD asI2CData[1]; +-} ATOM_I2C_DEVICE_SETUP_INFO; +- +-/* ========================================================================================== */ +-typedef struct _ATOM_ASIC_MVDD_INFO { +- ATOM_COMMON_TABLE_HEADER sHeader; +- ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1]; +-} ATOM_ASIC_MVDD_INFO; +- +-/* ========================================================================================== */ ++//Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol ++typedef struct _ATOM_I2C_DATA_RECORD ++{ ++ UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" ++ UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually ++}ATOM_I2C_DATA_RECORD; ++ ++ ++//Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information ++typedef struct _ATOM_I2C_DEVICE_SETUP_INFO ++{ ++ ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap. ++ UCHAR ucSSChipID; //SS chip being used ++ UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip ++ UCHAR ucNumOfI2CDataRecords; //number of data block ++ ATOM_I2C_DATA_RECORD asI2CData[1]; ++}ATOM_I2C_DEVICE_SETUP_INFO; ++ ++//========================================================================================== ++typedef struct _ATOM_ASIC_MVDD_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1]; ++}ATOM_ASIC_MVDD_INFO; ++ ++//========================================================================================== + #define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO + +-/* ========================================================================================== */ ++//========================================================================================== + /**************************************************************************/ + +-typedef struct _ATOM_ASIC_SS_ASSIGNMENT { +- ULONG ulTargetClockRange; /* Clock Out frequence (VCO ), in unit of 10Khz */ +- USHORT usSpreadSpectrumPercentage; /* in unit of 0.01% */ +- USHORT usSpreadRateInKhz; /* in unit of kHz, modulation freq */ +- UCHAR ucClockIndication; /* Indicate which clock source needs SS */ +- UCHAR ucSpreadSpectrumMode; /* Bit1=0 Down Spread,=1 Center Spread. */ +- UCHAR ucReserved[2]; +-} ATOM_ASIC_SS_ASSIGNMENT; +- +-/* Define ucSpreadSpectrumType */ ++typedef struct _ATOM_ASIC_SS_ASSIGNMENT ++{ ++ ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz ++ USHORT usSpreadSpectrumPercentage; //in unit of 0.01% ++ USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq ++ UCHAR ucClockIndication; //Indicate which clock source needs SS ++ UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread. ++ UCHAR ucReserved[2]; ++}ATOM_ASIC_SS_ASSIGNMENT; ++ ++//Define ucClockIndication, SW uses the IDs below to search if the SS is requried/enabled on a clock branch/signal type. ++//SS is not required or enabled if a match is not found. + #define ASIC_INTERNAL_MEMORY_SS 1 + #define ASIC_INTERNAL_ENGINE_SS 2 +-#define ASIC_INTERNAL_UVD_SS 3 ++#define ASIC_INTERNAL_UVD_SS 3 ++#define ASIC_INTERNAL_SS_ON_TMDS 4 ++#define ASIC_INTERNAL_SS_ON_HDMI 5 ++#define ASIC_INTERNAL_SS_ON_LVDS 6 ++#define ASIC_INTERNAL_SS_ON_DP 7 ++#define ASIC_INTERNAL_SS_ON_DCPLL 8 ++ ++typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 ++{ ++ ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz ++ //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) ++ USHORT usSpreadSpectrumPercentage; //in unit of 0.01% ++ USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq ++ UCHAR ucClockIndication; //Indicate which clock source needs SS ++ UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS ++ UCHAR ucReserved[2]; ++}ATOM_ASIC_SS_ASSIGNMENT_V2; ++ ++//ucSpreadSpectrumMode ++//#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 ++//#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 ++//#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 ++//#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 ++//#define ATOM_INTERNAL_SS_MASK 0x00000000 ++//#define ATOM_EXTERNAL_SS_MASK 0x00000002 ++ ++typedef struct _ATOM_ASIC_INTERNAL_SS_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; ++}ATOM_ASIC_INTERNAL_SS_INFO; + +-typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { +- ATOM_COMMON_TABLE_HEADER sHeader; +- ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; +-} ATOM_ASIC_INTERNAL_SS_INFO; ++typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only. ++}ATOM_ASIC_INTERNAL_SS_INFO_V2; + +-/* ==============================Scratch Pad Definition Portion=============================== */ ++typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3 ++{ ++ ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz ++ //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) ++ USHORT usSpreadSpectrumPercentage; //in unit of 0.01% ++ USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq ++ UCHAR ucClockIndication; //Indicate which clock source needs SS ++ UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS ++ UCHAR ucReserved[2]; ++}ATOM_ASIC_SS_ASSIGNMENT_V3; ++ ++typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only. ++}ATOM_ASIC_INTERNAL_SS_INFO_V3; ++ ++ ++//==============================Scratch Pad Definition Portion=============================== + #define ATOM_DEVICE_CONNECT_INFO_DEF 0 + #define ATOM_ROM_LOCATION_DEF 1 + #define ATOM_TV_STANDARD_DEF 2 +@@ -2995,7 +3852,8 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { + #define ATOM_I2C_CHANNEL_STATUS_DEF 8 + #define ATOM_I2C_CHANNEL_STATUS1_DEF 9 + +-/* BIOS_0_SCRATCH Definition */ ++ ++// BIOS_0_SCRATCH Definition + #define ATOM_S0_CRT1_MONO 0x00000001L + #define ATOM_S0_CRT1_COLOR 0x00000002L + #define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR) +@@ -3008,6 +3866,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { + #define ATOM_S0_CV_DIN_A 0x00000020L + #define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A) + ++ + #define ATOM_S0_CRT2_MONO 0x00000100L + #define ATOM_S0_CRT2_COLOR 0x00000200L + #define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR) +@@ -3025,28 +3884,27 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { + #define ATOM_S0_DFP2 0x00020000L + #define ATOM_S0_LCD1 0x00040000L + #define ATOM_S0_LCD2 0x00080000L +-#define ATOM_S0_TV2 0x00100000L +-#define ATOM_S0_DFP3 0x00200000L +-#define ATOM_S0_DFP4 0x00400000L +-#define ATOM_S0_DFP5 0x00800000L ++#define ATOM_S0_DFP6 0x00100000L ++#define ATOM_S0_DFP3 0x00200000L ++#define ATOM_S0_DFP4 0x00400000L ++#define ATOM_S0_DFP5 0x00800000L + +-#define ATOM_S0_DFP_MASK \ +- (ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5) ++#define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6 + +-#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L /* If set, indicates we are running a PCIE asic with */ +- /* the FAD/HDP reg access bug. Bit is read by DAL */ ++#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with ++ // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx + + #define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L + #define ATOM_S0_THERMAL_STATE_SHIFT 26 + + #define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L +-#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 ++#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 + + #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 + #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 + #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 + +-/* Byte aligned definition for BIOS usage */ ++//Byte aligned defintion for BIOS usage + #define ATOM_S0_CRT1_MONOb0 0x01 + #define ATOM_S0_CRT1_COLORb0 0x02 + #define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) +@@ -3076,8 +3934,11 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { + #define ATOM_S0_DFP2b2 0x02 + #define ATOM_S0_LCD1b2 0x04 + #define ATOM_S0_LCD2b2 0x08 +-#define ATOM_S0_TV2b2 0x10 +-#define ATOM_S0_DFP3b2 0x20 ++#define ATOM_S0_DFP6b2 0x10 ++#define ATOM_S0_DFP3b2 0x20 ++#define ATOM_S0_DFP4b2 0x40 ++#define ATOM_S0_DFP5b2 0x80 ++ + + #define ATOM_S0_THERMAL_STATE_MASKb3 0x1C + #define ATOM_S0_THERMAL_STATE_SHIFTb3 2 +@@ -3085,43 +3946,20 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { + #define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0 + #define ATOM_S0_LCD1_SHIFT 18 + +-/* BIOS_1_SCRATCH Definition */ ++// BIOS_1_SCRATCH Definition + #define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL + #define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L + +-/* BIOS_2_SCRATCH Definition */ ++// BIOS_2_SCRATCH Definition + #define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL + #define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L + #define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8 + +-#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L +-#define ATOM_S2_LCD1_DPMS_STATE 0x00020000L +-#define ATOM_S2_TV1_DPMS_STATE 0x00040000L +-#define ATOM_S2_DFP1_DPMS_STATE 0x00080000L +-#define ATOM_S2_CRT2_DPMS_STATE 0x00100000L +-#define ATOM_S2_LCD2_DPMS_STATE 0x00200000L +-#define ATOM_S2_TV2_DPMS_STATE 0x00400000L +-#define ATOM_S2_DFP2_DPMS_STATE 0x00800000L +-#define ATOM_S2_CV_DPMS_STATE 0x01000000L +-#define ATOM_S2_DFP3_DPMS_STATE 0x02000000L +-#define ATOM_S2_DFP4_DPMS_STATE 0x04000000L +-#define ATOM_S2_DFP5_DPMS_STATE 0x08000000L +- +-#define ATOM_S2_DFP_DPM_STATE \ +- (ATOM_S2_DFP1_DPMS_STATE | ATOM_S2_DFP2_DPMS_STATE | \ +- ATOM_S2_DFP3_DPMS_STATE | ATOM_S2_DFP4_DPMS_STATE | \ +- ATOM_S2_DFP5_DPMS_STATE) +- +-#define ATOM_S2_DEVICE_DPMS_STATE \ +- (ATOM_S2_CRT1_DPMS_STATE + ATOM_S2_LCD1_DPMS_STATE + \ +- ATOM_S2_TV1_DPMS_STATE + ATOM_S2_DFP_DPMS_STATE + \ +- ATOM_S2_CRT2_DPMS_STATE + ATOM_S2_LCD2_DPMS_STATE + \ +- ATOM_S2_TV2_DPMS_STATE + ATOM_S2_CV_DPMS_STATE) +- + #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L + #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26 + #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L + ++#define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L + #define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L + + #define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0 +@@ -3131,21 +3969,11 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { + #define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 + #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L + +-/* Byte aligned definition for BIOS usage */ ++ ++//Byte aligned defintion for BIOS usage + #define ATOM_S2_TV1_STANDARD_MASKb0 0x0F + #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF +-#define ATOM_S2_CRT1_DPMS_STATEb2 0x01 +-#define ATOM_S2_LCD1_DPMS_STATEb2 0x02 +-#define ATOM_S2_TV1_DPMS_STATEb2 0x04 +-#define ATOM_S2_DFP1_DPMS_STATEb2 0x08 +-#define ATOM_S2_CRT2_DPMS_STATEb2 0x10 +-#define ATOM_S2_LCD2_DPMS_STATEb2 0x20 +-#define ATOM_S2_TV2_DPMS_STATEb2 0x40 +-#define ATOM_S2_DFP2_DPMS_STATEb2 0x80 +-#define ATOM_S2_CV_DPMS_STATEb3 0x01 +-#define ATOM_S2_DFP3_DPMS_STATEb3 0x02 +-#define ATOM_S2_DFP4_DPMS_STATEb3 0x04 +-#define ATOM_S2_DFP5_DPMS_STATEb3 0x08 ++#define ATOM_S2_DEVICE_DPMS_STATEb2 0x01 + + #define ATOM_S2_DEVICE_DPMS_MASKw1 0x3FF + #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3 0x0C +@@ -3153,21 +3981,22 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { + #define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20 + #define ATOM_S2_ROTATION_STATE_MASKb3 0xC0 + +-/* BIOS_3_SCRATCH Definition */ ++ ++// BIOS_3_SCRATCH Definition + #define ATOM_S3_CRT1_ACTIVE 0x00000001L + #define ATOM_S3_LCD1_ACTIVE 0x00000002L + #define ATOM_S3_TV1_ACTIVE 0x00000004L + #define ATOM_S3_DFP1_ACTIVE 0x00000008L + #define ATOM_S3_CRT2_ACTIVE 0x00000010L + #define ATOM_S3_LCD2_ACTIVE 0x00000020L +-#define ATOM_S3_TV2_ACTIVE 0x00000040L ++#define ATOM_S3_DFP6_ACTIVE 0x00000040L + #define ATOM_S3_DFP2_ACTIVE 0x00000080L + #define ATOM_S3_CV_ACTIVE 0x00000100L + #define ATOM_S3_DFP3_ACTIVE 0x00000200L + #define ATOM_S3_DFP4_ACTIVE 0x00000400L + #define ATOM_S3_DFP5_ACTIVE 0x00000800L + +-#define ATOM_S3_DEVICE_ACTIVE_MASK 0x000003FFL ++#define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL + + #define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L + #define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L +@@ -3178,7 +4007,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { + #define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L + #define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L + #define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L +-#define ATOM_S3_TV2_CRTC_ACTIVE 0x00400000L ++#define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L + #define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L + #define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L + #define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L +@@ -3187,17 +4016,18 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { + + #define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L + #define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L ++//Below two definitions are not supported in pplib, but in the old powerplay in DAL + #define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L + #define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L + +-/* Byte aligned definition for BIOS usage */ ++//Byte aligned defintion for BIOS usage + #define ATOM_S3_CRT1_ACTIVEb0 0x01 + #define ATOM_S3_LCD1_ACTIVEb0 0x02 + #define ATOM_S3_TV1_ACTIVEb0 0x04 + #define ATOM_S3_DFP1_ACTIVEb0 0x08 + #define ATOM_S3_CRT2_ACTIVEb0 0x10 + #define ATOM_S3_LCD2_ACTIVEb0 0x20 +-#define ATOM_S3_TV2_ACTIVEb0 0x40 ++#define ATOM_S3_DFP6_ACTIVEb0 0x40 + #define ATOM_S3_DFP2_ACTIVEb0 0x80 + #define ATOM_S3_CV_ACTIVEb1 0x01 + #define ATOM_S3_DFP3_ACTIVEb1 0x02 +@@ -3212,7 +4042,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { + #define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08 + #define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10 + #define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20 +-#define ATOM_S3_TV2_CRTC_ACTIVEb2 0x40 ++#define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40 + #define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80 + #define ATOM_S3_CV_CRTC_ACTIVEb3 0x01 + #define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02 +@@ -3221,35 +4051,31 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { + + #define ATOM_S3_ACTIVE_CRTC2w1 0xFFF + +-#define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20 +-#define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40 +-#define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80 +- +-/* BIOS_4_SCRATCH Definition */ ++// BIOS_4_SCRATCH Definition + #define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL + #define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L + #define ATOM_S4_LCD1_REFRESH_SHIFT 8 + +-/* Byte aligned definition for BIOS usage */ ++//Byte aligned defintion for BIOS usage + #define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF + #define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 + #define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 + +-/* BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! */ ++// BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! + #define ATOM_S5_DOS_REQ_CRT1b0 0x01 + #define ATOM_S5_DOS_REQ_LCD1b0 0x02 + #define ATOM_S5_DOS_REQ_TV1b0 0x04 + #define ATOM_S5_DOS_REQ_DFP1b0 0x08 + #define ATOM_S5_DOS_REQ_CRT2b0 0x10 + #define ATOM_S5_DOS_REQ_LCD2b0 0x20 +-#define ATOM_S5_DOS_REQ_TV2b0 0x40 ++#define ATOM_S5_DOS_REQ_DFP6b0 0x40 + #define ATOM_S5_DOS_REQ_DFP2b0 0x80 + #define ATOM_S5_DOS_REQ_CVb1 0x01 + #define ATOM_S5_DOS_REQ_DFP3b1 0x02 + #define ATOM_S5_DOS_REQ_DFP4b1 0x04 + #define ATOM_S5_DOS_REQ_DFP5b1 0x08 + +-#define ATOM_S5_DOS_REQ_DEVICEw0 0x03FF ++#define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF + + #define ATOM_S5_DOS_REQ_CRT1 0x0001 + #define ATOM_S5_DOS_REQ_LCD1 0x0002 +@@ -3257,22 +4083,21 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { + #define ATOM_S5_DOS_REQ_DFP1 0x0008 + #define ATOM_S5_DOS_REQ_CRT2 0x0010 + #define ATOM_S5_DOS_REQ_LCD2 0x0020 +-#define ATOM_S5_DOS_REQ_TV2 0x0040 ++#define ATOM_S5_DOS_REQ_DFP6 0x0040 + #define ATOM_S5_DOS_REQ_DFP2 0x0080 + #define ATOM_S5_DOS_REQ_CV 0x0100 +-#define ATOM_S5_DOS_REQ_DFP3 0x0200 +-#define ATOM_S5_DOS_REQ_DFP4 0x0400 +-#define ATOM_S5_DOS_REQ_DFP5 0x0800 ++#define ATOM_S5_DOS_REQ_DFP3 0x0200 ++#define ATOM_S5_DOS_REQ_DFP4 0x0400 ++#define ATOM_S5_DOS_REQ_DFP5 0x0800 + + #define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0 + #define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0 + #define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0 + #define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1 +-#define ATOM_S5_DOS_FORCE_DEVICEw1 \ +- (ATOM_S5_DOS_FORCE_CRT1b2 + ATOM_S5_DOS_FORCE_TV1b2 + \ +- ATOM_S5_DOS_FORCE_CRT2b2 + (ATOM_S5_DOS_FORCE_CVb3 << 8)) ++#define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\ ++ (ATOM_S5_DOS_FORCE_CVb3<<8)) + +-/* BIOS_6_SCRATCH Definition */ ++// BIOS_6_SCRATCH Definition + #define ATOM_S6_DEVICE_CHANGE 0x00000001L + #define ATOM_S6_SCALER_CHANGE 0x00000002L + #define ATOM_S6_LID_CHANGE 0x00000004L +@@ -3285,11 +4110,11 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { + #define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L + #define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L + #define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L +-#define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L /* Normal expansion Request bit for LCD */ +-#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L /* Aspect ratio expansion Request bit for LCD */ ++#define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD ++#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD + +-#define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L /* This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion */ +-#define ATOM_S6_I2C_STATE_CHANGE 0x00008000L /* This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion */ ++#define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion ++#define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion + + #define ATOM_S6_ACC_REQ_CRT1 0x00010000L + #define ATOM_S6_ACC_REQ_LCD1 0x00020000L +@@ -3297,7 +4122,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { + #define ATOM_S6_ACC_REQ_DFP1 0x00080000L + #define ATOM_S6_ACC_REQ_CRT2 0x00100000L + #define ATOM_S6_ACC_REQ_LCD2 0x00200000L +-#define ATOM_S6_ACC_REQ_TV2 0x00400000L ++#define ATOM_S6_ACC_REQ_DFP6 0x00400000L + #define ATOM_S6_ACC_REQ_DFP2 0x00800000L + #define ATOM_S6_ACC_REQ_CV 0x01000000L + #define ATOM_S6_ACC_REQ_DFP3 0x02000000L +@@ -3310,7 +4135,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { + #define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L + #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L + +-/* Byte aligned definition for BIOS usage */ ++//Byte aligned defintion for BIOS usage + #define ATOM_S6_DEVICE_CHANGEb0 0x01 + #define ATOM_S6_SCALER_CHANGEb0 0x02 + #define ATOM_S6_LID_CHANGEb0 0x04 +@@ -3320,11 +4145,11 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { + #define ATOM_S6_LID_STATEb0 0x40 + #define ATOM_S6_DOCK_STATEb0 0x80 + #define ATOM_S6_CRITICAL_STATEb1 0x01 +-#define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 ++#define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 + #define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04 + #define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08 +-#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 +-#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 ++#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 ++#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 + + #define ATOM_S6_ACC_REQ_CRT1b2 0x01 + #define ATOM_S6_ACC_REQ_LCD1b2 0x02 +@@ -3332,12 +4157,12 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { + #define ATOM_S6_ACC_REQ_DFP1b2 0x08 + #define ATOM_S6_ACC_REQ_CRT2b2 0x10 + #define ATOM_S6_ACC_REQ_LCD2b2 0x20 +-#define ATOM_S6_ACC_REQ_TV2b2 0x40 ++#define ATOM_S6_ACC_REQ_DFP6b2 0x40 + #define ATOM_S6_ACC_REQ_DFP2b2 0x80 + #define ATOM_S6_ACC_REQ_CVb3 0x01 +-#define ATOM_S6_ACC_REQ_DFP3b3 0x02 +-#define ATOM_S6_ACC_REQ_DFP4b3 0x04 +-#define ATOM_S6_ACC_REQ_DFP5b3 0x08 ++#define ATOM_S6_ACC_REQ_DFP3b3 0x02 ++#define ATOM_S6_ACC_REQ_DFP4b3 0x04 ++#define ATOM_S6_ACC_REQ_DFP5b3 0x08 + + #define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0 + #define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10 +@@ -3366,7 +4191,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { + #define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30 + #define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31 + +-/* BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! */ ++// BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! + #define ATOM_S7_DOS_MODE_TYPEb0 0x03 + #define ATOM_S7_DOS_MODE_VGAb0 0x00 + #define ATOM_S7_DOS_MODE_VESAb0 0x01 +@@ -3378,220 +4203,194 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { + + #define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 + +-/* BIOS_8_SCRATCH Definition */ ++// BIOS_8_SCRATCH Definition + #define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF +-#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 ++#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 + + #define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0 + #define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16 + +-/* BIOS_9_SCRATCH Definition */ +-#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK ++// BIOS_9_SCRATCH Definition ++#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK + #define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF + #endif +-#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK ++#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK + #define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000 + #endif +-#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT ++#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT + #define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0 + #endif +-#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT ++#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT + #define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16 + #endif + ++ + #define ATOM_FLAG_SET 0x20 + #define ATOM_FLAG_CLEAR 0 +-#define CLEAR_ATOM_S6_ACC_MODE \ +- ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ +- ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) +-#define SET_ATOM_S6_DEVICE_CHANGE \ +- ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ +- ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET) +-#define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE \ +- ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ +- ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET) +-#define SET_ATOM_S6_SCALER_CHANGE \ +- ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ +- ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET) +-#define SET_ATOM_S6_LID_CHANGE \ +- ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ +- ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET) +- +-#define SET_ATOM_S6_LID_STATE \ +- ((ATOM_ACC_CHANGE_INFO_DEF << 8) |\ +- ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET) +-#define CLEAR_ATOM_S6_LID_STATE \ +- ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ +- ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR) +- +-#define SET_ATOM_S6_DOCK_CHANGE \ +- ((ATOM_ACC_CHANGE_INFO_DEF << 8)| \ +- ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET) +-#define SET_ATOM_S6_DOCK_STATE \ +- ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ +- ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET) +-#define CLEAR_ATOM_S6_DOCK_STATE \ +- ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ +- ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR) +- +-#define SET_ATOM_S6_THERMAL_STATE_CHANGE \ +- ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ +- ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET) +-#define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE \ +- ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ +- ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET) +-#define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS \ +- ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ +- ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET) +- +-#define SET_ATOM_S6_CRITICAL_STATE \ +- ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ +- ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) +-#define CLEAR_ATOM_S6_CRITICAL_STATE \ +- ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ +- ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) +- +-#define SET_ATOM_S6_REQ_SCALER \ +- ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ +- ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) +-#define CLEAR_ATOM_S6_REQ_SCALER \ +- ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ +- ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) +- +-#define SET_ATOM_S6_REQ_SCALER_ARATIO \ +- ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ +- ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) +-#define CLEAR_ATOM_S6_REQ_SCALER_ARATIO \ +- ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ +- ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR ) +- +-#define SET_ATOM_S6_I2C_STATE_CHANGE \ +- ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ +- ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) +- +-#define SET_ATOM_S6_DISPLAY_STATE_CHANGE \ +- ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ +- ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) +- +-#define SET_ATOM_S6_DEVICE_RECONFIG \ +- ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ +- ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET) +-#define CLEAR_ATOM_S0_LCD1 \ +- ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 ) | \ +- ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR ) +-#define SET_ATOM_S7_DOS_8BIT_DAC_EN \ +- ((ATOM_DOS_MODE_INFO_DEF << 8) | \ +- ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) +-#define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN \ +- ((ATOM_DOS_MODE_INFO_DEF << 8) | \ +- ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) ++#define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) ++#define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET) ++#define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET) ++#define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET) ++#define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET) + +-/****************************************************************************/ +-/* Portion II: Definitinos only used in Driver */ ++#define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET) ++#define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR) ++ ++#define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET) ++#define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET) ++#define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR) ++ ++#define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET) ++#define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET) ++#define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET) ++ ++#define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) ++#define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) ++ ++#define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) ++#define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) ++ ++#define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) ++#define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR ) ++ ++#define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) ++ ++#define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) ++ ++#define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET) ++#define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR ) ++#define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) ++#define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) ++ ++/****************************************************************************/ ++//Portion II: Definitinos only used in Driver + /****************************************************************************/ + +-/* Macros used by driver */ ++// Macros used by driver ++#ifdef __cplusplus ++#define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast(&(static_cast(0))->FieldName)-static_cast(0))/sizeof(USHORT)) + +-#define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char *)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES *)0)->FieldName)-(char *)0)/sizeof(USHORT)) ++#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F) ++#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F) ++#else // not __cplusplus ++#define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT)) + + #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F) + #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F) ++#endif // __cplusplus + + #define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION + #define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION + +-/****************************************************************************/ +-/* Portion III: Definitinos only used in VBIOS */ ++/****************************************************************************/ ++//Portion III: Definitinos only used in VBIOS + /****************************************************************************/ + #define ATOM_DAC_SRC 0x80 + #define ATOM_SRC_DAC1 0 + #define ATOM_SRC_DAC2 0x80 + +-#ifdef UEFI_BUILD +-#define USHORT UTEMP +-#endif +- +-typedef struct _MEMORY_PLLINIT_PARAMETERS { +- ULONG ulTargetMemoryClock; /* In 10Khz unit */ +- UCHAR ucAction; /* not define yet */ +- UCHAR ucFbDiv_Hi; /* Fbdiv Hi byte */ +- UCHAR ucFbDiv; /* FB value */ +- UCHAR ucPostDiv; /* Post div */ +-} MEMORY_PLLINIT_PARAMETERS; ++typedef struct _MEMORY_PLLINIT_PARAMETERS ++{ ++ ULONG ulTargetMemoryClock; //In 10Khz unit ++ UCHAR ucAction; //not define yet ++ UCHAR ucFbDiv_Hi; //Fbdiv Hi byte ++ UCHAR ucFbDiv; //FB value ++ UCHAR ucPostDiv; //Post div ++}MEMORY_PLLINIT_PARAMETERS; + + #define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS + +-#define GPIO_PIN_WRITE 0x01 ++ ++#define GPIO_PIN_WRITE 0x01 + #define GPIO_PIN_READ 0x00 + +-typedef struct _GPIO_PIN_CONTROL_PARAMETERS { +- UCHAR ucGPIO_ID; /* return value, read from GPIO pins */ +- UCHAR ucGPIOBitShift; /* define which bit in uGPIOBitVal need to be update */ +- UCHAR ucGPIOBitVal; /* Set/Reset corresponding bit defined in ucGPIOBitMask */ +- UCHAR ucAction; /* =GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write */ +-} GPIO_PIN_CONTROL_PARAMETERS; +- +-typedef struct _ENABLE_SCALER_PARAMETERS { +- UCHAR ucScaler; /* ATOM_SCALER1, ATOM_SCALER2 */ +- UCHAR ucEnable; /* ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION */ +- UCHAR ucTVStandard; /* */ +- UCHAR ucPadding[1]; +-} ENABLE_SCALER_PARAMETERS; +-#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS +- +-/* ucEnable: */ ++typedef struct _GPIO_PIN_CONTROL_PARAMETERS ++{ ++ UCHAR ucGPIO_ID; //return value, read from GPIO pins ++ UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update ++ UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask ++ UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write ++}GPIO_PIN_CONTROL_PARAMETERS; ++ ++typedef struct _ENABLE_SCALER_PARAMETERS ++{ ++ UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2 ++ UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION ++ UCHAR ucTVStandard; // ++ UCHAR ucPadding[1]; ++}ENABLE_SCALER_PARAMETERS; ++#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS ++ ++//ucEnable: + #define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0 + #define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1 + #define SCALER_ENABLE_2TAP_ALPHA_MODE 2 + #define SCALER_ENABLE_MULTITAP_MODE 3 + +-typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS { +- ULONG usHWIconHorzVertPosn; /* Hardware Icon Vertical position */ +- UCHAR ucHWIconVertOffset; /* Hardware Icon Vertical offset */ +- UCHAR ucHWIconHorzOffset; /* Hardware Icon Horizontal offset */ +- UCHAR ucSelection; /* ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 */ +- UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ +-} ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; +- +-typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION { +- ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; +- ENABLE_CRTC_PARAMETERS sReserved; +-} ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; +- +-typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS { +- USHORT usHight; /* Image Hight */ +- USHORT usWidth; /* Image Width */ +- UCHAR ucSurface; /* Surface 1 or 2 */ +- UCHAR ucPadding[3]; +-} ENABLE_GRAPH_SURFACE_PARAMETERS; +- +-typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 { +- USHORT usHight; /* Image Hight */ +- USHORT usWidth; /* Image Width */ +- UCHAR ucSurface; /* Surface 1 or 2 */ +- UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ +- UCHAR ucPadding[2]; +-} ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2; +- +-typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION { +- ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; +- ENABLE_YUV_PS_ALLOCATION sReserved; /* Don't set this one */ +-} ENABLE_GRAPH_SURFACE_PS_ALLOCATION; +- +-typedef struct _MEMORY_CLEAN_UP_PARAMETERS { +- USHORT usMemoryStart; /* in 8Kb boundry, offset from memory base address */ +- USHORT usMemorySize; /* 8Kb blocks aligned */ +-} MEMORY_CLEAN_UP_PARAMETERS; ++typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS ++{ ++ ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position ++ UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset ++ UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset ++ UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 ++ UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE ++}ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; ++ ++typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION ++{ ++ ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; ++ ENABLE_CRTC_PARAMETERS sReserved; ++}ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; ++ ++typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS ++{ ++ USHORT usHight; // Image Hight ++ USHORT usWidth; // Image Width ++ UCHAR ucSurface; // Surface 1 or 2 ++ UCHAR ucPadding[3]; ++}ENABLE_GRAPH_SURFACE_PARAMETERS; ++ ++typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 ++{ ++ USHORT usHight; // Image Hight ++ USHORT usWidth; // Image Width ++ UCHAR ucSurface; // Surface 1 or 2 ++ UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE ++ UCHAR ucPadding[2]; ++}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2; ++ ++typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3 ++{ ++ USHORT usHight; // Image Hight ++ USHORT usWidth; // Image Width ++ UCHAR ucSurface; // Surface 1 or 2 ++ UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE ++ USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0. ++}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3; ++ ++typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION ++{ ++ ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; ++ ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one ++}ENABLE_GRAPH_SURFACE_PS_ALLOCATION; ++ ++typedef struct _MEMORY_CLEAN_UP_PARAMETERS ++{ ++ USHORT usMemoryStart; //in 8Kb boundry, offset from memory base address ++ USHORT usMemorySize; //8Kb blocks aligned ++}MEMORY_CLEAN_UP_PARAMETERS; + #define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS + +-typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS { +- USHORT usX_Size; /* When use as input parameter, usX_Size indicates which CRTC */ +- USHORT usY_Size; +-} GET_DISPLAY_SURFACE_SIZE_PARAMETERS; ++typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS ++{ ++ USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC ++ USHORT usY_Size; ++}GET_DISPLAY_SURFACE_SIZE_PARAMETERS; + +-typedef struct _INDIRECT_IO_ACCESS { +- ATOM_COMMON_TABLE_HEADER sHeader; +- UCHAR IOAccessSequence[256]; ++typedef struct _INDIRECT_IO_ACCESS ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ UCHAR IOAccessSequence[256]; + } INDIRECT_IO_ACCESS; + + #define INDIRECT_READ 0x00 +@@ -3615,93 +4414,108 @@ typedef struct _INDIRECT_IO_ACCESS { + #define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ + #define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE + +-typedef struct _ATOM_OEM_INFO { +- ATOM_COMMON_TABLE_HEADER sHeader; +- ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; +-} ATOM_OEM_INFO; +- +-typedef struct _ATOM_TV_MODE { +- UCHAR ucVMode_Num; /* Video mode number */ +- UCHAR ucTV_Mode_Num; /* Internal TV mode number */ +-} ATOM_TV_MODE; +- +-typedef struct _ATOM_BIOS_INT_TVSTD_MODE { +- ATOM_COMMON_TABLE_HEADER sHeader; +- USHORT usTV_Mode_LUT_Offset; /* Pointer to standard to internal number conversion table */ +- USHORT usTV_FIFO_Offset; /* Pointer to FIFO entry table */ +- USHORT usNTSC_Tbl_Offset; /* Pointer to SDTV_Mode_NTSC table */ +- USHORT usPAL_Tbl_Offset; /* Pointer to SDTV_Mode_PAL table */ +- USHORT usCV_Tbl_Offset; /* Pointer to SDTV_Mode_PAL table */ +-} ATOM_BIOS_INT_TVSTD_MODE; +- +-typedef struct _ATOM_TV_MODE_SCALER_PTR { +- USHORT ucFilter0_Offset; /* Pointer to filter format 0 coefficients */ +- USHORT usFilter1_Offset; /* Pointer to filter format 0 coefficients */ +- UCHAR ucTV_Mode_Num; +-} ATOM_TV_MODE_SCALER_PTR; +- +-typedef struct _ATOM_STANDARD_VESA_TIMING { +- ATOM_COMMON_TABLE_HEADER sHeader; +- ATOM_DTD_FORMAT aModeTimings[16]; /* 16 is not the real array number, just for initial allocation */ +-} ATOM_STANDARD_VESA_TIMING; +- +-typedef struct _ATOM_STD_FORMAT { +- USHORT usSTD_HDisp; +- USHORT usSTD_VDisp; +- USHORT usSTD_RefreshRate; +- USHORT usReserved; +-} ATOM_STD_FORMAT; +- +-typedef struct _ATOM_VESA_TO_EXTENDED_MODE { +- USHORT usVESA_ModeNumber; +- USHORT usExtendedModeNumber; +-} ATOM_VESA_TO_EXTENDED_MODE; +- +-typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT { +- ATOM_COMMON_TABLE_HEADER sHeader; +- ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; +-} ATOM_VESA_TO_INTENAL_MODE_LUT; ++typedef struct _ATOM_OEM_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; ++}ATOM_OEM_INFO; ++ ++typedef struct _ATOM_TV_MODE ++{ ++ UCHAR ucVMode_Num; //Video mode number ++ UCHAR ucTV_Mode_Num; //Internal TV mode number ++}ATOM_TV_MODE; ++ ++typedef struct _ATOM_BIOS_INT_TVSTD_MODE ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table ++ USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table ++ USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table ++ USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table ++ USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table ++}ATOM_BIOS_INT_TVSTD_MODE; ++ ++ ++typedef struct _ATOM_TV_MODE_SCALER_PTR ++{ ++ USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients ++ USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients ++ UCHAR ucTV_Mode_Num; ++}ATOM_TV_MODE_SCALER_PTR; ++ ++typedef struct _ATOM_STANDARD_VESA_TIMING ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation ++}ATOM_STANDARD_VESA_TIMING; ++ ++ ++typedef struct _ATOM_STD_FORMAT ++{ ++ USHORT usSTD_HDisp; ++ USHORT usSTD_VDisp; ++ USHORT usSTD_RefreshRate; ++ USHORT usReserved; ++}ATOM_STD_FORMAT; ++ ++typedef struct _ATOM_VESA_TO_EXTENDED_MODE ++{ ++ USHORT usVESA_ModeNumber; ++ USHORT usExtendedModeNumber; ++}ATOM_VESA_TO_EXTENDED_MODE; ++ ++typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; ++}ATOM_VESA_TO_INTENAL_MODE_LUT; + + /*************** ATOM Memory Related Data Structure ***********************/ +-typedef struct _ATOM_MEMORY_VENDOR_BLOCK { +- UCHAR ucMemoryType; +- UCHAR ucMemoryVendor; +- UCHAR ucAdjMCId; +- UCHAR ucDynClkId; +- ULONG ulDllResetClkRange; +-} ATOM_MEMORY_VENDOR_BLOCK; +- +-typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG { ++typedef struct _ATOM_MEMORY_VENDOR_BLOCK{ ++ UCHAR ucMemoryType; ++ UCHAR ucMemoryVendor; ++ UCHAR ucAdjMCId; ++ UCHAR ucDynClkId; ++ ULONG ulDllResetClkRange; ++}ATOM_MEMORY_VENDOR_BLOCK; ++ ++ ++typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{ + #if ATOM_BIG_ENDIAN +- ULONG ucMemBlkId:8; +- ULONG ulMemClockRange:24; ++ ULONG ucMemBlkId:8; ++ ULONG ulMemClockRange:24; + #else +- ULONG ulMemClockRange:24; +- ULONG ucMemBlkId:8; ++ ULONG ulMemClockRange:24; ++ ULONG ucMemBlkId:8; + #endif +-} ATOM_MEMORY_SETTING_ID_CONFIG; +- +-typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS { +- ATOM_MEMORY_SETTING_ID_CONFIG slAccess; +- ULONG ulAccess; +-} ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; +- +-typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK { +- ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID; +- ULONG aulMemData[1]; +-} ATOM_MEMORY_SETTING_DATA_BLOCK; +- +-typedef struct _ATOM_INIT_REG_INDEX_FORMAT { +- USHORT usRegIndex; /* MC register index */ +- UCHAR ucPreRegDataLength; /* offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf */ +-} ATOM_INIT_REG_INDEX_FORMAT; +- +-typedef struct _ATOM_INIT_REG_BLOCK { +- USHORT usRegIndexTblSize; /* size of asRegIndexBuf */ +- USHORT usRegDataBlkSize; /* size of ATOM_MEMORY_SETTING_DATA_BLOCK */ +- ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1]; +- ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1]; +-} ATOM_INIT_REG_BLOCK; ++}ATOM_MEMORY_SETTING_ID_CONFIG; ++ ++typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ++{ ++ ATOM_MEMORY_SETTING_ID_CONFIG slAccess; ++ ULONG ulAccess; ++}ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; ++ ++ ++typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{ ++ ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID; ++ ULONG aulMemData[1]; ++}ATOM_MEMORY_SETTING_DATA_BLOCK; ++ ++ ++typedef struct _ATOM_INIT_REG_INDEX_FORMAT{ ++ USHORT usRegIndex; // MC register index ++ UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf ++}ATOM_INIT_REG_INDEX_FORMAT; ++ ++ ++typedef struct _ATOM_INIT_REG_BLOCK{ ++ USHORT usRegIndexTblSize; //size of asRegIndexBuf ++ USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK ++ ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1]; ++ ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1]; ++}ATOM_INIT_REG_BLOCK; + + #define END_OF_REG_INDEX_BLOCK 0x0ffff + #define END_OF_REG_DATA_BLOCK 0x00000000 +@@ -3716,16 +4530,19 @@ typedef struct _ATOM_INIT_REG_BLOCK { + #define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1) + #define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1) + +-typedef struct _ATOM_MC_INIT_PARAM_TABLE { +- ATOM_COMMON_TABLE_HEADER sHeader; +- USHORT usAdjustARB_SEQDataOffset; +- USHORT usMCInitMemTypeTblOffset; +- USHORT usMCInitCommonTblOffset; +- USHORT usMCInitPowerDownTblOffset; +- ULONG ulARB_SEQDataBuf[32]; +- ATOM_INIT_REG_BLOCK asMCInitMemType; +- ATOM_INIT_REG_BLOCK asMCInitCommon; +-} ATOM_MC_INIT_PARAM_TABLE; ++ ++typedef struct _ATOM_MC_INIT_PARAM_TABLE ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT usAdjustARB_SEQDataOffset; ++ USHORT usMCInitMemTypeTblOffset; ++ USHORT usMCInitCommonTblOffset; ++ USHORT usMCInitPowerDownTblOffset; ++ ULONG ulARB_SEQDataBuf[32]; ++ ATOM_INIT_REG_BLOCK asMCInitMemType; ++ ATOM_INIT_REG_BLOCK asMCInitCommon; ++}ATOM_MC_INIT_PARAM_TABLE; ++ + + #define _4Mx16 0x2 + #define _4Mx32 0x3 +@@ -3751,221 +4568,272 @@ typedef struct _ATOM_MC_INIT_PARAM_TABLE { + + #define QIMONDA INFINEON + #define PROMOS MOSEL ++#define KRETON INFINEON + +-/* ///////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// */ ++/////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// + + #define UCODE_ROM_START_ADDRESS 0x1c000 +-#define UCODE_SIGNATURE 0x4375434d /* 'MCuC' - MC uCode */ +- +-/* uCode block header for reference */ +- +-typedef struct _MCuCodeHeader { +- ULONG ulSignature; +- UCHAR ucRevision; +- UCHAR ucChecksum; +- UCHAR ucReserved1; +- UCHAR ucReserved2; +- USHORT usParametersLength; +- USHORT usUCodeLength; +- USHORT usReserved1; +- USHORT usReserved2; ++#define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode ++ ++//uCode block header for reference ++ ++typedef struct _MCuCodeHeader ++{ ++ ULONG ulSignature; ++ UCHAR ucRevision; ++ UCHAR ucChecksum; ++ UCHAR ucReserved1; ++ UCHAR ucReserved2; ++ USHORT usParametersLength; ++ USHORT usUCodeLength; ++ USHORT usReserved1; ++ USHORT usReserved2; + } MCuCodeHeader; + +-/* //////////////////////////////////////////////////////////////////////////////// */ ++////////////////////////////////////////////////////////////////////////////////// + + #define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16 + + #define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF +-typedef struct _ATOM_VRAM_MODULE_V1 { +- ULONG ulReserved; +- USHORT usEMRSValue; +- USHORT usMRSValue; +- USHORT usReserved; +- UCHAR ucExtMemoryID; /* An external indicator (by hardcode, callback or pin) to tell what is the current memory module */ +- UCHAR ucMemoryType; /* [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; */ +- UCHAR ucMemoryVenderID; /* Predefined,never change across designs or memory type/vender */ +- UCHAR ucMemoryDeviceCfg; /* [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... */ +- UCHAR ucRow; /* Number of Row,in power of 2; */ +- UCHAR ucColumn; /* Number of Column,in power of 2; */ +- UCHAR ucBank; /* Nunber of Bank; */ +- UCHAR ucRank; /* Number of Rank, in power of 2 */ +- UCHAR ucChannelNum; /* Number of channel; */ +- UCHAR ucChannelConfig; /* [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 */ +- UCHAR ucDefaultMVDDQ_ID; /* Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; */ +- UCHAR ucDefaultMVDDC_ID; /* Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; */ +- UCHAR ucReserved[2]; +-} ATOM_VRAM_MODULE_V1; +- +-typedef struct _ATOM_VRAM_MODULE_V2 { +- ULONG ulReserved; +- ULONG ulFlags; /* To enable/disable functionalities based on memory type */ +- ULONG ulEngineClock; /* Override of default engine clock for particular memory type */ +- ULONG ulMemoryClock; /* Override of default memory clock for particular memory type */ +- USHORT usEMRS2Value; /* EMRS2 Value is used for GDDR2 and GDDR4 memory type */ +- USHORT usEMRS3Value; /* EMRS3 Value is used for GDDR2 and GDDR4 memory type */ +- USHORT usEMRSValue; +- USHORT usMRSValue; +- USHORT usReserved; +- UCHAR ucExtMemoryID; /* An external indicator (by hardcode, callback or pin) to tell what is the current memory module */ +- UCHAR ucMemoryType; /* [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; */ +- UCHAR ucMemoryVenderID; /* Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed */ +- UCHAR ucMemoryDeviceCfg; /* [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... */ +- UCHAR ucRow; /* Number of Row,in power of 2; */ +- UCHAR ucColumn; /* Number of Column,in power of 2; */ +- UCHAR ucBank; /* Nunber of Bank; */ +- UCHAR ucRank; /* Number of Rank, in power of 2 */ +- UCHAR ucChannelNum; /* Number of channel; */ +- UCHAR ucChannelConfig; /* [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 */ +- UCHAR ucDefaultMVDDQ_ID; /* Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; */ +- UCHAR ucDefaultMVDDC_ID; /* Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; */ +- UCHAR ucRefreshRateFactor; +- UCHAR ucReserved[3]; +-} ATOM_VRAM_MODULE_V2; +- +-typedef struct _ATOM_MEMORY_TIMING_FORMAT { +- ULONG ulClkRange; /* memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing */ +- union { +- USHORT usMRS; /* mode register */ +- USHORT usDDR3_MR0; +- }; +- union { +- USHORT usEMRS; /* extended mode register */ +- USHORT usDDR3_MR1; +- }; +- UCHAR ucCL; /* CAS latency */ +- UCHAR ucWL; /* WRITE Latency */ +- UCHAR uctRAS; /* tRAS */ +- UCHAR uctRC; /* tRC */ +- UCHAR uctRFC; /* tRFC */ +- UCHAR uctRCDR; /* tRCDR */ +- UCHAR uctRCDW; /* tRCDW */ +- UCHAR uctRP; /* tRP */ +- UCHAR uctRRD; /* tRRD */ +- UCHAR uctWR; /* tWR */ +- UCHAR uctWTR; /* tWTR */ +- UCHAR uctPDIX; /* tPDIX */ +- UCHAR uctFAW; /* tFAW */ +- UCHAR uctAOND; /* tAOND */ +- union { +- struct { +- UCHAR ucflag; /* flag to control memory timing calculation. bit0= control EMRS2 Infineon */ +- UCHAR ucReserved; +- }; +- USHORT usDDR3_MR2; +- }; +-} ATOM_MEMORY_TIMING_FORMAT; +- +-typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 { +- ULONG ulClkRange; /* memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing */ +- USHORT usMRS; /* mode register */ +- USHORT usEMRS; /* extended mode register */ +- UCHAR ucCL; /* CAS latency */ +- UCHAR ucWL; /* WRITE Latency */ +- UCHAR uctRAS; /* tRAS */ +- UCHAR uctRC; /* tRC */ +- UCHAR uctRFC; /* tRFC */ +- UCHAR uctRCDR; /* tRCDR */ +- UCHAR uctRCDW; /* tRCDW */ +- UCHAR uctRP; /* tRP */ +- UCHAR uctRRD; /* tRRD */ +- UCHAR uctWR; /* tWR */ +- UCHAR uctWTR; /* tWTR */ +- UCHAR uctPDIX; /* tPDIX */ +- UCHAR uctFAW; /* tFAW */ +- UCHAR uctAOND; /* tAOND */ +- UCHAR ucflag; /* flag to control memory timing calculation. bit0= control EMRS2 Infineon */ +-/* ///////////////////////GDDR parameters/////////////////////////////////// */ +- UCHAR uctCCDL; /* */ +- UCHAR uctCRCRL; /* */ +- UCHAR uctCRCWL; /* */ +- UCHAR uctCKE; /* */ +- UCHAR uctCKRSE; /* */ +- UCHAR uctCKRSX; /* */ +- UCHAR uctFAW32; /* */ +- UCHAR ucReserved1; /* */ +- UCHAR ucReserved2; /* */ +- UCHAR ucTerminator; +-} ATOM_MEMORY_TIMING_FORMAT_V1; +- +-typedef struct _ATOM_MEMORY_FORMAT { +- ULONG ulDllDisClock; /* memory DLL will be disable when target memory clock is below this clock */ +- union { +- USHORT usEMRS2Value; /* EMRS2 Value is used for GDDR2 and GDDR4 memory type */ +- USHORT usDDR3_Reserved; /* Not used for DDR3 memory */ +- }; +- union { +- USHORT usEMRS3Value; /* EMRS3 Value is used for GDDR2 and GDDR4 memory type */ +- USHORT usDDR3_MR3; /* Used for DDR3 memory */ +- }; +- UCHAR ucMemoryType; /* [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; */ +- UCHAR ucMemoryVenderID; /* Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed */ +- UCHAR ucRow; /* Number of Row,in power of 2; */ +- UCHAR ucColumn; /* Number of Column,in power of 2; */ +- UCHAR ucBank; /* Nunber of Bank; */ +- UCHAR ucRank; /* Number of Rank, in power of 2 */ +- UCHAR ucBurstSize; /* burst size, 0= burst size=4 1= burst size=8 */ +- UCHAR ucDllDisBit; /* position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) */ +- UCHAR ucRefreshRateFactor; /* memory refresh rate in unit of ms */ +- UCHAR ucDensity; /* _8Mx32, _16Mx32, _16Mx16, _32Mx16 */ +- UCHAR ucPreamble; /* [7:4] Write Preamble, [3:0] Read Preamble */ +- UCHAR ucMemAttrib; /* Memory Device Addribute, like RDBI/WDBI etc */ +- ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; /* Memory Timing block sort from lower clock to higher clock */ +-} ATOM_MEMORY_FORMAT; +- +-typedef struct _ATOM_VRAM_MODULE_V3 { +- ULONG ulChannelMapCfg; /* board dependent paramenter:Channel combination */ +- USHORT usSize; /* size of ATOM_VRAM_MODULE_V3 */ +- USHORT usDefaultMVDDQ; /* board dependent parameter:Default Memory Core Voltage */ +- USHORT usDefaultMVDDC; /* board dependent parameter:Default Memory IO Voltage */ +- UCHAR ucExtMemoryID; /* An external indicator (by hardcode, callback or pin) to tell what is the current memory module */ +- UCHAR ucChannelNum; /* board dependent parameter:Number of channel; */ +- UCHAR ucChannelSize; /* board dependent parameter:32bit or 64bit */ +- UCHAR ucVREFI; /* board dependnt parameter: EXT or INT +160mv to -140mv */ +- UCHAR ucNPL_RT; /* board dependent parameter:NPL round trip delay, used for calculate memory timing parameters */ +- UCHAR ucFlag; /* To enable/disable functionalities based on memory type */ +- ATOM_MEMORY_FORMAT asMemory; /* describ all of video memory parameters from memory spec */ +-} ATOM_VRAM_MODULE_V3; +- +-/* ATOM_VRAM_MODULE_V3.ucNPL_RT */ ++typedef struct _ATOM_VRAM_MODULE_V1 ++{ ++ ULONG ulReserved; ++ USHORT usEMRSValue; ++ USHORT usMRSValue; ++ USHORT usReserved; ++ UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module ++ UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; ++ UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender ++ UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... ++ UCHAR ucRow; // Number of Row,in power of 2; ++ UCHAR ucColumn; // Number of Column,in power of 2; ++ UCHAR ucBank; // Nunber of Bank; ++ UCHAR ucRank; // Number of Rank, in power of 2 ++ UCHAR ucChannelNum; // Number of channel; ++ UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 ++ UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; ++ UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; ++ UCHAR ucReserved[2]; ++}ATOM_VRAM_MODULE_V1; ++ ++ ++typedef struct _ATOM_VRAM_MODULE_V2 ++{ ++ ULONG ulReserved; ++ ULONG ulFlags; // To enable/disable functionalities based on memory type ++ ULONG ulEngineClock; // Override of default engine clock for particular memory type ++ ULONG ulMemoryClock; // Override of default memory clock for particular memory type ++ USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type ++ USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type ++ USHORT usEMRSValue; ++ USHORT usMRSValue; ++ USHORT usReserved; ++ UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module ++ UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; ++ UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed ++ UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... ++ UCHAR ucRow; // Number of Row,in power of 2; ++ UCHAR ucColumn; // Number of Column,in power of 2; ++ UCHAR ucBank; // Nunber of Bank; ++ UCHAR ucRank; // Number of Rank, in power of 2 ++ UCHAR ucChannelNum; // Number of channel; ++ UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 ++ UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; ++ UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; ++ UCHAR ucRefreshRateFactor; ++ UCHAR ucReserved[3]; ++}ATOM_VRAM_MODULE_V2; ++ ++ ++typedef struct _ATOM_MEMORY_TIMING_FORMAT ++{ ++ ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing ++ union{ ++ USHORT usMRS; // mode register ++ USHORT usDDR3_MR0; ++ }; ++ union{ ++ USHORT usEMRS; // extended mode register ++ USHORT usDDR3_MR1; ++ }; ++ UCHAR ucCL; // CAS latency ++ UCHAR ucWL; // WRITE Latency ++ UCHAR uctRAS; // tRAS ++ UCHAR uctRC; // tRC ++ UCHAR uctRFC; // tRFC ++ UCHAR uctRCDR; // tRCDR ++ UCHAR uctRCDW; // tRCDW ++ UCHAR uctRP; // tRP ++ UCHAR uctRRD; // tRRD ++ UCHAR uctWR; // tWR ++ UCHAR uctWTR; // tWTR ++ UCHAR uctPDIX; // tPDIX ++ UCHAR uctFAW; // tFAW ++ UCHAR uctAOND; // tAOND ++ union ++ { ++ struct { ++ UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon ++ UCHAR ucReserved; ++ }; ++ USHORT usDDR3_MR2; ++ }; ++}ATOM_MEMORY_TIMING_FORMAT; ++ ++ ++typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 ++{ ++ ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing ++ USHORT usMRS; // mode register ++ USHORT usEMRS; // extended mode register ++ UCHAR ucCL; // CAS latency ++ UCHAR ucWL; // WRITE Latency ++ UCHAR uctRAS; // tRAS ++ UCHAR uctRC; // tRC ++ UCHAR uctRFC; // tRFC ++ UCHAR uctRCDR; // tRCDR ++ UCHAR uctRCDW; // tRCDW ++ UCHAR uctRP; // tRP ++ UCHAR uctRRD; // tRRD ++ UCHAR uctWR; // tWR ++ UCHAR uctWTR; // tWTR ++ UCHAR uctPDIX; // tPDIX ++ UCHAR uctFAW; // tFAW ++ UCHAR uctAOND; // tAOND ++ UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon ++////////////////////////////////////GDDR parameters/////////////////////////////////// ++ UCHAR uctCCDL; // ++ UCHAR uctCRCRL; // ++ UCHAR uctCRCWL; // ++ UCHAR uctCKE; // ++ UCHAR uctCKRSE; // ++ UCHAR uctCKRSX; // ++ UCHAR uctFAW32; // ++ UCHAR ucMR5lo; // ++ UCHAR ucMR5hi; // ++ UCHAR ucTerminator; ++}ATOM_MEMORY_TIMING_FORMAT_V1; ++ ++typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2 ++{ ++ ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing ++ USHORT usMRS; // mode register ++ USHORT usEMRS; // extended mode register ++ UCHAR ucCL; // CAS latency ++ UCHAR ucWL; // WRITE Latency ++ UCHAR uctRAS; // tRAS ++ UCHAR uctRC; // tRC ++ UCHAR uctRFC; // tRFC ++ UCHAR uctRCDR; // tRCDR ++ UCHAR uctRCDW; // tRCDW ++ UCHAR uctRP; // tRP ++ UCHAR uctRRD; // tRRD ++ UCHAR uctWR; // tWR ++ UCHAR uctWTR; // tWTR ++ UCHAR uctPDIX; // tPDIX ++ UCHAR uctFAW; // tFAW ++ UCHAR uctAOND; // tAOND ++ UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon ++////////////////////////////////////GDDR parameters/////////////////////////////////// ++ UCHAR uctCCDL; // ++ UCHAR uctCRCRL; // ++ UCHAR uctCRCWL; // ++ UCHAR uctCKE; // ++ UCHAR uctCKRSE; // ++ UCHAR uctCKRSX; // ++ UCHAR uctFAW32; // ++ UCHAR ucMR4lo; // ++ UCHAR ucMR4hi; // ++ UCHAR ucMR5lo; // ++ UCHAR ucMR5hi; // ++ UCHAR ucTerminator; ++ UCHAR ucReserved; ++}ATOM_MEMORY_TIMING_FORMAT_V2; ++ ++typedef struct _ATOM_MEMORY_FORMAT ++{ ++ ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock ++ union{ ++ USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type ++ USHORT usDDR3_Reserved; // Not used for DDR3 memory ++ }; ++ union{ ++ USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type ++ USHORT usDDR3_MR3; // Used for DDR3 memory ++ }; ++ UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; ++ UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed ++ UCHAR ucRow; // Number of Row,in power of 2; ++ UCHAR ucColumn; // Number of Column,in power of 2; ++ UCHAR ucBank; // Nunber of Bank; ++ UCHAR ucRank; // Number of Rank, in power of 2 ++ UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8 ++ UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) ++ UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms ++ UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 ++ UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble ++ UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc ++ ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; //Memory Timing block sort from lower clock to higher clock ++}ATOM_MEMORY_FORMAT; ++ ++ ++typedef struct _ATOM_VRAM_MODULE_V3 ++{ ++ ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination ++ USHORT usSize; // size of ATOM_VRAM_MODULE_V3 ++ USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage ++ USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage ++ UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module ++ UCHAR ucChannelNum; // board dependent parameter:Number of channel; ++ UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit ++ UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv ++ UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters ++ UCHAR ucFlag; // To enable/disable functionalities based on memory type ++ ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec ++}ATOM_VRAM_MODULE_V3; ++ ++ ++//ATOM_VRAM_MODULE_V3.ucNPL_RT + #define NPL_RT_MASK 0x0f + #define BATTERY_ODT_MASK 0xc0 + + #define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3 + +-typedef struct _ATOM_VRAM_MODULE_V4 { +- ULONG ulChannelMapCfg; /* board dependent parameter: Channel combination */ +- USHORT usModuleSize; /* size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE */ +- USHORT usPrivateReserved; /* BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! */ +- /* MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) */ +- USHORT usReserved; +- UCHAR ucExtMemoryID; /* An external indicator (by hardcode, callback or pin) to tell what is the current memory module */ +- UCHAR ucMemoryType; /* [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; */ +- UCHAR ucChannelNum; /* Number of channels present in this module config */ +- UCHAR ucChannelWidth; /* 0 - 32 bits; 1 - 64 bits */ +- UCHAR ucDensity; /* _8Mx32, _16Mx32, _16Mx16, _32Mx16 */ +- UCHAR ucFlag; /* To enable/disable functionalities based on memory type */ +- UCHAR ucMisc; /* bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 */ +- UCHAR ucVREFI; /* board dependent parameter */ +- UCHAR ucNPL_RT; /* board dependent parameter:NPL round trip delay, used for calculate memory timing parameters */ +- UCHAR ucPreamble; /* [7:4] Write Preamble, [3:0] Read Preamble */ +- UCHAR ucMemorySize; /* BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! */ +- /* Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros */ +- UCHAR ucReserved[3]; +- +-/* compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level */ +- union { +- USHORT usEMRS2Value; /* EMRS2 Value is used for GDDR2 and GDDR4 memory type */ +- USHORT usDDR3_Reserved; +- }; +- union { +- USHORT usEMRS3Value; /* EMRS3 Value is used for GDDR2 and GDDR4 memory type */ +- USHORT usDDR3_MR3; /* Used for DDR3 memory */ +- }; +- UCHAR ucMemoryVenderID; /* Predefined, If not predefined, vendor detection table gets executed */ +- UCHAR ucRefreshRateFactor; /* [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) */ +- UCHAR ucReserved2[2]; +- ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; /* Memory Timing block sort from lower clock to higher clock */ +-} ATOM_VRAM_MODULE_V4; ++typedef struct _ATOM_VRAM_MODULE_V4 ++{ ++ ULONG ulChannelMapCfg; // board dependent parameter: Channel combination ++ USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE ++ USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! ++ // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) ++ USHORT usReserved; ++ UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module ++ UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; ++ UCHAR ucChannelNum; // Number of channels present in this module config ++ UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits ++ UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 ++ UCHAR ucFlag; // To enable/disable functionalities based on memory type ++ UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 ++ UCHAR ucVREFI; // board dependent parameter ++ UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters ++ UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble ++ UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! ++ // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros ++ UCHAR ucReserved[3]; ++ ++//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level ++ union{ ++ USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type ++ USHORT usDDR3_Reserved; ++ }; ++ union{ ++ USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type ++ USHORT usDDR3_MR3; // Used for DDR3 memory ++ }; ++ UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed ++ UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) ++ UCHAR ucReserved2[2]; ++ ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock ++}ATOM_VRAM_MODULE_V4; + + #define VRAM_MODULE_V4_MISC_RANK_MASK 0x3 + #define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1 +@@ -3973,96 +4841,139 @@ typedef struct _ATOM_VRAM_MODULE_V4 { + #define VRAM_MODULE_V4_MISC_BL8 0x4 + #define VRAM_MODULE_V4_MISC_DUAL_CS 0x10 + +-typedef struct _ATOM_VRAM_MODULE_V5 { +- ULONG ulChannelMapCfg; /* board dependent parameter: Channel combination */ +- USHORT usModuleSize; /* size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE */ +- USHORT usPrivateReserved; /* BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! */ +- /* MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) */ +- USHORT usReserved; +- UCHAR ucExtMemoryID; /* An external indicator (by hardcode, callback or pin) to tell what is the current memory module */ +- UCHAR ucMemoryType; /* [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; */ +- UCHAR ucChannelNum; /* Number of channels present in this module config */ +- UCHAR ucChannelWidth; /* 0 - 32 bits; 1 - 64 bits */ +- UCHAR ucDensity; /* _8Mx32, _16Mx32, _16Mx16, _32Mx16 */ +- UCHAR ucFlag; /* To enable/disable functionalities based on memory type */ +- UCHAR ucMisc; /* bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 */ +- UCHAR ucVREFI; /* board dependent parameter */ +- UCHAR ucNPL_RT; /* board dependent parameter:NPL round trip delay, used for calculate memory timing parameters */ +- UCHAR ucPreamble; /* [7:4] Write Preamble, [3:0] Read Preamble */ +- UCHAR ucMemorySize; /* BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! */ +- /* Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros */ +- UCHAR ucReserved[3]; ++typedef struct _ATOM_VRAM_MODULE_V5 ++{ ++ ULONG ulChannelMapCfg; // board dependent parameter: Channel combination ++ USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE ++ USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! ++ // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) ++ USHORT usReserved; ++ UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module ++ UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; ++ UCHAR ucChannelNum; // Number of channels present in this module config ++ UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits ++ UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 ++ UCHAR ucFlag; // To enable/disable functionalities based on memory type ++ UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 ++ UCHAR ucVREFI; // board dependent parameter ++ UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters ++ UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble ++ UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! ++ // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros ++ UCHAR ucReserved[3]; ++ ++//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level ++ USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type ++ USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type ++ UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed ++ UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) ++ UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth ++ UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth ++ ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock ++}ATOM_VRAM_MODULE_V5; ++ ++typedef struct _ATOM_VRAM_MODULE_V6 ++{ ++ ULONG ulChannelMapCfg; // board dependent parameter: Channel combination ++ USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE ++ USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! ++ // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) ++ USHORT usReserved; ++ UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module ++ UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; ++ UCHAR ucChannelNum; // Number of channels present in this module config ++ UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits ++ UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 ++ UCHAR ucFlag; // To enable/disable functionalities based on memory type ++ UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 ++ UCHAR ucVREFI; // board dependent parameter ++ UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters ++ UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble ++ UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! ++ // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros ++ UCHAR ucReserved[3]; ++ ++//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level ++ USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type ++ USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type ++ UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed ++ UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) ++ UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth ++ UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth ++ ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock ++}ATOM_VRAM_MODULE_V6; ++ ++ ++ ++typedef struct _ATOM_VRAM_INFO_V2 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ UCHAR ucNumOfVRAMModule; ++ ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; ++}ATOM_VRAM_INFO_V2; + +-/* compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level */ +- USHORT usEMRS2Value; /* EMRS2 Value is used for GDDR2 and GDDR4 memory type */ +- USHORT usEMRS3Value; /* EMRS3 Value is used for GDDR2 and GDDR4 memory type */ +- UCHAR ucMemoryVenderID; /* Predefined, If not predefined, vendor detection table gets executed */ +- UCHAR ucRefreshRateFactor; /* [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) */ +- UCHAR ucFIFODepth; /* FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth */ +- UCHAR ucCDR_Bandwidth; /* [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth */ +- ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5]; /* Memory Timing block sort from lower clock to higher clock */ +-} ATOM_VRAM_MODULE_V5; +- +-typedef struct _ATOM_VRAM_INFO_V2 { +- ATOM_COMMON_TABLE_HEADER sHeader; +- UCHAR ucNumOfVRAMModule; +- ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; /* just for allocation, real number of blocks is in ucNumOfVRAMModule; */ +-} ATOM_VRAM_INFO_V2; +- +-typedef struct _ATOM_VRAM_INFO_V3 { +- ATOM_COMMON_TABLE_HEADER sHeader; +- USHORT usMemAdjustTblOffset; /* offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting */ +- USHORT usMemClkPatchTblOffset; /* offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting */ +- USHORT usRerseved; +- UCHAR aVID_PinsShift[9]; /* 8 bit strap maximum+terminator */ +- UCHAR ucNumOfVRAMModule; +- ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; /* just for allocation, real number of blocks is in ucNumOfVRAMModule; */ +- ATOM_INIT_REG_BLOCK asMemPatch; /* for allocation */ +- /* ATOM_INIT_REG_BLOCK aMemAdjust; */ +-} ATOM_VRAM_INFO_V3; ++typedef struct _ATOM_VRAM_INFO_V3 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting ++ USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting ++ USHORT usRerseved; ++ UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator ++ UCHAR ucNumOfVRAMModule; ++ ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; ++ ATOM_INIT_REG_BLOCK asMemPatch; // for allocation ++ // ATOM_INIT_REG_BLOCK aMemAdjust; ++}ATOM_VRAM_INFO_V3; + + #define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3 + +-typedef struct _ATOM_VRAM_INFO_V4 { +- ATOM_COMMON_TABLE_HEADER sHeader; +- USHORT usMemAdjustTblOffset; /* offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting */ +- USHORT usMemClkPatchTblOffset; /* offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting */ +- USHORT usRerseved; +- UCHAR ucMemDQ7_0ByteRemap; /* DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 */ +- ULONG ulMemDQ7_0BitRemap; /* each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] */ +- UCHAR ucReservde[4]; +- UCHAR ucNumOfVRAMModule; +- ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; /* just for allocation, real number of blocks is in ucNumOfVRAMModule; */ +- ATOM_INIT_REG_BLOCK asMemPatch; /* for allocation */ +- /* ATOM_INIT_REG_BLOCK aMemAdjust; */ +-} ATOM_VRAM_INFO_V4; +- +-typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO { +- ATOM_COMMON_TABLE_HEADER sHeader; +- UCHAR aVID_PinsShift[9]; /* 8 bit strap maximum+terminator */ +-} ATOM_VRAM_GPIO_DETECTION_INFO; +- +-typedef struct _ATOM_MEMORY_TRAINING_INFO { +- ATOM_COMMON_TABLE_HEADER sHeader; +- UCHAR ucTrainingLoop; +- UCHAR ucReserved[3]; +- ATOM_INIT_REG_BLOCK asMemTrainingSetting; +-} ATOM_MEMORY_TRAINING_INFO; +- +-typedef struct SW_I2C_CNTL_DATA_PARAMETERS { +- UCHAR ucControl; +- UCHAR ucData; +- UCHAR ucSatus; +- UCHAR ucTemp; ++typedef struct _ATOM_VRAM_INFO_V4 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting ++ USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting ++ USHORT usRerseved; ++ UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 ++ ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] ++ UCHAR ucReservde[4]; ++ UCHAR ucNumOfVRAMModule; ++ ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; ++ ATOM_INIT_REG_BLOCK asMemPatch; // for allocation ++ // ATOM_INIT_REG_BLOCK aMemAdjust; ++}ATOM_VRAM_INFO_V4; ++ ++typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator ++}ATOM_VRAM_GPIO_DETECTION_INFO; ++ ++ ++typedef struct _ATOM_MEMORY_TRAINING_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ UCHAR ucTrainingLoop; ++ UCHAR ucReserved[3]; ++ ATOM_INIT_REG_BLOCK asMemTrainingSetting; ++}ATOM_MEMORY_TRAINING_INFO; ++ ++ ++typedef struct SW_I2C_CNTL_DATA_PARAMETERS ++{ ++ UCHAR ucControl; ++ UCHAR ucData; ++ UCHAR ucSatus; ++ UCHAR ucTemp; + } SW_I2C_CNTL_DATA_PARAMETERS; + + #define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS + +-typedef struct _SW_I2C_IO_DATA_PARAMETERS { +- USHORT GPIO_Info; +- UCHAR ucAct; +- UCHAR ucData; +-} SW_I2C_IO_DATA_PARAMETERS; ++typedef struct _SW_I2C_IO_DATA_PARAMETERS ++{ ++ USHORT GPIO_Info; ++ UCHAR ucAct; ++ UCHAR ucData; ++ } SW_I2C_IO_DATA_PARAMETERS; + + #define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS + +@@ -4087,127 +4998,136 @@ typedef struct _SW_I2C_IO_DATA_PARAMETERS { + #define SW_I2C_CNTL_CLOSE 5 + #define SW_I2C_CNTL_WRITE1BIT 6 + +-/* ==============================VESA definition Portion=============================== */ ++//==============================VESA definition Portion=============================== + #define VESA_OEM_PRODUCT_REV '01.00' +-#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB /* refer to VBE spec p.32, no TTY support */ ++#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support + #define VESA_MODE_WIN_ATTRIBUTE 7 + #define VESA_WIN_SIZE 64 + +-typedef struct _PTR_32_BIT_STRUCTURE { +- USHORT Offset16; +- USHORT Segment16; ++typedef struct _PTR_32_BIT_STRUCTURE ++{ ++ USHORT Offset16; ++ USHORT Segment16; + } PTR_32_BIT_STRUCTURE; + +-typedef union _PTR_32_BIT_UNION { +- PTR_32_BIT_STRUCTURE SegmentOffset; +- ULONG Ptr32_Bit; ++typedef union _PTR_32_BIT_UNION ++{ ++ PTR_32_BIT_STRUCTURE SegmentOffset; ++ ULONG Ptr32_Bit; + } PTR_32_BIT_UNION; + +-typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE { +- UCHAR VbeSignature[4]; +- USHORT VbeVersion; +- PTR_32_BIT_UNION OemStringPtr; +- UCHAR Capabilities[4]; +- PTR_32_BIT_UNION VideoModePtr; +- USHORT TotalMemory; ++typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE ++{ ++ UCHAR VbeSignature[4]; ++ USHORT VbeVersion; ++ PTR_32_BIT_UNION OemStringPtr; ++ UCHAR Capabilities[4]; ++ PTR_32_BIT_UNION VideoModePtr; ++ USHORT TotalMemory; + } VBE_1_2_INFO_BLOCK_UPDATABLE; + +-typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE { +- VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock; +- USHORT OemSoftRev; +- PTR_32_BIT_UNION OemVendorNamePtr; +- PTR_32_BIT_UNION OemProductNamePtr; +- PTR_32_BIT_UNION OemProductRevPtr; ++ ++typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE ++{ ++ VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock; ++ USHORT OemSoftRev; ++ PTR_32_BIT_UNION OemVendorNamePtr; ++ PTR_32_BIT_UNION OemProductNamePtr; ++ PTR_32_BIT_UNION OemProductRevPtr; + } VBE_2_0_INFO_BLOCK_UPDATABLE; + +-typedef union _VBE_VERSION_UNION { +- VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock; +- VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock; ++typedef union _VBE_VERSION_UNION ++{ ++ VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock; ++ VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock; + } VBE_VERSION_UNION; + +-typedef struct _VBE_INFO_BLOCK { +- VBE_VERSION_UNION UpdatableVBE_Info; +- UCHAR Reserved[222]; +- UCHAR OemData[256]; ++typedef struct _VBE_INFO_BLOCK ++{ ++ VBE_VERSION_UNION UpdatableVBE_Info; ++ UCHAR Reserved[222]; ++ UCHAR OemData[256]; + } VBE_INFO_BLOCK; + +-typedef struct _VBE_FP_INFO { +- USHORT HSize; +- USHORT VSize; +- USHORT FPType; +- UCHAR RedBPP; +- UCHAR GreenBPP; +- UCHAR BlueBPP; +- UCHAR ReservedBPP; +- ULONG RsvdOffScrnMemSize; +- ULONG RsvdOffScrnMEmPtr; +- UCHAR Reserved[14]; ++typedef struct _VBE_FP_INFO ++{ ++ USHORT HSize; ++ USHORT VSize; ++ USHORT FPType; ++ UCHAR RedBPP; ++ UCHAR GreenBPP; ++ UCHAR BlueBPP; ++ UCHAR ReservedBPP; ++ ULONG RsvdOffScrnMemSize; ++ ULONG RsvdOffScrnMEmPtr; ++ UCHAR Reserved[14]; + } VBE_FP_INFO; + +-typedef struct _VESA_MODE_INFO_BLOCK { +-/* Mandatory information for all VBE revisions */ +- USHORT ModeAttributes; /* dw ? ; mode attributes */ +- UCHAR WinAAttributes; /* db ? ; window A attributes */ +- UCHAR WinBAttributes; /* db ? ; window B attributes */ +- USHORT WinGranularity; /* dw ? ; window granularity */ +- USHORT WinSize; /* dw ? ; window size */ +- USHORT WinASegment; /* dw ? ; window A start segment */ +- USHORT WinBSegment; /* dw ? ; window B start segment */ +- ULONG WinFuncPtr; /* dd ? ; real mode pointer to window function */ +- USHORT BytesPerScanLine; /* dw ? ; bytes per scan line */ +- +-/* ; Mandatory information for VBE 1.2 and above */ +- USHORT XResolution; /* dw ? ; horizontal resolution in pixels or characters */ +- USHORT YResolution; /* dw ? ; vertical resolution in pixels or characters */ +- UCHAR XCharSize; /* db ? ; character cell width in pixels */ +- UCHAR YCharSize; /* db ? ; character cell height in pixels */ +- UCHAR NumberOfPlanes; /* db ? ; number of memory planes */ +- UCHAR BitsPerPixel; /* db ? ; bits per pixel */ +- UCHAR NumberOfBanks; /* db ? ; number of banks */ +- UCHAR MemoryModel; /* db ? ; memory model type */ +- UCHAR BankSize; /* db ? ; bank size in KB */ +- UCHAR NumberOfImagePages; /* db ? ; number of images */ +- UCHAR ReservedForPageFunction; /* db 1 ; reserved for page function */ +- +-/* ; Direct Color fields(required for direct/6 and YUV/7 memory models) */ +- UCHAR RedMaskSize; /* db ? ; size of direct color red mask in bits */ +- UCHAR RedFieldPosition; /* db ? ; bit position of lsb of red mask */ +- UCHAR GreenMaskSize; /* db ? ; size of direct color green mask in bits */ +- UCHAR GreenFieldPosition; /* db ? ; bit position of lsb of green mask */ +- UCHAR BlueMaskSize; /* db ? ; size of direct color blue mask in bits */ +- UCHAR BlueFieldPosition; /* db ? ; bit position of lsb of blue mask */ +- UCHAR RsvdMaskSize; /* db ? ; size of direct color reserved mask in bits */ +- UCHAR RsvdFieldPosition; /* db ? ; bit position of lsb of reserved mask */ +- UCHAR DirectColorModeInfo; /* db ? ; direct color mode attributes */ +- +-/* ; Mandatory information for VBE 2.0 and above */ +- ULONG PhysBasePtr; /* dd ? ; physical address for flat memory frame buffer */ +- ULONG Reserved_1; /* dd 0 ; reserved - always set to 0 */ +- USHORT Reserved_2; /* dw 0 ; reserved - always set to 0 */ +- +-/* ; Mandatory information for VBE 3.0 and above */ +- USHORT LinBytesPerScanLine; /* dw ? ; bytes per scan line for linear modes */ +- UCHAR BnkNumberOfImagePages; /* db ? ; number of images for banked modes */ +- UCHAR LinNumberOfImagPages; /* db ? ; number of images for linear modes */ +- UCHAR LinRedMaskSize; /* db ? ; size of direct color red mask(linear modes) */ +- UCHAR LinRedFieldPosition; /* db ? ; bit position of lsb of red mask(linear modes) */ +- UCHAR LinGreenMaskSize; /* db ? ; size of direct color green mask(linear modes) */ +- UCHAR LinGreenFieldPosition; /* db ? ; bit position of lsb of green mask(linear modes) */ +- UCHAR LinBlueMaskSize; /* db ? ; size of direct color blue mask(linear modes) */ +- UCHAR LinBlueFieldPosition; /* db ? ; bit position of lsb of blue mask(linear modes) */ +- UCHAR LinRsvdMaskSize; /* db ? ; size of direct color reserved mask(linear modes) */ +- UCHAR LinRsvdFieldPosition; /* db ? ; bit position of lsb of reserved mask(linear modes) */ +- ULONG MaxPixelClock; /* dd ? ; maximum pixel clock(in Hz) for graphics mode */ +- UCHAR Reserved; /* db 190 dup (0) */ ++typedef struct _VESA_MODE_INFO_BLOCK ++{ ++// Mandatory information for all VBE revisions ++ USHORT ModeAttributes; // dw ? ; mode attributes ++ UCHAR WinAAttributes; // db ? ; window A attributes ++ UCHAR WinBAttributes; // db ? ; window B attributes ++ USHORT WinGranularity; // dw ? ; window granularity ++ USHORT WinSize; // dw ? ; window size ++ USHORT WinASegment; // dw ? ; window A start segment ++ USHORT WinBSegment; // dw ? ; window B start segment ++ ULONG WinFuncPtr; // dd ? ; real mode pointer to window function ++ USHORT BytesPerScanLine;// dw ? ; bytes per scan line ++ ++//; Mandatory information for VBE 1.2 and above ++ USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters ++ USHORT YResolution; // dw ? ; vertical resolution in pixels or characters ++ UCHAR XCharSize; // db ? ; character cell width in pixels ++ UCHAR YCharSize; // db ? ; character cell height in pixels ++ UCHAR NumberOfPlanes; // db ? ; number of memory planes ++ UCHAR BitsPerPixel; // db ? ; bits per pixel ++ UCHAR NumberOfBanks; // db ? ; number of banks ++ UCHAR MemoryModel; // db ? ; memory model type ++ UCHAR BankSize; // db ? ; bank size in KB ++ UCHAR NumberOfImagePages;// db ? ; number of images ++ UCHAR ReservedForPageFunction;//db 1 ; reserved for page function ++ ++//; Direct Color fields(required for direct/6 and YUV/7 memory models) ++ UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits ++ UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask ++ UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits ++ UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask ++ UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits ++ UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask ++ UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits ++ UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask ++ UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes ++ ++//; Mandatory information for VBE 2.0 and above ++ ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer ++ ULONG Reserved_1; // dd 0 ; reserved - always set to 0 ++ USHORT Reserved_2; // dw 0 ; reserved - always set to 0 ++ ++//; Mandatory information for VBE 3.0 and above ++ USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes ++ UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes ++ UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes ++ UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes) ++ UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes) ++ UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes) ++ UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes) ++ UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes) ++ UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes) ++ UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes) ++ UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes) ++ ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode ++ UCHAR Reserved; // db 190 dup (0) + } VESA_MODE_INFO_BLOCK; + +-/* BIOS function CALLS */ +-#define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 /* ATI Extended Function code */ ++// BIOS function CALLS ++#define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code + #define ATOM_BIOS_FUNCTION_COP_MODE 0x00 + #define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04 + #define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05 + #define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06 +-#define ATOM_BIOS_FUNCTION_GET_DDC 0x0B ++#define ATOM_BIOS_FUNCTION_GET_DDC 0x0B + #define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E + #define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F + #define ATOM_BIOS_FUNCTION_STV_STD 0x16 +@@ -4217,100 +5137,135 @@ typedef struct _VESA_MODE_INFO_BLOCK { + #define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 + #define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 + #define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 +-#define ATOM_BIOS_FUNCTION_HW_ICON 0x8A ++#define ATOM_BIOS_FUNCTION_HW_ICON 0x8A + #define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B +-#define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 /* Sub function 80 */ +-#define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 /* Sub function 80 */ ++#define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80 ++#define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80 + + #define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D + #define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E +-#define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F +-#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 /* Sub function 03 */ +-#define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 /* Sub function 7 */ +-#define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 /* Notify caller the current thermal state */ +-#define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 /* Notify caller the current critical state */ +-#define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 /* Sub function 85 */ +-#define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900 /* Sub function 89 */ +-#define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 /* Notify caller that ADC is supported */ +- +-#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 /* Set DPMS */ +-#define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 /* BL: Sub function 01 */ +-#define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 /* BL: Sub function 02 */ +-#define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 /* BH Parameter for DPMS ON. */ +-#define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 /* BH Parameter for DPMS STANDBY */ +-#define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 /* BH Parameter for DPMS SUSPEND */ +-#define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 /* BH Parameter for DPMS OFF */ +-#define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 /* BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) */ ++#define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F ++#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 ++#define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7 ++#define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state ++#define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state ++#define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85 ++#define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89 ++#define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported ++ ++ ++#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS ++#define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 ++#define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 ++#define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. ++#define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY ++#define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND ++#define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF ++#define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) + + #define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L + #define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L + #define ATOM_BIOS_REG_LOW_MASK 0x000000FFL + +-/* structure used for VBIOS only */ ++// structure used for VBIOS only + +-/* DispOutInfoTable */ +-typedef struct _ASIC_TRANSMITTER_INFO { ++//DispOutInfoTable ++typedef struct _ASIC_TRANSMITTER_INFO ++{ + USHORT usTransmitterObjId; + USHORT usSupportDevice; +- UCHAR ucTransmitterCmdTblId; +- UCHAR ucConfig; +- UCHAR ucEncoderID; /* available 1st encoder ( default ) */ +- UCHAR ucOptionEncoderID; /* available 2nd encoder ( optional ) */ +- UCHAR uc2ndEncoderID; +- UCHAR ucReserved; +-} ASIC_TRANSMITTER_INFO; +- +-typedef struct _ASIC_ENCODER_INFO { ++ UCHAR ucTransmitterCmdTblId; ++ UCHAR ucConfig; ++ UCHAR ucEncoderID; //available 1st encoder ( default ) ++ UCHAR ucOptionEncoderID; //available 2nd encoder ( optional ) ++ UCHAR uc2ndEncoderID; ++ UCHAR ucReserved; ++}ASIC_TRANSMITTER_INFO; ++ ++typedef struct _ASIC_ENCODER_INFO ++{ + UCHAR ucEncoderID; + UCHAR ucEncoderConfig; +- USHORT usEncoderCmdTblId; +-} ASIC_ENCODER_INFO; ++ USHORT usEncoderCmdTblId; ++}ASIC_ENCODER_INFO; ++ ++typedef struct _ATOM_DISP_OUT_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT ptrTransmitterInfo; ++ USHORT ptrEncoderInfo; ++ ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; ++ ASIC_ENCODER_INFO asEncoderInfo[1]; ++}ATOM_DISP_OUT_INFO; + +-typedef struct _ATOM_DISP_OUT_INFO { +- ATOM_COMMON_TABLE_HEADER sHeader; ++typedef struct _ATOM_DISP_OUT_INFO_V2 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; + USHORT ptrTransmitterInfo; + USHORT ptrEncoderInfo; +- ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; +- ASIC_ENCODER_INFO asEncoderInfo[1]; +-} ATOM_DISP_OUT_INFO; ++ USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. ++ ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; ++ ASIC_ENCODER_INFO asEncoderInfo[1]; ++}ATOM_DISP_OUT_INFO_V2; + +-/* DispDevicePriorityInfo */ +-typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO { +- ATOM_COMMON_TABLE_HEADER sHeader; ++// DispDevicePriorityInfo ++typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; + USHORT asDevicePriority[16]; +-} ATOM_DISPLAY_DEVICE_PRIORITY_INFO; +- +-/* ProcessAuxChannelTransactionTable */ +-typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS { +- USHORT lpAuxRequest; +- USHORT lpDataOut; +- UCHAR ucChannelID; +- union { +- UCHAR ucReplyStatus; +- UCHAR ucDelay; ++}ATOM_DISPLAY_DEVICE_PRIORITY_INFO; ++ ++//ProcessAuxChannelTransactionTable ++typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS ++{ ++ USHORT lpAuxRequest; ++ USHORT lpDataOut; ++ UCHAR ucChannelID; ++ union ++ { ++ UCHAR ucReplyStatus; ++ UCHAR ucDelay; ++ }; ++ UCHAR ucDataOutLen; ++ UCHAR ucReserved; ++}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; ++ ++//ProcessAuxChannelTransactionTable ++typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 ++{ ++ USHORT lpAuxRequest; ++ USHORT lpDataOut; ++ UCHAR ucChannelID; ++ union ++ { ++ UCHAR ucReplyStatus; ++ UCHAR ucDelay; + }; +- UCHAR ucDataOutLen; +- UCHAR ucReserved; +-} PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; ++ UCHAR ucDataOutLen; ++ UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 ++}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2; + + #define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS + +-/* GetSinkType */ ++//GetSinkType + +-typedef struct _DP_ENCODER_SERVICE_PARAMETERS { ++typedef struct _DP_ENCODER_SERVICE_PARAMETERS ++{ + USHORT ucLinkClock; +- union { +- UCHAR ucConfig; /* for DP training command */ +- UCHAR ucI2cId; /* use for GET_SINK_TYPE command */ ++ union ++ { ++ UCHAR ucConfig; // for DP training command ++ UCHAR ucI2cId; // use for GET_SINK_TYPE command + }; + UCHAR ucAction; + UCHAR ucStatus; + UCHAR ucLaneNum; + UCHAR ucReserved[2]; +-} DP_ENCODER_SERVICE_PARAMETERS; ++}DP_ENCODER_SERVICE_PARAMETERS; + +-/* ucAction */ ++// ucAction + #define ATOM_DP_ACTION_GET_SINK_TYPE 0x01 ++/* obselete */ + #define ATOM_DP_ACTION_TRAINING_START 0x02 + #define ATOM_DP_ACTION_TRAINING_COMPLETE 0x03 + #define ATOM_DP_ACTION_TRAINING_PATTERN_SEL 0x04 +@@ -4318,7 +5273,7 @@ typedef struct _DP_ENCODER_SERVICE_PARAMETERS { + #define ATOM_DP_ACTION_GET_VSWING_PREEMP 0x06 + #define ATOM_DP_ACTION_BLANKING 0x07 + +-/* ucConfig */ ++// ucConfig + #define ATOM_DP_CONFIG_ENCODER_SEL_MASK 0x03 + #define ATOM_DP_CONFIG_DIG1_ENCODER 0x00 + #define ATOM_DP_CONFIG_DIG2_ENCODER 0x01 +@@ -4326,14 +5281,14 @@ typedef struct _DP_ENCODER_SERVICE_PARAMETERS { + #define ATOM_DP_CONFIG_LINK_SEL_MASK 0x04 + #define ATOM_DP_CONFIG_LINK_A 0x00 + #define ATOM_DP_CONFIG_LINK_B 0x04 +- ++/* /obselete */ + #define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS + +-/* DP_TRAINING_TABLE */ +-#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR ++// DP_TRAINING_TABLE ++#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR + #define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) +-#define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16) +-#define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24) ++#define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) ++#define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 ) + #define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32) + #define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40) + #define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48) +@@ -4341,183 +5296,241 @@ typedef struct _DP_ENCODER_SERVICE_PARAMETERS { + #define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64) + #define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72) + #define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76) +-#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) ++#define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) ++#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84) + +-typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS { +- UCHAR ucI2CSpeed; +- union { +- UCHAR ucRegIndex; +- UCHAR ucStatus; ++typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS ++{ ++ UCHAR ucI2CSpeed; ++ union ++ { ++ UCHAR ucRegIndex; ++ UCHAR ucStatus; + }; +- USHORT lpI2CDataOut; +- UCHAR ucFlag; +- UCHAR ucTransBytes; +- UCHAR ucSlaveAddr; +- UCHAR ucLineNumber; +-} PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS; ++ USHORT lpI2CDataOut; ++ UCHAR ucFlag; ++ UCHAR ucTransBytes; ++ UCHAR ucSlaveAddr; ++ UCHAR ucLineNumber; ++}PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS; + + #define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS + +-/* ucFlag */ ++//ucFlag + #define HW_I2C_WRITE 1 + #define HW_I2C_READ 0 ++#define I2C_2BYTE_ADDR 0x02 + ++typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2 ++{ ++ UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ... ++ UCHAR ucReserved[3]; ++}SET_HWBLOCK_INSTANCE_PARAMETER_V2; ++ ++#define HWBLKINST_INSTANCE_MASK 0x07 ++#define HWBLKINST_HWBLK_MASK 0xF0 ++#define HWBLKINST_HWBLK_SHIFT 0x04 ++ ++//ucHWBlock ++#define SELECT_DISP_ENGINE 0 ++#define SELECT_DISP_PLL 1 ++#define SELECT_DCIO_UNIPHY_LINK0 2 ++#define SELECT_DCIO_UNIPHY_LINK1 3 ++#define SELECT_DCIO_IMPCAL 4 ++#define SELECT_DCIO_DIG 6 ++#define SELECT_CRTC_PIXEL_RATE 7 ++ ++/****************************************************************************/ ++//Portion VI: Definitinos for vbios MC scratch registers that driver used + /****************************************************************************/ +-/* Portion VI: Definitinos being oboselete */ ++ ++#define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000 ++#define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000 ++#define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000 ++#define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000 ++#define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000 ++#define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000 ++#define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000 ++ ++/****************************************************************************/ ++//Portion VI: Definitinos being oboselete + /****************************************************************************/ + +-/* ========================================================================================== */ +-/* Remove the definitions below when driver is ready! */ +-typedef struct _ATOM_DAC_INFO { +- ATOM_COMMON_TABLE_HEADER sHeader; +- USHORT usMaxFrequency; /* in 10kHz unit */ +- USHORT usReserved; +-} ATOM_DAC_INFO; +- +-typedef struct _COMPASSIONATE_DATA { +- ATOM_COMMON_TABLE_HEADER sHeader; +- +- /* ============================== DAC1 portion */ +- UCHAR ucDAC1_BG_Adjustment; +- UCHAR ucDAC1_DAC_Adjustment; +- USHORT usDAC1_FORCE_Data; +- /* ============================== DAC2 portion */ +- UCHAR ucDAC2_CRT2_BG_Adjustment; +- UCHAR ucDAC2_CRT2_DAC_Adjustment; +- USHORT usDAC2_CRT2_FORCE_Data; +- USHORT usDAC2_CRT2_MUX_RegisterIndex; +- UCHAR ucDAC2_CRT2_MUX_RegisterInfo; /* Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low */ +- UCHAR ucDAC2_NTSC_BG_Adjustment; +- UCHAR ucDAC2_NTSC_DAC_Adjustment; +- USHORT usDAC2_TV1_FORCE_Data; +- USHORT usDAC2_TV1_MUX_RegisterIndex; +- UCHAR ucDAC2_TV1_MUX_RegisterInfo; /* Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low */ +- UCHAR ucDAC2_CV_BG_Adjustment; +- UCHAR ucDAC2_CV_DAC_Adjustment; +- USHORT usDAC2_CV_FORCE_Data; +- USHORT usDAC2_CV_MUX_RegisterIndex; +- UCHAR ucDAC2_CV_MUX_RegisterInfo; /* Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low */ +- UCHAR ucDAC2_PAL_BG_Adjustment; +- UCHAR ucDAC2_PAL_DAC_Adjustment; +- USHORT usDAC2_TV2_FORCE_Data; +-} COMPASSIONATE_DATA; ++//========================================================================================== ++//Remove the definitions below when driver is ready! ++typedef struct _ATOM_DAC_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT usMaxFrequency; // in 10kHz unit ++ USHORT usReserved; ++}ATOM_DAC_INFO; ++ ++ ++typedef struct _COMPASSIONATE_DATA ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ ++ //============================== DAC1 portion ++ UCHAR ucDAC1_BG_Adjustment; ++ UCHAR ucDAC1_DAC_Adjustment; ++ USHORT usDAC1_FORCE_Data; ++ //============================== DAC2 portion ++ UCHAR ucDAC2_CRT2_BG_Adjustment; ++ UCHAR ucDAC2_CRT2_DAC_Adjustment; ++ USHORT usDAC2_CRT2_FORCE_Data; ++ USHORT usDAC2_CRT2_MUX_RegisterIndex; ++ UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low ++ UCHAR ucDAC2_NTSC_BG_Adjustment; ++ UCHAR ucDAC2_NTSC_DAC_Adjustment; ++ USHORT usDAC2_TV1_FORCE_Data; ++ USHORT usDAC2_TV1_MUX_RegisterIndex; ++ UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low ++ UCHAR ucDAC2_CV_BG_Adjustment; ++ UCHAR ucDAC2_CV_DAC_Adjustment; ++ USHORT usDAC2_CV_FORCE_Data; ++ USHORT usDAC2_CV_MUX_RegisterIndex; ++ UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low ++ UCHAR ucDAC2_PAL_BG_Adjustment; ++ UCHAR ucDAC2_PAL_DAC_Adjustment; ++ USHORT usDAC2_TV2_FORCE_Data; ++}COMPASSIONATE_DATA; + + /****************************Supported Device Info Table Definitions**********************/ +-/* ucConnectInfo: */ +-/* [7:4] - connector type */ +-/* = 1 - VGA connector */ +-/* = 2 - DVI-I */ +-/* = 3 - DVI-D */ +-/* = 4 - DVI-A */ +-/* = 5 - SVIDEO */ +-/* = 6 - COMPOSITE */ +-/* = 7 - LVDS */ +-/* = 8 - DIGITAL LINK */ +-/* = 9 - SCART */ +-/* = 0xA - HDMI_type A */ +-/* = 0xB - HDMI_type B */ +-/* = 0xE - Special case1 (DVI+DIN) */ +-/* Others=TBD */ +-/* [3:0] - DAC Associated */ +-/* = 0 - no DAC */ +-/* = 1 - DACA */ +-/* = 2 - DACB */ +-/* = 3 - External DAC */ +-/* Others=TBD */ +-/* */ +- +-typedef struct _ATOM_CONNECTOR_INFO { ++// ucConnectInfo: ++// [7:4] - connector type ++// = 1 - VGA connector ++// = 2 - DVI-I ++// = 3 - DVI-D ++// = 4 - DVI-A ++// = 5 - SVIDEO ++// = 6 - COMPOSITE ++// = 7 - LVDS ++// = 8 - DIGITAL LINK ++// = 9 - SCART ++// = 0xA - HDMI_type A ++// = 0xB - HDMI_type B ++// = 0xE - Special case1 (DVI+DIN) ++// Others=TBD ++// [3:0] - DAC Associated ++// = 0 - no DAC ++// = 1 - DACA ++// = 2 - DACB ++// = 3 - External DAC ++// Others=TBD ++// ++ ++typedef struct _ATOM_CONNECTOR_INFO ++{ + #if ATOM_BIG_ENDIAN +- UCHAR bfConnectorType:4; +- UCHAR bfAssociatedDAC:4; ++ UCHAR bfConnectorType:4; ++ UCHAR bfAssociatedDAC:4; + #else +- UCHAR bfAssociatedDAC:4; +- UCHAR bfConnectorType:4; ++ UCHAR bfAssociatedDAC:4; ++ UCHAR bfConnectorType:4; + #endif +-} ATOM_CONNECTOR_INFO; ++}ATOM_CONNECTOR_INFO; ++ ++typedef union _ATOM_CONNECTOR_INFO_ACCESS ++{ ++ ATOM_CONNECTOR_INFO sbfAccess; ++ UCHAR ucAccess; ++}ATOM_CONNECTOR_INFO_ACCESS; + +-typedef union _ATOM_CONNECTOR_INFO_ACCESS { +- ATOM_CONNECTOR_INFO sbfAccess; +- UCHAR ucAccess; +-} ATOM_CONNECTOR_INFO_ACCESS; ++typedef struct _ATOM_CONNECTOR_INFO_I2C ++{ ++ ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo; ++ ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; ++}ATOM_CONNECTOR_INFO_I2C; + +-typedef struct _ATOM_CONNECTOR_INFO_I2C { +- ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo; +- ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; +-} ATOM_CONNECTOR_INFO_I2C; + +-typedef struct _ATOM_SUPPORTED_DEVICES_INFO { +- ATOM_COMMON_TABLE_HEADER sHeader; +- USHORT usDeviceSupport; +- ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; +-} ATOM_SUPPORTED_DEVICES_INFO; ++typedef struct _ATOM_SUPPORTED_DEVICES_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT usDeviceSupport; ++ ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; ++}ATOM_SUPPORTED_DEVICES_INFO; + + #define NO_INT_SRC_MAPPED 0xFF + +-typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP { +- UCHAR ucIntSrcBitmap; +-} ATOM_CONNECTOR_INC_SRC_BITMAP; +- +-typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 { +- ATOM_COMMON_TABLE_HEADER sHeader; +- USHORT usDeviceSupport; +- ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; +- ATOM_CONNECTOR_INC_SRC_BITMAP +- asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; +-} ATOM_SUPPORTED_DEVICES_INFO_2; +- +-typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 { +- ATOM_COMMON_TABLE_HEADER sHeader; +- USHORT usDeviceSupport; +- ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; +- ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE]; +-} ATOM_SUPPORTED_DEVICES_INFO_2d1; ++typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP ++{ ++ UCHAR ucIntSrcBitmap; ++}ATOM_CONNECTOR_INC_SRC_BITMAP; ++ ++typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT usDeviceSupport; ++ ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; ++ ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; ++}ATOM_SUPPORTED_DEVICES_INFO_2; ++ ++typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT usDeviceSupport; ++ ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; ++ ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE]; ++}ATOM_SUPPORTED_DEVICES_INFO_2d1; + + #define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1 + +-typedef struct _ATOM_MISC_CONTROL_INFO { +- USHORT usFrequency; +- UCHAR ucPLL_ChargePump; /* PLL charge-pump gain control */ +- UCHAR ucPLL_DutyCycle; /* PLL duty cycle control */ +- UCHAR ucPLL_VCO_Gain; /* PLL VCO gain control */ +- UCHAR ucPLL_VoltageSwing; /* PLL driver voltage swing control */ +-} ATOM_MISC_CONTROL_INFO; ++ ++ ++typedef struct _ATOM_MISC_CONTROL_INFO ++{ ++ USHORT usFrequency; ++ UCHAR ucPLL_ChargePump; // PLL charge-pump gain control ++ UCHAR ucPLL_DutyCycle; // PLL duty cycle control ++ UCHAR ucPLL_VCO_Gain; // PLL VCO gain control ++ UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control ++}ATOM_MISC_CONTROL_INFO; ++ + + #define ATOM_MAX_MISC_INFO 4 + +-typedef struct _ATOM_TMDS_INFO { +- ATOM_COMMON_TABLE_HEADER sHeader; +- USHORT usMaxFrequency; /* in 10Khz */ +- ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; +-} ATOM_TMDS_INFO; ++typedef struct _ATOM_TMDS_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT usMaxFrequency; // in 10Khz ++ ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; ++}ATOM_TMDS_INFO; ++ ++ ++typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE ++{ ++ UCHAR ucTVStandard; //Same as TV standards defined above, ++ UCHAR ucPadding[1]; ++}ATOM_ENCODER_ANALOG_ATTRIBUTE; + +-typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE { +- UCHAR ucTVStandard; /* Same as TV standards defined above, */ +- UCHAR ucPadding[1]; +-} ATOM_ENCODER_ANALOG_ATTRIBUTE; ++typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE ++{ ++ UCHAR ucAttribute; //Same as other digital encoder attributes defined above ++ UCHAR ucPadding[1]; ++}ATOM_ENCODER_DIGITAL_ATTRIBUTE; + +-typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE { +- UCHAR ucAttribute; /* Same as other digital encoder attributes defined above */ +- UCHAR ucPadding[1]; +-} ATOM_ENCODER_DIGITAL_ATTRIBUTE; ++typedef union _ATOM_ENCODER_ATTRIBUTE ++{ ++ ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib; ++ ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib; ++}ATOM_ENCODER_ATTRIBUTE; + +-typedef union _ATOM_ENCODER_ATTRIBUTE { +- ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib; +- ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib; +-} ATOM_ENCODER_ATTRIBUTE; + +-typedef struct _DVO_ENCODER_CONTROL_PARAMETERS { +- USHORT usPixelClock; +- USHORT usEncoderID; +- UCHAR ucDeviceType; /* Use ATOM_DEVICE_xxx1_Index to indicate device type only. */ +- UCHAR ucAction; /* ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT */ +- ATOM_ENCODER_ATTRIBUTE usDevAttr; +-} DVO_ENCODER_CONTROL_PARAMETERS; ++typedef struct _DVO_ENCODER_CONTROL_PARAMETERS ++{ ++ USHORT usPixelClock; ++ USHORT usEncoderID; ++ UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. ++ UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT ++ ATOM_ENCODER_ATTRIBUTE usDevAttr; ++}DVO_ENCODER_CONTROL_PARAMETERS; ++ ++typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION ++{ ++ DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; ++ WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion ++}DVO_ENCODER_CONTROL_PS_ALLOCATION; + +-typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION { +- DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; +- WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; /* Caller doesn't need to init this portion */ +-} DVO_ENCODER_CONTROL_PS_ALLOCATION; + + #define ATOM_XTMDS_ASIC_SI164_ID 1 + #define ATOM_XTMDS_ASIC_SI178_ID 2 +@@ -4526,27 +5539,30 @@ typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION { + #define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002 + #define ATOM_XTMDS_MVPU_FPGA 0x00000004 + +-typedef struct _ATOM_XTMDS_INFO { +- ATOM_COMMON_TABLE_HEADER sHeader; +- USHORT usSingleLinkMaxFrequency; +- ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; /* Point the ID on which I2C is used to control external chip */ +- UCHAR ucXtransimitterID; +- UCHAR ucSupportedLink; /* Bit field, bit0=1, single link supported;bit1=1,dual link supported */ +- UCHAR ucSequnceAlterID; /* Even with the same external TMDS asic, it's possible that the program seqence alters */ +- /* due to design. This ID is used to alert driver that the sequence is not "standard"! */ +- UCHAR ucMasterAddress; /* Address to control Master xTMDS Chip */ +- UCHAR ucSlaveAddress; /* Address to control Slave xTMDS Chip */ +-} ATOM_XTMDS_INFO; +- +-typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS { +- UCHAR ucEnable; /* ATOM_ENABLE=On or ATOM_DISABLE=Off */ +- UCHAR ucDevice; /* ATOM_DEVICE_DFP1_INDEX.... */ +- UCHAR ucPadding[2]; +-} DFP_DPMS_STATUS_CHANGE_PARAMETERS; ++ ++typedef struct _ATOM_XTMDS_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ USHORT usSingleLinkMaxFrequency; ++ ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip ++ UCHAR ucXtransimitterID; ++ UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported ++ UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters ++ // due to design. This ID is used to alert driver that the sequence is not "standard"! ++ UCHAR ucMasterAddress; // Address to control Master xTMDS Chip ++ UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip ++}ATOM_XTMDS_INFO; ++ ++typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS ++{ ++ UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off ++ UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX.... ++ UCHAR ucPadding[2]; ++}DFP_DPMS_STATUS_CHANGE_PARAMETERS; + + /****************************Legacy Power Play Table Definitions **********************/ + +-/* Definitions for ulPowerPlayMiscInfo */ ++//Definitions for ulPowerPlayMiscInfo + #define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L + #define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L + #define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L +@@ -4558,8 +5574,8 @@ typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS { + + #define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L + #define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L +-#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L /* When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program */ +- ++#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program ++ + #define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L + #define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L + #define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L +@@ -4569,22 +5585,22 @@ typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS { + #define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L + + #define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L +-#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L ++#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L + #define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L + #define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L + #define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L + +-#define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L /* 0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved */ +-#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 ++#define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved ++#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 + + #define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L + #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L + #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L +-#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L /* When set, Dynamic */ +-#define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L /* When set, Dynamic */ +-#define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L /* When set, This mode is for acceleated 3D mode */ ++#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic ++#define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic ++#define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode + +-#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L /* 1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) */ ++#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) + #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 + #define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L + +@@ -4594,55 +5610,59 @@ typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS { + #define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L + #define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L + #define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L +-#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L /* If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. */ +- /* If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback */ ++#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. ++ //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback + #define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L + #define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L +-#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L +- +-/* ucTableFormatRevision=1 */ +-/* ucTableContentRevision=1 */ +-typedef struct _ATOM_POWERMODE_INFO { +- ULONG ulMiscInfo; /* The power level should be arranged in ascending order */ +- ULONG ulReserved1; /* must set to 0 */ +- ULONG ulReserved2; /* must set to 0 */ +- USHORT usEngineClock; +- USHORT usMemoryClock; +- UCHAR ucVoltageDropIndex; /* index to GPIO table */ +- UCHAR ucSelectedPanel_RefreshRate; /* panel refresh rate */ +- UCHAR ucMinTemperature; +- UCHAR ucMaxTemperature; +- UCHAR ucNumPciELanes; /* number of PCIE lanes */ +-} ATOM_POWERMODE_INFO; +- +-/* ucTableFormatRevision=2 */ +-/* ucTableContentRevision=1 */ +-typedef struct _ATOM_POWERMODE_INFO_V2 { +- ULONG ulMiscInfo; /* The power level should be arranged in ascending order */ +- ULONG ulMiscInfo2; +- ULONG ulEngineClock; +- ULONG ulMemoryClock; +- UCHAR ucVoltageDropIndex; /* index to GPIO table */ +- UCHAR ucSelectedPanel_RefreshRate; /* panel refresh rate */ +- UCHAR ucMinTemperature; +- UCHAR ucMaxTemperature; +- UCHAR ucNumPciELanes; /* number of PCIE lanes */ +-} ATOM_POWERMODE_INFO_V2; +- +-/* ucTableFormatRevision=2 */ +-/* ucTableContentRevision=2 */ +-typedef struct _ATOM_POWERMODE_INFO_V3 { +- ULONG ulMiscInfo; /* The power level should be arranged in ascending order */ +- ULONG ulMiscInfo2; +- ULONG ulEngineClock; +- ULONG ulMemoryClock; +- UCHAR ucVoltageDropIndex; /* index to Core (VDDC) votage table */ +- UCHAR ucSelectedPanel_RefreshRate; /* panel refresh rate */ +- UCHAR ucMinTemperature; +- UCHAR ucMaxTemperature; +- UCHAR ucNumPciELanes; /* number of PCIE lanes */ +- UCHAR ucVDDCI_VoltageDropIndex; /* index to VDDCI votage table */ +-} ATOM_POWERMODE_INFO_V3; ++#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L ++ ++//ucTableFormatRevision=1 ++//ucTableContentRevision=1 ++typedef struct _ATOM_POWERMODE_INFO ++{ ++ ULONG ulMiscInfo; //The power level should be arranged in ascending order ++ ULONG ulReserved1; // must set to 0 ++ ULONG ulReserved2; // must set to 0 ++ USHORT usEngineClock; ++ USHORT usMemoryClock; ++ UCHAR ucVoltageDropIndex; // index to GPIO table ++ UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate ++ UCHAR ucMinTemperature; ++ UCHAR ucMaxTemperature; ++ UCHAR ucNumPciELanes; // number of PCIE lanes ++}ATOM_POWERMODE_INFO; ++ ++//ucTableFormatRevision=2 ++//ucTableContentRevision=1 ++typedef struct _ATOM_POWERMODE_INFO_V2 ++{ ++ ULONG ulMiscInfo; //The power level should be arranged in ascending order ++ ULONG ulMiscInfo2; ++ ULONG ulEngineClock; ++ ULONG ulMemoryClock; ++ UCHAR ucVoltageDropIndex; // index to GPIO table ++ UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate ++ UCHAR ucMinTemperature; ++ UCHAR ucMaxTemperature; ++ UCHAR ucNumPciELanes; // number of PCIE lanes ++}ATOM_POWERMODE_INFO_V2; ++ ++//ucTableFormatRevision=2 ++//ucTableContentRevision=2 ++typedef struct _ATOM_POWERMODE_INFO_V3 ++{ ++ ULONG ulMiscInfo; //The power level should be arranged in ascending order ++ ULONG ulMiscInfo2; ++ ULONG ulEngineClock; ++ ULONG ulMemoryClock; ++ UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table ++ UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate ++ UCHAR ucMinTemperature; ++ UCHAR ucMaxTemperature; ++ UCHAR ucNumPciELanes; // number of PCIE lanes ++ UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table ++}ATOM_POWERMODE_INFO_V3; ++ + + #define ATOM_MAX_NUMBEROF_POWER_BLOCK 8 + +@@ -4655,40 +5675,44 @@ typedef struct _ATOM_POWERMODE_INFO_V3 { + #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04 + #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05 + #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06 +-#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 /* Andigilog */ +- +-typedef struct _ATOM_POWERPLAY_INFO { +- ATOM_COMMON_TABLE_HEADER sHeader; +- UCHAR ucOverdriveThermalController; +- UCHAR ucOverdriveI2cLine; +- UCHAR ucOverdriveIntBitmap; +- UCHAR ucOverdriveControllerAddress; +- UCHAR ucSizeOfPowerModeEntry; +- UCHAR ucNumOfPowerModeEntries; +- ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; +-} ATOM_POWERPLAY_INFO; +- +-typedef struct _ATOM_POWERPLAY_INFO_V2 { +- ATOM_COMMON_TABLE_HEADER sHeader; +- UCHAR ucOverdriveThermalController; +- UCHAR ucOverdriveI2cLine; +- UCHAR ucOverdriveIntBitmap; +- UCHAR ucOverdriveControllerAddress; +- UCHAR ucSizeOfPowerModeEntry; +- UCHAR ucNumOfPowerModeEntries; +- ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; +-} ATOM_POWERPLAY_INFO_V2; +- +-typedef struct _ATOM_POWERPLAY_INFO_V3 { +- ATOM_COMMON_TABLE_HEADER sHeader; +- UCHAR ucOverdriveThermalController; +- UCHAR ucOverdriveI2cLine; +- UCHAR ucOverdriveIntBitmap; +- UCHAR ucOverdriveControllerAddress; +- UCHAR ucSizeOfPowerModeEntry; +- UCHAR ucNumOfPowerModeEntries; +- ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; +-} ATOM_POWERPLAY_INFO_V3; ++#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog ++ ++ ++typedef struct _ATOM_POWERPLAY_INFO ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ UCHAR ucOverdriveThermalController; ++ UCHAR ucOverdriveI2cLine; ++ UCHAR ucOverdriveIntBitmap; ++ UCHAR ucOverdriveControllerAddress; ++ UCHAR ucSizeOfPowerModeEntry; ++ UCHAR ucNumOfPowerModeEntries; ++ ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; ++}ATOM_POWERPLAY_INFO; ++ ++typedef struct _ATOM_POWERPLAY_INFO_V2 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ UCHAR ucOverdriveThermalController; ++ UCHAR ucOverdriveI2cLine; ++ UCHAR ucOverdriveIntBitmap; ++ UCHAR ucOverdriveControllerAddress; ++ UCHAR ucSizeOfPowerModeEntry; ++ UCHAR ucNumOfPowerModeEntries; ++ ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; ++}ATOM_POWERPLAY_INFO_V2; ++ ++typedef struct _ATOM_POWERPLAY_INFO_V3 ++{ ++ ATOM_COMMON_TABLE_HEADER sHeader; ++ UCHAR ucOverdriveThermalController; ++ UCHAR ucOverdriveI2cLine; ++ UCHAR ucOverdriveIntBitmap; ++ UCHAR ucOverdriveControllerAddress; ++ UCHAR ucSizeOfPowerModeEntry; ++ UCHAR ucNumOfPowerModeEntries; ++ ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; ++}ATOM_POWERPLAY_INFO_V3; + + /* New PPlib */ + /**************************************************************************/ +@@ -4873,40 +5897,42 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO + UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16} + UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could be bigger as display BW requriement. + USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200). +- ULONG ulFlags; ++ ULONG ulFlags; + } ATOM_PPLIB_RS780_CLOCK_INFO; + +-#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0 +-#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1 +-#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2 +-#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3 ++#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0 ++#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1 ++#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2 ++#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3 + + #define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is. + #define ATOM_PPLIB_RS780_SPMCLK_LOW 1 + #define ATOM_PPLIB_RS780_SPMCLK_HIGH 2 + +-#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0 +-#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 +-#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 ++#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0 ++#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 ++#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 + + /**************************************************************************/ + +-/* Following definitions are for compatiblity issue in different SW components. */ ++ ++// Following definitions are for compatiblity issue in different SW components. + #define ATOM_MASTER_DATA_TABLE_REVISION 0x01 +-#define Object_Info Object_Header ++#define Object_Info Object_Header + #define AdjustARB_SEQ MC_InitParameter + #define VRAM_GPIO_DetectionInfo VoltageObjectInfo +-#define ASIC_VDDCI_Info ASIC_ProfilingInfo ++#define ASIC_VDDCI_Info ASIC_ProfilingInfo + #define ASIC_MVDDQ_Info MemoryTrainingInfo +-#define SS_Info PPLL_SS_Info ++#define SS_Info PPLL_SS_Info + #define ASIC_MVDDC_Info ASIC_InternalSS_Info + #define DispDevicePriorityInfo SaveRestoreInfo + #define DispOutInfo TV_VideoMode + ++ + #define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE + #define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE + +-/* New device naming, remove them when both DAL/VBIOS is ready */ ++//New device naming, remove them when both DAL/VBIOS is ready + #define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS + #define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS + +@@ -4921,7 +5947,7 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO + + #define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX + #define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX +- ++ + #define ATOM_DEVICE_DFP2I_INDEX 0x00000009 + #define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX) + +@@ -4939,7 +5965,7 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO + + #define ATOM_S3_DFP2I_ACTIVEb1 0x02 + +-#define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE ++#define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE + #define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE + + #define ATOM_S3_DFP2I_ACTIVE 0x00000200L +@@ -4958,14 +5984,14 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO + #define ATOM_S6_ACC_REQ_DFP2Ib3 0x02 + #define ATOM_S6_ACC_REQ_DFP2I 0x02000000L + +-#define TMDS1XEncoderControl DVOEncoderControl ++#define TMDS1XEncoderControl DVOEncoderControl + #define DFP1XOutputControl DVOOutputControl + + #define ExternalDFPOutputControl DFP1XOutputControl + #define EnableExternalTMDS_Encoder TMDS1XEncoderControl + + #define DFP1IOutputControl TMDSAOutputControl +-#define DFP2IOutputControl LVTMAOutputControl ++#define DFP2IOutputControl LVTMAOutputControl + + #define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS + #define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION +@@ -4974,7 +6000,7 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO + #define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION + + #define ucDac1Standard ucDacStandard +-#define ucDac2Standard ucDacStandard ++#define ucDac2Standard ucDacStandard + + #define TMDS1EncoderControl TMDSAEncoderControl + #define TMDS2EncoderControl LVTMAEncoderControl +@@ -4984,12 +6010,56 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO + #define CRT1OutputControl DAC1OutputControl + #define CRT2OutputControl DAC2OutputControl + +-/* These two lines will be removed for sure in a few days, will follow up with Michael V. */ ++//These two lines will be removed for sure in a few days, will follow up with Michael V. + #define EnableLVDS_SS EnableSpreadSpectrumOnPPLL +-#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL ++#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL ++ ++//#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L ++//#define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE ++//#define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE ++//#define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE ++//#define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE ++ ++#define ATOM_S6_ACC_REQ_TV2 0x00400000L ++#define ATOM_DEVICE_TV2_INDEX 0x00000006 ++#define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX) ++#define ATOM_S0_TV2 0x00100000L ++#define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE ++#define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE ++ ++// ++#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L ++#define ATOM_S2_LCD1_DPMS_STATE 0x00020000L ++#define ATOM_S2_TV1_DPMS_STATE 0x00040000L ++#define ATOM_S2_DFP1_DPMS_STATE 0x00080000L ++#define ATOM_S2_CRT2_DPMS_STATE 0x00100000L ++#define ATOM_S2_LCD2_DPMS_STATE 0x00200000L ++#define ATOM_S2_TV2_DPMS_STATE 0x00400000L ++#define ATOM_S2_DFP2_DPMS_STATE 0x00800000L ++#define ATOM_S2_CV_DPMS_STATE 0x01000000L ++#define ATOM_S2_DFP3_DPMS_STATE 0x02000000L ++#define ATOM_S2_DFP4_DPMS_STATE 0x04000000L ++#define ATOM_S2_DFP5_DPMS_STATE 0x08000000L ++ ++#define ATOM_S2_CRT1_DPMS_STATEb2 0x01 ++#define ATOM_S2_LCD1_DPMS_STATEb2 0x02 ++#define ATOM_S2_TV1_DPMS_STATEb2 0x04 ++#define ATOM_S2_DFP1_DPMS_STATEb2 0x08 ++#define ATOM_S2_CRT2_DPMS_STATEb2 0x10 ++#define ATOM_S2_LCD2_DPMS_STATEb2 0x20 ++#define ATOM_S2_TV2_DPMS_STATEb2 0x40 ++#define ATOM_S2_DFP2_DPMS_STATEb2 0x80 ++#define ATOM_S2_CV_DPMS_STATEb3 0x01 ++#define ATOM_S2_DFP3_DPMS_STATEb3 0x02 ++#define ATOM_S2_DFP4_DPMS_STATEb3 0x04 ++#define ATOM_S2_DFP5_DPMS_STATEb3 0x08 ++ ++#define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20 ++#define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40 ++#define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80 + + /*********************************************************************************/ + +-#pragma pack() /* BIOS data must use byte aligment */ ++#pragma pack() // BIOS data must use byte aligment + + #endif /* _ATOMBIOS_H */ +diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c +index af464e3..c076eac 100644 +--- a/drivers/gpu/drm/radeon/atombios_crtc.c ++++ b/drivers/gpu/drm/radeon/atombios_crtc.c +@@ -245,21 +245,25 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) + + switch (mode) { + case DRM_MODE_DPMS_ON: +- atombios_enable_crtc(crtc, 1); ++ atombios_enable_crtc(crtc, ATOM_ENABLE); + if (ASIC_IS_DCE3(rdev)) +- atombios_enable_crtc_memreq(crtc, 1); +- atombios_blank_crtc(crtc, 0); +- drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); ++ atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); ++ atombios_blank_crtc(crtc, ATOM_DISABLE); ++ /* XXX re-enable when interrupt support is added */ ++ if (!ASIC_IS_DCE4(rdev)) ++ drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); + radeon_crtc_load_lut(crtc); + break; + case DRM_MODE_DPMS_STANDBY: + case DRM_MODE_DPMS_SUSPEND: + case DRM_MODE_DPMS_OFF: +- drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); +- atombios_blank_crtc(crtc, 1); ++ /* XXX re-enable when interrupt support is added */ ++ if (!ASIC_IS_DCE4(rdev)) ++ drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); ++ atombios_blank_crtc(crtc, ATOM_ENABLE); + if (ASIC_IS_DCE3(rdev)) +- atombios_enable_crtc_memreq(crtc, 0); +- atombios_enable_crtc(crtc, 0); ++ atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); ++ atombios_enable_crtc(crtc, ATOM_DISABLE); + break; + } + } +@@ -363,6 +367,10 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable) + uint16_t percentage = 0; + uint8_t type = 0, step = 0, delay = 0, range = 0; + ++ /* XXX add ss support for DCE4 */ ++ if (ASIC_IS_DCE4(rdev)) ++ return; ++ + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + if (encoder->crtc == crtc) { + radeon_encoder = to_radeon_encoder(encoder); +@@ -409,6 +417,7 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable) + + union adjust_pixel_clock { + ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; ++ ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; + }; + + static u32 atombios_adjust_pll(struct drm_crtc *crtc, +@@ -420,6 +429,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, + struct drm_encoder *encoder = NULL; + struct radeon_encoder *radeon_encoder = NULL; + u32 adjusted_clock = mode->clock; ++ int encoder_mode = 0; + + /* reset the pll flags */ + pll->flags = 0; +@@ -448,6 +458,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + if (encoder->crtc == crtc) { + radeon_encoder = to_radeon_encoder(encoder); ++ encoder_mode = atombios_get_encoder_mode(encoder); + if (ASIC_IS_AVIVO(rdev)) { + /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ + if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) +@@ -468,14 +479,9 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, + */ + if (ASIC_IS_DCE3(rdev)) { + union adjust_pixel_clock args; +- struct radeon_encoder_atom_dig *dig; + u8 frev, crev; + int index; + +- if (!radeon_encoder->enc_priv) +- return adjusted_clock; +- dig = radeon_encoder->enc_priv; +- + index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); + atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, + &crev); +@@ -489,12 +495,56 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, + case 2: + args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); + args.v1.ucTransmitterID = radeon_encoder->encoder_id; +- args.v1.ucEncodeMode = atombios_get_encoder_mode(encoder); ++ args.v1.ucEncodeMode = encoder_mode; + + atom_execute_table(rdev->mode_info.atom_context, + index, (uint32_t *)&args); + adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; + break; ++ case 3: ++ args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10); ++ args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; ++ args.v3.sInput.ucEncodeMode = encoder_mode; ++ args.v3.sInput.ucDispPllConfig = 0; ++ if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { ++ struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; ++ ++ if (encoder_mode == ATOM_ENCODER_MODE_DP) ++ args.v3.sInput.ucDispPllConfig |= ++ DISPPLL_CONFIG_COHERENT_MODE; ++ else { ++ if (dig->coherent_mode) ++ args.v3.sInput.ucDispPllConfig |= ++ DISPPLL_CONFIG_COHERENT_MODE; ++ if (mode->clock > 165000) ++ args.v3.sInput.ucDispPllConfig |= ++ DISPPLL_CONFIG_DUAL_LINK; ++ } ++ } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { ++ /* may want to enable SS on DP/eDP eventually */ ++ /*args.v3.sInput.ucDispPllConfig |= ++ DISPPLL_CONFIG_SS_ENABLE;*/ ++ if (encoder_mode == ATOM_ENCODER_MODE_DP) ++ args.v3.sInput.ucDispPllConfig |= ++ DISPPLL_CONFIG_COHERENT_MODE; ++ else { ++ if (mode->clock > 165000) ++ args.v3.sInput.ucDispPllConfig |= ++ DISPPLL_CONFIG_DUAL_LINK; ++ } ++ } ++ atom_execute_table(rdev->mode_info.atom_context, ++ index, (uint32_t *)&args); ++ adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; ++ if (args.v3.sOutput.ucRefDiv) { ++ pll->flags |= RADEON_PLL_USE_REF_DIV; ++ pll->reference_div = args.v3.sOutput.ucRefDiv; ++ } ++ if (args.v3.sOutput.ucPostDiv) { ++ pll->flags |= RADEON_PLL_USE_POST_DIV; ++ pll->post_div = args.v3.sOutput.ucPostDiv; ++ } ++ break; + default: + DRM_ERROR("Unknown table version %d %d\n", frev, crev); + return adjusted_clock; +@@ -513,9 +563,47 @@ union set_pixel_clock { + PIXEL_CLOCK_PARAMETERS v1; + PIXEL_CLOCK_PARAMETERS_V2 v2; + PIXEL_CLOCK_PARAMETERS_V3 v3; ++ PIXEL_CLOCK_PARAMETERS_V5 v5; + }; + +-void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) ++static void atombios_crtc_set_dcpll(struct drm_crtc *crtc) ++{ ++ struct drm_device *dev = crtc->dev; ++ struct radeon_device *rdev = dev->dev_private; ++ u8 frev, crev; ++ int index; ++ union set_pixel_clock args; ++ ++ memset(&args, 0, sizeof(args)); ++ ++ index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); ++ atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, ++ &crev); ++ ++ switch (frev) { ++ case 1: ++ switch (crev) { ++ case 5: ++ /* if the default dcpll clock is specified, ++ * SetPixelClock provides the dividers ++ */ ++ args.v5.ucCRTC = ATOM_CRTC_INVALID; ++ args.v5.usPixelClock = rdev->clock.default_dispclk; ++ args.v5.ucPpll = ATOM_DCPLL; ++ break; ++ default: ++ DRM_ERROR("Unknown table version %d %d\n", frev, crev); ++ return; ++ } ++ break; ++ default: ++ DRM_ERROR("Unknown table version %d %d\n", frev, crev); ++ return; ++ } ++ atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); ++} ++ ++static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) + { + struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); + struct drm_device *dev = crtc->dev; +@@ -529,12 +617,14 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) + u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; + struct radeon_pll *pll; + u32 adjusted_clock; ++ int encoder_mode = 0; + + memset(&args, 0, sizeof(args)); + + list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + if (encoder->crtc == crtc) { + radeon_encoder = to_radeon_encoder(encoder); ++ encoder_mode = atombios_get_encoder_mode(encoder); + break; + } + } +@@ -542,10 +632,18 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) + if (!radeon_encoder) + return; + +- if (radeon_crtc->crtc_id == 0) ++ switch (radeon_crtc->pll_id) { ++ case ATOM_PPLL1: + pll = &rdev->clock.p1pll; +- else ++ break; ++ case ATOM_PPLL2: + pll = &rdev->clock.p2pll; ++ break; ++ case ATOM_DCPLL: ++ case ATOM_PPLL_INVALID: ++ pll = &rdev->clock.dcpll; ++ break; ++ } + + /* adjust pixel clock as needed */ + adjusted_clock = atombios_adjust_pll(crtc, mode, pll); +@@ -576,8 +674,7 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) + args.v1.usFbDiv = cpu_to_le16(fb_div); + args.v1.ucFracFbDiv = frac_fb_div; + args.v1.ucPostDiv = post_div; +- args.v1.ucPpll = +- radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; ++ args.v1.ucPpll = radeon_crtc->pll_id; + args.v1.ucCRTC = radeon_crtc->crtc_id; + args.v1.ucRefDivSrc = 1; + break; +@@ -587,8 +684,7 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) + args.v2.usFbDiv = cpu_to_le16(fb_div); + args.v2.ucFracFbDiv = frac_fb_div; + args.v2.ucPostDiv = post_div; +- args.v2.ucPpll = +- radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; ++ args.v2.ucPpll = radeon_crtc->pll_id; + args.v2.ucCRTC = radeon_crtc->crtc_id; + args.v2.ucRefDivSrc = 1; + break; +@@ -598,12 +694,22 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) + args.v3.usFbDiv = cpu_to_le16(fb_div); + args.v3.ucFracFbDiv = frac_fb_div; + args.v3.ucPostDiv = post_div; +- args.v3.ucPpll = +- radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; +- args.v3.ucMiscInfo = (radeon_crtc->crtc_id << 2); ++ args.v3.ucPpll = radeon_crtc->pll_id; ++ args.v3.ucMiscInfo = (radeon_crtc->pll_id << 2); + args.v3.ucTransmitterId = radeon_encoder->encoder_id; +- args.v3.ucEncoderMode = +- atombios_get_encoder_mode(encoder); ++ args.v3.ucEncoderMode = encoder_mode; ++ break; ++ case 5: ++ args.v5.ucCRTC = radeon_crtc->crtc_id; ++ args.v5.usPixelClock = cpu_to_le16(mode->clock / 10); ++ args.v5.ucRefDiv = ref_div; ++ args.v5.usFbDiv = cpu_to_le16(fb_div); ++ args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); ++ args.v5.ucPostDiv = post_div; ++ args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ ++ args.v5.ucTransmitterID = radeon_encoder->encoder_id; ++ args.v5.ucEncoderMode = encoder_mode; ++ args.v5.ucPpll = radeon_crtc->pll_id; + break; + default: + DRM_ERROR("Unknown table version %d %d\n", frev, crev); +@@ -618,6 +724,140 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) + atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); + } + ++static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y, ++ struct drm_framebuffer *old_fb) ++{ ++ struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); ++ struct drm_device *dev = crtc->dev; ++ struct radeon_device *rdev = dev->dev_private; ++ struct radeon_framebuffer *radeon_fb; ++ struct drm_gem_object *obj; ++ struct radeon_bo *rbo; ++ uint64_t fb_location; ++ uint32_t fb_format, fb_pitch_pixels, tiling_flags; ++ int r; ++ ++ /* no fb bound */ ++ if (!crtc->fb) { ++ DRM_DEBUG("No FB bound\n"); ++ return 0; ++ } ++ ++ radeon_fb = to_radeon_framebuffer(crtc->fb); ++ ++ /* Pin framebuffer & get tilling informations */ ++ obj = radeon_fb->obj; ++ rbo = obj->driver_private; ++ r = radeon_bo_reserve(rbo, false); ++ if (unlikely(r != 0)) ++ return r; ++ r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); ++ if (unlikely(r != 0)) { ++ radeon_bo_unreserve(rbo); ++ return -EINVAL; ++ } ++ radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); ++ radeon_bo_unreserve(rbo); ++ ++ switch (crtc->fb->bits_per_pixel) { ++ case 8: ++ fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | ++ EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); ++ break; ++ case 15: ++ fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | ++ EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); ++ break; ++ case 16: ++ fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | ++ EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); ++ break; ++ case 24: ++ case 32: ++ fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | ++ EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); ++ break; ++ default: ++ DRM_ERROR("Unsupported screen depth %d\n", ++ crtc->fb->bits_per_pixel); ++ return -EINVAL; ++ } ++ ++ switch (radeon_crtc->crtc_id) { ++ case 0: ++ WREG32(AVIVO_D1VGA_CONTROL, 0); ++ break; ++ case 1: ++ WREG32(AVIVO_D2VGA_CONTROL, 0); ++ break; ++ case 2: ++ WREG32(EVERGREEN_D3VGA_CONTROL, 0); ++ break; ++ case 3: ++ WREG32(EVERGREEN_D4VGA_CONTROL, 0); ++ break; ++ case 4: ++ WREG32(EVERGREEN_D5VGA_CONTROL, 0); ++ break; ++ case 5: ++ WREG32(EVERGREEN_D6VGA_CONTROL, 0); ++ break; ++ default: ++ break; ++ } ++ ++ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, ++ upper_32_bits(fb_location)); ++ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, ++ upper_32_bits(fb_location)); ++ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, ++ (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); ++ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, ++ (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); ++ WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); ++ ++ WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); ++ WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); ++ WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); ++ WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); ++ WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width); ++ WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height); ++ ++ fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8); ++ WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); ++ WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); ++ ++ WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, ++ crtc->mode.vdisplay); ++ x &= ~3; ++ y &= ~1; ++ WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, ++ (x << 16) | y); ++ WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, ++ (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); ++ ++ if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ++ WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, ++ EVERGREEN_INTERLEAVE_EN); ++ else ++ WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); ++ ++ if (old_fb && old_fb != crtc->fb) { ++ radeon_fb = to_radeon_framebuffer(old_fb); ++ rbo = radeon_fb->obj->driver_private; ++ r = radeon_bo_reserve(rbo, false); ++ if (unlikely(r != 0)) ++ return r; ++ radeon_bo_unpin(rbo); ++ radeon_bo_unreserve(rbo); ++ } ++ ++ /* Bytes per pixel may have changed */ ++ radeon_bandwidth_update(rdev); ++ ++ return 0; ++} ++ + static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y, + struct drm_framebuffer *old_fb) + { +@@ -755,7 +995,9 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, + struct drm_device *dev = crtc->dev; + struct radeon_device *rdev = dev->dev_private; + +- if (ASIC_IS_AVIVO(rdev)) ++ if (ASIC_IS_DCE4(rdev)) ++ return evergreen_crtc_set_base(crtc, x, y, old_fb); ++ else if (ASIC_IS_AVIVO(rdev)) + return avivo_crtc_set_base(crtc, x, y, old_fb); + else + return radeon_crtc_set_base(crtc, x, y, old_fb); +@@ -785,6 +1027,46 @@ static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) + } + } + ++static int radeon_atom_pick_pll(struct drm_crtc *crtc) ++{ ++ struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); ++ struct drm_device *dev = crtc->dev; ++ struct radeon_device *rdev = dev->dev_private; ++ struct drm_encoder *test_encoder; ++ struct drm_crtc *test_crtc; ++ uint32_t pll_in_use = 0; ++ ++ if (ASIC_IS_DCE4(rdev)) { ++ /* if crtc is driving DP and we have an ext clock, use that */ ++ list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { ++ if (test_encoder->crtc && (test_encoder->crtc == crtc)) { ++ if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) { ++ if (rdev->clock.dp_extclk) ++ return ATOM_PPLL_INVALID; ++ } ++ } ++ } ++ ++ /* otherwise, pick one of the plls */ ++ list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { ++ struct radeon_crtc *radeon_test_crtc; ++ ++ if (crtc == test_crtc) ++ continue; ++ ++ radeon_test_crtc = to_radeon_crtc(test_crtc); ++ if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) && ++ (radeon_test_crtc->pll_id <= ATOM_PPLL2)) ++ pll_in_use |= (1 << radeon_test_crtc->pll_id); ++ } ++ if (!(pll_in_use & 1)) ++ return ATOM_PPLL1; ++ return ATOM_PPLL2; ++ } else ++ return radeon_crtc->crtc_id; ++ ++} ++ + int atombios_crtc_mode_set(struct drm_crtc *crtc, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode, +@@ -796,19 +1078,27 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc, + + /* TODO color tiling */ + ++ /* pick pll */ ++ radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); ++ + atombios_set_ss(crtc, 0); ++ /* always set DCPLL */ ++ if (ASIC_IS_DCE4(rdev)) ++ atombios_crtc_set_dcpll(crtc); + atombios_crtc_set_pll(crtc, adjusted_mode); + atombios_set_ss(crtc, 1); +- atombios_crtc_set_timing(crtc, adjusted_mode); + +- if (ASIC_IS_AVIVO(rdev)) +- atombios_crtc_set_base(crtc, x, y, old_fb); ++ if (ASIC_IS_DCE4(rdev)) ++ atombios_set_crtc_dtd_timing(crtc, adjusted_mode); ++ else if (ASIC_IS_AVIVO(rdev)) ++ atombios_crtc_set_timing(crtc, adjusted_mode); + else { ++ atombios_crtc_set_timing(crtc, adjusted_mode); + if (radeon_crtc->crtc_id == 0) + atombios_set_crtc_dtd_timing(crtc, adjusted_mode); +- atombios_crtc_set_base(crtc, x, y, old_fb); + radeon_legacy_atom_fixup(crtc); + } ++ atombios_crtc_set_base(crtc, x, y, old_fb); + atombios_overscan_setup(crtc, mode, adjusted_mode); + atombios_scaler_setup(crtc); + return 0; +@@ -825,14 +1115,14 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, + + static void atombios_crtc_prepare(struct drm_crtc *crtc) + { +- atombios_lock_crtc(crtc, 1); ++ atombios_lock_crtc(crtc, ATOM_ENABLE); + atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); + } + + static void atombios_crtc_commit(struct drm_crtc *crtc) + { + atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); +- atombios_lock_crtc(crtc, 0); ++ atombios_lock_crtc(crtc, ATOM_DISABLE); + } + + static const struct drm_crtc_helper_funcs atombios_helper_funcs = { +@@ -848,8 +1138,37 @@ static const struct drm_crtc_helper_funcs atombios_helper_funcs = { + void radeon_atombios_init_crtc(struct drm_device *dev, + struct radeon_crtc *radeon_crtc) + { +- if (radeon_crtc->crtc_id == 1) +- radeon_crtc->crtc_offset = +- AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; ++ struct radeon_device *rdev = dev->dev_private; ++ ++ if (ASIC_IS_DCE4(rdev)) { ++ switch (radeon_crtc->crtc_id) { ++ case 0: ++ default: ++ radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; ++ break; ++ case 1: ++ radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; ++ break; ++ case 2: ++ radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; ++ break; ++ case 3: ++ radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; ++ break; ++ case 4: ++ radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; ++ break; ++ case 5: ++ radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; ++ break; ++ } ++ } else { ++ if (radeon_crtc->crtc_id == 1) ++ radeon_crtc->crtc_offset = ++ AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; ++ else ++ radeon_crtc->crtc_offset = 0; ++ } ++ radeon_crtc->pll_id = -1; + drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); + } +diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c +index 99915a6..28b31c6 100644 +--- a/drivers/gpu/drm/radeon/atombios_dp.c ++++ b/drivers/gpu/drm/radeon/atombios_dp.c +@@ -321,6 +321,10 @@ static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], + train_set[lane] = v | p; + } + ++union aux_channel_transaction { ++ PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; ++ PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; ++}; + + /* radeon aux chan functions */ + bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes, +@@ -329,7 +333,7 @@ bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes, + { + struct drm_device *dev = chan->dev; + struct radeon_device *rdev = dev->dev_private; +- PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION args; ++ union aux_channel_transaction args; + int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); + unsigned char *base; + int retry_count = 0; +@@ -341,31 +345,33 @@ bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes, + retry: + memcpy(base, req_bytes, num_bytes); + +- args.lpAuxRequest = 0; +- args.lpDataOut = 16; +- args.ucDataOutLen = 0; +- args.ucChannelID = chan->rec.i2c_id; +- args.ucDelay = delay / 10; ++ args.v1.lpAuxRequest = 0; ++ args.v1.lpDataOut = 16; ++ args.v1.ucDataOutLen = 0; ++ args.v1.ucChannelID = chan->rec.i2c_id; ++ args.v1.ucDelay = delay / 10; ++ if (ASIC_IS_DCE4(rdev)) ++ args.v2.ucHPD_ID = chan->rec.hpd_id; + + atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); + +- if (args.ucReplyStatus && !args.ucDataOutLen) { +- if (args.ucReplyStatus == 0x20 && retry_count++ < 10) ++ if (args.v1.ucReplyStatus && !args.v1.ucDataOutLen) { ++ if (args.v1.ucReplyStatus == 0x20 && retry_count++ < 10) + goto retry; + DRM_DEBUG("failed to get auxch %02x%02x %02x %02x 0x%02x %02x after %d retries\n", + req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3], +- chan->rec.i2c_id, args.ucReplyStatus, retry_count); ++ chan->rec.i2c_id, args.v1.ucReplyStatus, retry_count); + return false; + } + +- if (args.ucDataOutLen && read_byte && read_buf_len) { +- if (read_buf_len < args.ucDataOutLen) { ++ if (args.v1.ucDataOutLen && read_byte && read_buf_len) { ++ if (read_buf_len < args.v1.ucDataOutLen) { + DRM_ERROR("Buffer to small for return answer %d %d\n", +- read_buf_len, args.ucDataOutLen); ++ read_buf_len, args.v1.ucDataOutLen); + return false; + } + { +- int len = min(read_buf_len, args.ucDataOutLen); ++ int len = min(read_buf_len, args.v1.ucDataOutLen); + memcpy(read_byte, base + 16, len); + } + } +@@ -626,12 +632,19 @@ void dp_link_train(struct drm_encoder *encoder, + dp_set_link_bw_lanes(radeon_connector, link_configuration); + /* disable downspread on the sink */ + dp_set_downspread(radeon_connector, 0); +- /* start training on the source */ +- radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_START, +- dig_connector->dp_clock, enc_id, 0); +- /* set training pattern 1 on the source */ +- radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, +- dig_connector->dp_clock, enc_id, 0); ++ if (ASIC_IS_DCE4(rdev)) { ++ /* start training on the source */ ++ atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_START); ++ /* set training pattern 1 on the source */ ++ atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1); ++ } else { ++ /* start training on the source */ ++ radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_START, ++ dig_connector->dp_clock, enc_id, 0); ++ /* set training pattern 1 on the source */ ++ radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, ++ dig_connector->dp_clock, enc_id, 0); ++ } + + /* set initial vs/emph */ + memset(train_set, 0, 4); +@@ -691,8 +704,11 @@ void dp_link_train(struct drm_encoder *encoder, + /* set training pattern 2 on the sink */ + dp_set_training(radeon_connector, DP_TRAINING_PATTERN_2); + /* set training pattern 2 on the source */ +- radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, +- dig_connector->dp_clock, enc_id, 1); ++ if (ASIC_IS_DCE4(rdev)) ++ atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2); ++ else ++ radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, ++ dig_connector->dp_clock, enc_id, 1); + + /* channel equalization loop */ + tries = 0; +@@ -731,8 +747,12 @@ void dp_link_train(struct drm_encoder *encoder, + /* disable the training pattern on the sink */ + dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE); + +- radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, +- dig_connector->dp_clock, enc_id, 0); ++ /* disable the training pattern on the source */ ++ if (ASIC_IS_DCE4(rdev)) ++ atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE); ++ else ++ radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, ++ dig_connector->dp_clock, enc_id, 0); + } + + int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, +diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c +new file mode 100644 +index 0000000..c2f9752 +--- /dev/null ++++ b/drivers/gpu/drm/radeon/evergreen.c +@@ -0,0 +1,794 @@ ++/* ++ * Copyright 2010 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: Alex Deucher ++ */ ++#include ++#include ++#include "drmP.h" ++#include "radeon.h" ++#include "radeon_drm.h" ++#include "rv770d.h" ++#include "atom.h" ++#include "avivod.h" ++#include "evergreen_reg.h" ++ ++static void evergreen_gpu_init(struct radeon_device *rdev); ++void evergreen_fini(struct radeon_device *rdev); ++ ++bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) ++{ ++ bool connected = false; ++ /* XXX */ ++ return connected; ++} ++ ++void evergreen_hpd_set_polarity(struct radeon_device *rdev, ++ enum radeon_hpd_id hpd) ++{ ++ /* XXX */ ++} ++ ++void evergreen_hpd_init(struct radeon_device *rdev) ++{ ++ /* XXX */ ++} ++ ++ ++void evergreen_bandwidth_update(struct radeon_device *rdev) ++{ ++ /* XXX */ ++} ++ ++void evergreen_hpd_fini(struct radeon_device *rdev) ++{ ++ /* XXX */ ++} ++ ++static int evergreen_mc_wait_for_idle(struct radeon_device *rdev) ++{ ++ unsigned i; ++ u32 tmp; ++ ++ for (i = 0; i < rdev->usec_timeout; i++) { ++ /* read MC_STATUS */ ++ tmp = RREG32(SRBM_STATUS) & 0x1F00; ++ if (!tmp) ++ return 0; ++ udelay(1); ++ } ++ return -1; ++} ++ ++/* ++ * GART ++ */ ++int evergreen_pcie_gart_enable(struct radeon_device *rdev) ++{ ++ u32 tmp; ++ int r, i; ++ ++ if (rdev->gart.table.vram.robj == NULL) { ++ dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); ++ return -EINVAL; ++ } ++ r = radeon_gart_table_vram_pin(rdev); ++ if (r) ++ return r; ++ /* Setup L2 cache */ ++ WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | ++ ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | ++ EFFECTIVE_L2_QUEUE_SIZE(7)); ++ WREG32(VM_L2_CNTL2, 0); ++ WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); ++ /* Setup TLB control */ ++ tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | ++ SYSTEM_ACCESS_MODE_NOT_IN_SYS | ++ SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | ++ EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); ++ WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); ++ WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); ++ WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); ++ WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); ++ WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); ++ WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); ++ WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); ++ WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); ++ WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); ++ WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); ++ WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | ++ RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); ++ WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, ++ (u32)(rdev->dummy_page.addr >> 12)); ++ for (i = 1; i < 7; i++) ++ WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); ++ ++ r600_pcie_gart_tlb_flush(rdev); ++ rdev->gart.ready = true; ++ return 0; ++} ++ ++void evergreen_pcie_gart_disable(struct radeon_device *rdev) ++{ ++ u32 tmp; ++ int i, r; ++ ++ /* Disable all tables */ ++ for (i = 0; i < 7; i++) ++ WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); ++ ++ /* Setup L2 cache */ ++ WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | ++ EFFECTIVE_L2_QUEUE_SIZE(7)); ++ WREG32(VM_L2_CNTL2, 0); ++ WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); ++ /* Setup TLB control */ ++ tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); ++ WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); ++ WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); ++ WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); ++ WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); ++ WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); ++ WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); ++ WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); ++ if (rdev->gart.table.vram.robj) { ++ r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); ++ if (likely(r == 0)) { ++ radeon_bo_kunmap(rdev->gart.table.vram.robj); ++ radeon_bo_unpin(rdev->gart.table.vram.robj); ++ radeon_bo_unreserve(rdev->gart.table.vram.robj); ++ } ++ } ++} ++ ++void evergreen_pcie_gart_fini(struct radeon_device *rdev) ++{ ++ evergreen_pcie_gart_disable(rdev); ++ radeon_gart_table_vram_free(rdev); ++ radeon_gart_fini(rdev); ++} ++ ++ ++void evergreen_agp_enable(struct radeon_device *rdev) ++{ ++ u32 tmp; ++ int i; ++ ++ /* Setup L2 cache */ ++ WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | ++ ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | ++ EFFECTIVE_L2_QUEUE_SIZE(7)); ++ WREG32(VM_L2_CNTL2, 0); ++ WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); ++ /* Setup TLB control */ ++ tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | ++ SYSTEM_ACCESS_MODE_NOT_IN_SYS | ++ SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | ++ EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); ++ WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); ++ WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); ++ WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); ++ WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); ++ WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); ++ WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); ++ WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); ++ for (i = 0; i < 7; i++) ++ WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); ++} ++ ++static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save) ++{ ++ save->vga_control[0] = RREG32(D1VGA_CONTROL); ++ save->vga_control[1] = RREG32(D2VGA_CONTROL); ++ save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL); ++ save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL); ++ save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL); ++ save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL); ++ save->vga_render_control = RREG32(VGA_RENDER_CONTROL); ++ save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); ++ save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); ++ save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); ++ save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); ++ save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); ++ save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); ++ save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); ++ ++ /* Stop all video */ ++ WREG32(VGA_RENDER_CONTROL, 0); ++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); ++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); ++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); ++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); ++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); ++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); ++ WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); ++ WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); ++ WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); ++ WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); ++ WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); ++ WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); ++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); ++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); ++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); ++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); ++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); ++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); ++ ++ WREG32(D1VGA_CONTROL, 0); ++ WREG32(D2VGA_CONTROL, 0); ++ WREG32(EVERGREEN_D3VGA_CONTROL, 0); ++ WREG32(EVERGREEN_D4VGA_CONTROL, 0); ++ WREG32(EVERGREEN_D5VGA_CONTROL, 0); ++ WREG32(EVERGREEN_D6VGA_CONTROL, 0); ++} ++ ++static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save) ++{ ++ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET, ++ upper_32_bits(rdev->mc.vram_start)); ++ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET, ++ upper_32_bits(rdev->mc.vram_start)); ++ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET, ++ (u32)rdev->mc.vram_start); ++ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET, ++ (u32)rdev->mc.vram_start); ++ ++ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET, ++ upper_32_bits(rdev->mc.vram_start)); ++ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET, ++ upper_32_bits(rdev->mc.vram_start)); ++ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, ++ (u32)rdev->mc.vram_start); ++ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, ++ (u32)rdev->mc.vram_start); ++ ++ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, ++ upper_32_bits(rdev->mc.vram_start)); ++ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, ++ upper_32_bits(rdev->mc.vram_start)); ++ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET, ++ (u32)rdev->mc.vram_start); ++ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET, ++ (u32)rdev->mc.vram_start); ++ ++ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET, ++ upper_32_bits(rdev->mc.vram_start)); ++ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET, ++ upper_32_bits(rdev->mc.vram_start)); ++ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, ++ (u32)rdev->mc.vram_start); ++ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, ++ (u32)rdev->mc.vram_start); ++ ++ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, ++ upper_32_bits(rdev->mc.vram_start)); ++ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, ++ upper_32_bits(rdev->mc.vram_start)); ++ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET, ++ (u32)rdev->mc.vram_start); ++ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET, ++ (u32)rdev->mc.vram_start); ++ ++ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET, ++ upper_32_bits(rdev->mc.vram_start)); ++ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET, ++ upper_32_bits(rdev->mc.vram_start)); ++ WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET, ++ (u32)rdev->mc.vram_start); ++ WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET, ++ (u32)rdev->mc.vram_start); ++ ++ WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); ++ WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); ++ /* Unlock host access */ ++ WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); ++ mdelay(1); ++ /* Restore video state */ ++ WREG32(D1VGA_CONTROL, save->vga_control[0]); ++ WREG32(D2VGA_CONTROL, save->vga_control[1]); ++ WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]); ++ WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]); ++ WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]); ++ WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]); ++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); ++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); ++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); ++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); ++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); ++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); ++ WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]); ++ WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]); ++ WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]); ++ WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]); ++ WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]); ++ WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]); ++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); ++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); ++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); ++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); ++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); ++ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); ++ WREG32(VGA_RENDER_CONTROL, save->vga_render_control); ++} ++ ++static void evergreen_mc_program(struct radeon_device *rdev) ++{ ++ struct evergreen_mc_save save; ++ u32 tmp; ++ int i, j; ++ ++ /* Initialize HDP */ ++ for (i = 0, j = 0; i < 32; i++, j += 0x18) { ++ WREG32((0x2c14 + j), 0x00000000); ++ WREG32((0x2c18 + j), 0x00000000); ++ WREG32((0x2c1c + j), 0x00000000); ++ WREG32((0x2c20 + j), 0x00000000); ++ WREG32((0x2c24 + j), 0x00000000); ++ } ++ WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); ++ ++ evergreen_mc_stop(rdev, &save); ++ if (evergreen_mc_wait_for_idle(rdev)) { ++ dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); ++ } ++ /* Lockout access through VGA aperture*/ ++ WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); ++ /* Update configuration */ ++ if (rdev->flags & RADEON_IS_AGP) { ++ if (rdev->mc.vram_start < rdev->mc.gtt_start) { ++ /* VRAM before AGP */ ++ WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, ++ rdev->mc.vram_start >> 12); ++ WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, ++ rdev->mc.gtt_end >> 12); ++ } else { ++ /* VRAM after AGP */ ++ WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, ++ rdev->mc.gtt_start >> 12); ++ WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, ++ rdev->mc.vram_end >> 12); ++ } ++ } else { ++ WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, ++ rdev->mc.vram_start >> 12); ++ WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, ++ rdev->mc.vram_end >> 12); ++ } ++ WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); ++ tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; ++ tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); ++ WREG32(MC_VM_FB_LOCATION, tmp); ++ WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); ++ WREG32(HDP_NONSURFACE_INFO, (2 << 7)); ++ WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF); ++ if (rdev->flags & RADEON_IS_AGP) { ++ WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); ++ WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); ++ WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); ++ } else { ++ WREG32(MC_VM_AGP_BASE, 0); ++ WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); ++ WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); ++ } ++ if (evergreen_mc_wait_for_idle(rdev)) { ++ dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); ++ } ++ evergreen_mc_resume(rdev, &save); ++ /* we need to own VRAM, so turn off the VGA renderer here ++ * to stop it overwriting our objects */ ++ rv515_vga_render_disable(rdev); ++} ++ ++#if 0 ++/* ++ * CP. ++ */ ++static void evergreen_cp_stop(struct radeon_device *rdev) ++{ ++ /* XXX */ ++} ++ ++ ++static int evergreen_cp_load_microcode(struct radeon_device *rdev) ++{ ++ /* XXX */ ++ ++ return 0; ++} ++ ++ ++/* ++ * Core functions ++ */ ++static u32 evergreen_get_tile_pipe_to_backend_map(u32 num_tile_pipes, ++ u32 num_backends, ++ u32 backend_disable_mask) ++{ ++ u32 backend_map = 0; ++ ++ return backend_map; ++} ++#endif ++ ++static void evergreen_gpu_init(struct radeon_device *rdev) ++{ ++ /* XXX */ ++} ++ ++int evergreen_mc_init(struct radeon_device *rdev) ++{ ++ fixed20_12 a; ++ u32 tmp; ++ int chansize, numchan; ++ int r; ++ ++ /* Get VRAM informations */ ++ rdev->mc.vram_is_ddr = true; ++ tmp = RREG32(MC_ARB_RAMCFG); ++ if (tmp & CHANSIZE_OVERRIDE) { ++ chansize = 16; ++ } else if (tmp & CHANSIZE_MASK) { ++ chansize = 64; ++ } else { ++ chansize = 32; ++ } ++ tmp = RREG32(MC_SHARED_CHMAP); ++ switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { ++ case 0: ++ default: ++ numchan = 1; ++ break; ++ case 1: ++ numchan = 2; ++ break; ++ case 2: ++ numchan = 4; ++ break; ++ case 3: ++ numchan = 8; ++ break; ++ } ++ rdev->mc.vram_width = numchan * chansize; ++ /* Could aper size report 0 ? */ ++ rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); ++ rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); ++ /* Setup GPU memory space */ ++ /* size in MB on evergreen */ ++ rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; ++ rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; ++ ++ if (rdev->mc.mc_vram_size > rdev->mc.aper_size) ++ rdev->mc.mc_vram_size = rdev->mc.aper_size; ++ ++ if (rdev->mc.real_vram_size > rdev->mc.aper_size) ++ rdev->mc.real_vram_size = rdev->mc.aper_size; ++ ++ if (rdev->flags & RADEON_IS_AGP) { ++ r = radeon_agp_init(rdev); ++ if (r) ++ return r; ++ /* gtt_size is setup by radeon_agp_init */ ++ rdev->mc.gtt_location = rdev->mc.agp_base; ++ tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; ++ /* Try to put vram before or after AGP because we ++ * we want SYSTEM_APERTURE to cover both VRAM and ++ * AGP so that GPU can catch out of VRAM/AGP access ++ */ ++ if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) { ++ /* Enought place before */ ++ rdev->mc.vram_location = rdev->mc.gtt_location - ++ rdev->mc.mc_vram_size; ++ } else if (tmp > rdev->mc.mc_vram_size) { ++ /* Enought place after */ ++ rdev->mc.vram_location = rdev->mc.gtt_location + ++ rdev->mc.gtt_size; ++ } else { ++ /* Try to setup VRAM then AGP might not ++ * not work on some card ++ */ ++ rdev->mc.vram_location = 0x00000000UL; ++ rdev->mc.gtt_location = rdev->mc.mc_vram_size; ++ } ++ } else { ++ rdev->mc.vram_location = 0x00000000UL; ++ rdev->mc.gtt_location = rdev->mc.mc_vram_size; ++ rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; ++ } ++ rdev->mc.vram_start = rdev->mc.vram_location; ++ rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; ++ rdev->mc.gtt_start = rdev->mc.gtt_location; ++ rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; ++ /* FIXME: we should enforce default clock in case GPU is not in ++ * default setup ++ */ ++ a.full = rfixed_const(100); ++ rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); ++ rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); ++ return 0; ++} ++int evergreen_gpu_reset(struct radeon_device *rdev) ++{ ++ /* FIXME: implement for evergreen */ ++ return 0; ++} ++ ++static int evergreen_startup(struct radeon_device *rdev) ++{ ++#if 0 ++ int r; ++ ++ if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { ++ r = r600_init_microcode(rdev); ++ if (r) { ++ DRM_ERROR("Failed to load firmware!\n"); ++ return r; ++ } ++ } ++#endif ++ evergreen_mc_program(rdev); ++#if 0 ++ if (rdev->flags & RADEON_IS_AGP) { ++ evergreem_agp_enable(rdev); ++ } else { ++ r = evergreen_pcie_gart_enable(rdev); ++ if (r) ++ return r; ++ } ++#endif ++ evergreen_gpu_init(rdev); ++#if 0 ++ if (!rdev->r600_blit.shader_obj) { ++ r = r600_blit_init(rdev); ++ if (r) { ++ DRM_ERROR("radeon: failed blitter (%d).\n", r); ++ return r; ++ } ++ } ++ ++ r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); ++ if (unlikely(r != 0)) ++ return r; ++ r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, ++ &rdev->r600_blit.shader_gpu_addr); ++ radeon_bo_unreserve(rdev->r600_blit.shader_obj); ++ if (r) { ++ DRM_ERROR("failed to pin blit object %d\n", r); ++ return r; ++ } ++ ++ /* Enable IRQ */ ++ r = r600_irq_init(rdev); ++ if (r) { ++ DRM_ERROR("radeon: IH init failed (%d).\n", r); ++ radeon_irq_kms_fini(rdev); ++ return r; ++ } ++ r600_irq_set(rdev); ++ ++ r = radeon_ring_init(rdev, rdev->cp.ring_size); ++ if (r) ++ return r; ++ r = evergreen_cp_load_microcode(rdev); ++ if (r) ++ return r; ++ r = r600_cp_resume(rdev); ++ if (r) ++ return r; ++ /* write back buffer are not vital so don't worry about failure */ ++ r600_wb_enable(rdev); ++#endif ++ return 0; ++} ++ ++int evergreen_resume(struct radeon_device *rdev) ++{ ++ int r; ++ ++ /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, ++ * posting will perform necessary task to bring back GPU into good ++ * shape. ++ */ ++ /* post card */ ++ atom_asic_init(rdev->mode_info.atom_context); ++ /* Initialize clocks */ ++ r = radeon_clocks_init(rdev); ++ if (r) { ++ return r; ++ } ++ ++ r = evergreen_startup(rdev); ++ if (r) { ++ DRM_ERROR("r600 startup failed on resume\n"); ++ return r; ++ } ++#if 0 ++ r = r600_ib_test(rdev); ++ if (r) { ++ DRM_ERROR("radeon: failled testing IB (%d).\n", r); ++ return r; ++ } ++#endif ++ return r; ++ ++} ++ ++int evergreen_suspend(struct radeon_device *rdev) ++{ ++#if 0 ++ int r; ++ ++ /* FIXME: we should wait for ring to be empty */ ++ r700_cp_stop(rdev); ++ rdev->cp.ready = false; ++ r600_wb_disable(rdev); ++ evergreen_pcie_gart_disable(rdev); ++ /* unpin shaders bo */ ++ r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); ++ if (likely(r == 0)) { ++ radeon_bo_unpin(rdev->r600_blit.shader_obj); ++ radeon_bo_unreserve(rdev->r600_blit.shader_obj); ++ } ++#endif ++ return 0; ++} ++ ++static bool evergreen_card_posted(struct radeon_device *rdev) ++{ ++ u32 reg; ++ ++ /* first check CRTCs */ ++ reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | ++ RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | ++ RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | ++ RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | ++ RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | ++ RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); ++ if (reg & EVERGREEN_CRTC_MASTER_EN) ++ return true; ++ ++ /* then check MEM_SIZE, in case the crtcs are off */ ++ if (RREG32(CONFIG_MEMSIZE)) ++ return true; ++ ++ return false; ++} ++ ++/* Plan is to move initialization in that function and use ++ * helper function so that radeon_device_init pretty much ++ * do nothing more than calling asic specific function. This ++ * should also allow to remove a bunch of callback function ++ * like vram_info. ++ */ ++int evergreen_init(struct radeon_device *rdev) ++{ ++ int r; ++ ++ r = radeon_dummy_page_init(rdev); ++ if (r) ++ return r; ++ /* This don't do much */ ++ r = radeon_gem_init(rdev); ++ if (r) ++ return r; ++ /* Read BIOS */ ++ if (!radeon_get_bios(rdev)) { ++ if (ASIC_IS_AVIVO(rdev)) ++ return -EINVAL; ++ } ++ /* Must be an ATOMBIOS */ ++ if (!rdev->is_atom_bios) { ++ dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); ++ return -EINVAL; ++ } ++ r = radeon_atombios_init(rdev); ++ if (r) ++ return r; ++ /* Post card if necessary */ ++ if (!evergreen_card_posted(rdev)) { ++ if (!rdev->bios) { ++ dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); ++ return -EINVAL; ++ } ++ DRM_INFO("GPU not posted. posting now...\n"); ++ atom_asic_init(rdev->mode_info.atom_context); ++ } ++ /* Initialize scratch registers */ ++ r600_scratch_init(rdev); ++ /* Initialize surface registers */ ++ radeon_surface_init(rdev); ++ /* Initialize clocks */ ++ radeon_get_clock_info(rdev->ddev); ++ r = radeon_clocks_init(rdev); ++ if (r) ++ return r; ++ /* Initialize power management */ ++ radeon_pm_init(rdev); ++ /* Fence driver */ ++ r = radeon_fence_driver_init(rdev); ++ if (r) ++ return r; ++ r = evergreen_mc_init(rdev); ++ if (r) ++ return r; ++ /* Memory manager */ ++ r = radeon_bo_init(rdev); ++ if (r) ++ return r; ++#if 0 ++ r = radeon_irq_kms_init(rdev); ++ if (r) ++ return r; ++ ++ rdev->cp.ring_obj = NULL; ++ r600_ring_init(rdev, 1024 * 1024); ++ ++ rdev->ih.ring_obj = NULL; ++ r600_ih_ring_init(rdev, 64 * 1024); ++ ++ r = r600_pcie_gart_init(rdev); ++ if (r) ++ return r; ++#endif ++ rdev->accel_working = false; ++ r = evergreen_startup(rdev); ++ if (r) { ++ evergreen_suspend(rdev); ++ /*r600_wb_fini(rdev);*/ ++ /*radeon_ring_fini(rdev);*/ ++ /*evergreen_pcie_gart_fini(rdev);*/ ++ rdev->accel_working = false; ++ } ++ if (rdev->accel_working) { ++ r = radeon_ib_pool_init(rdev); ++ if (r) { ++ DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r); ++ rdev->accel_working = false; ++ } ++ r = r600_ib_test(rdev); ++ if (r) { ++ DRM_ERROR("radeon: failed testing IB (%d).\n", r); ++ rdev->accel_working = false; ++ } ++ } ++ return 0; ++} ++ ++void evergreen_fini(struct radeon_device *rdev) ++{ ++ evergreen_suspend(rdev); ++#if 0 ++ r600_blit_fini(rdev); ++ r600_irq_fini(rdev); ++ radeon_irq_kms_fini(rdev); ++ radeon_ring_fini(rdev); ++ r600_wb_fini(rdev); ++ evergreen_pcie_gart_fini(rdev); ++#endif ++ radeon_gem_fini(rdev); ++ radeon_fence_driver_fini(rdev); ++ radeon_clocks_fini(rdev); ++ radeon_agp_fini(rdev); ++ radeon_bo_fini(rdev); ++ radeon_atombios_fini(rdev); ++ kfree(rdev->bios); ++ rdev->bios = NULL; ++ radeon_dummy_page_fini(rdev); ++} +diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h b/drivers/gpu/drm/radeon/evergreen_reg.h +new file mode 100644 +index 0000000..f7c7c96 +--- /dev/null ++++ b/drivers/gpu/drm/radeon/evergreen_reg.h +@@ -0,0 +1,176 @@ ++/* ++ * Copyright 2010 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * Authors: Alex Deucher ++ */ ++#ifndef __EVERGREEN_REG_H__ ++#define __EVERGREEN_REG_H__ ++ ++/* evergreen */ ++#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310 ++#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324 ++#define EVERGREEN_D3VGA_CONTROL 0x3e0 ++#define EVERGREEN_D4VGA_CONTROL 0x3e4 ++#define EVERGREEN_D5VGA_CONTROL 0x3e8 ++#define EVERGREEN_D6VGA_CONTROL 0x3ec ++ ++#define EVERGREEN_P1PLL_SS_CNTL 0x414 ++#define EVERGREEN_P2PLL_SS_CNTL 0x454 ++# define EVERGREEN_PxPLL_SS_EN (1 << 12) ++/* GRPH blocks at 0x6800, 0x7400, 0x10000, 0x10c00, 0x11800, 0x12400 */ ++#define EVERGREEN_GRPH_ENABLE 0x6800 ++#define EVERGREEN_GRPH_CONTROL 0x6804 ++# define EVERGREEN_GRPH_DEPTH(x) (((x) & 0x3) << 0) ++# define EVERGREEN_GRPH_DEPTH_8BPP 0 ++# define EVERGREEN_GRPH_DEPTH_16BPP 1 ++# define EVERGREEN_GRPH_DEPTH_32BPP 2 ++# define EVERGREEN_GRPH_FORMAT(x) (((x) & 0x7) << 8) ++/* 8 BPP */ ++# define EVERGREEN_GRPH_FORMAT_INDEXED 0 ++/* 16 BPP */ ++# define EVERGREEN_GRPH_FORMAT_ARGB1555 0 ++# define EVERGREEN_GRPH_FORMAT_ARGB565 1 ++# define EVERGREEN_GRPH_FORMAT_ARGB4444 2 ++# define EVERGREEN_GRPH_FORMAT_AI88 3 ++# define EVERGREEN_GRPH_FORMAT_MONO16 4 ++# define EVERGREEN_GRPH_FORMAT_BGRA5551 5 ++/* 32 BPP */ ++# define EVERGREEN_GRPH_FORMAT_ARGB8888 0 ++# define EVERGREEN_GRPH_FORMAT_ARGB2101010 1 ++# define EVERGREEN_GRPH_FORMAT_32BPP_DIG 2 ++# define EVERGREEN_GRPH_FORMAT_8B_ARGB2101010 3 ++# define EVERGREEN_GRPH_FORMAT_BGRA1010102 4 ++# define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102 5 ++# define EVERGREEN_GRPH_FORMAT_RGB111110 6 ++# define EVERGREEN_GRPH_FORMAT_BGR101111 7 ++#define EVERGREEN_GRPH_SWAP_CONTROL 0x680c ++# define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) ++# define EVERGREEN_GRPH_ENDIAN_NONE 0 ++# define EVERGREEN_GRPH_ENDIAN_8IN16 1 ++# define EVERGREEN_GRPH_ENDIAN_8IN32 2 ++# define EVERGREEN_GRPH_ENDIAN_8IN64 3 ++# define EVERGREEN_GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) ++# define EVERGREEN_GRPH_RED_SEL_R 0 ++# define EVERGREEN_GRPH_RED_SEL_G 1 ++# define EVERGREEN_GRPH_RED_SEL_B 2 ++# define EVERGREEN_GRPH_RED_SEL_A 3 ++# define EVERGREEN_GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) ++# define EVERGREEN_GRPH_GREEN_SEL_G 0 ++# define EVERGREEN_GRPH_GREEN_SEL_B 1 ++# define EVERGREEN_GRPH_GREEN_SEL_A 2 ++# define EVERGREEN_GRPH_GREEN_SEL_R 3 ++# define EVERGREEN_GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) ++# define EVERGREEN_GRPH_BLUE_SEL_B 0 ++# define EVERGREEN_GRPH_BLUE_SEL_A 1 ++# define EVERGREEN_GRPH_BLUE_SEL_R 2 ++# define EVERGREEN_GRPH_BLUE_SEL_G 3 ++# define EVERGREEN_GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10) ++# define EVERGREEN_GRPH_ALPHA_SEL_A 0 ++# define EVERGREEN_GRPH_ALPHA_SEL_R 1 ++# define EVERGREEN_GRPH_ALPHA_SEL_G 2 ++# define EVERGREEN_GRPH_ALPHA_SEL_B 3 ++#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS 0x6810 ++#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS 0x6814 ++# define EVERGREEN_GRPH_DFQ_ENABLE (1 << 0) ++# define EVERGREEN_GRPH_SURFACE_ADDRESS_MASK 0xffffff00 ++#define EVERGREEN_GRPH_PITCH 0x6818 ++#define EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x681c ++#define EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x6820 ++#define EVERGREEN_GRPH_SURFACE_OFFSET_X 0x6824 ++#define EVERGREEN_GRPH_SURFACE_OFFSET_Y 0x6828 ++#define EVERGREEN_GRPH_X_START 0x682c ++#define EVERGREEN_GRPH_Y_START 0x6830 ++#define EVERGREEN_GRPH_X_END 0x6834 ++#define EVERGREEN_GRPH_Y_END 0x6838 ++ ++/* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */ ++#define EVERGREEN_CUR_CONTROL 0x6998 ++# define EVERGREEN_CURSOR_EN (1 << 0) ++# define EVERGREEN_CURSOR_MODE(x) (((x) & 0x3) << 8) ++# define EVERGREEN_CURSOR_MONO 0 ++# define EVERGREEN_CURSOR_24_1 1 ++# define EVERGREEN_CURSOR_24_8_PRE_MULT 2 ++# define EVERGREEN_CURSOR_24_8_UNPRE_MULT 3 ++# define EVERGREEN_CURSOR_2X_MAGNIFY (1 << 16) ++# define EVERGREEN_CURSOR_FORCE_MC_ON (1 << 20) ++# define EVERGREEN_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24) ++# define EVERGREEN_CURSOR_URGENT_ALWAYS 0 ++# define EVERGREEN_CURSOR_URGENT_1_8 1 ++# define EVERGREEN_CURSOR_URGENT_1_4 2 ++# define EVERGREEN_CURSOR_URGENT_3_8 3 ++# define EVERGREEN_CURSOR_URGENT_1_2 4 ++#define EVERGREEN_CUR_SURFACE_ADDRESS 0x699c ++# define EVERGREEN_CUR_SURFACE_ADDRESS_MASK 0xfffff000 ++#define EVERGREEN_CUR_SIZE 0x69a0 ++#define EVERGREEN_CUR_SURFACE_ADDRESS_HIGH 0x69a4 ++#define EVERGREEN_CUR_POSITION 0x69a8 ++#define EVERGREEN_CUR_HOT_SPOT 0x69ac ++#define EVERGREEN_CUR_COLOR1 0x69b0 ++#define EVERGREEN_CUR_COLOR2 0x69b4 ++#define EVERGREEN_CUR_UPDATE 0x69b8 ++# define EVERGREEN_CURSOR_UPDATE_PENDING (1 << 0) ++# define EVERGREEN_CURSOR_UPDATE_TAKEN (1 << 1) ++# define EVERGREEN_CURSOR_UPDATE_LOCK (1 << 16) ++# define EVERGREEN_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24) ++ ++/* LUT blocks at 0x69e0, 0x75e0, 0x101e0, 0x10de0, 0x119e0, 0x125e0 */ ++#define EVERGREEN_DC_LUT_RW_MODE 0x69e0 ++#define EVERGREEN_DC_LUT_RW_INDEX 0x69e4 ++#define EVERGREEN_DC_LUT_SEQ_COLOR 0x69e8 ++#define EVERGREEN_DC_LUT_PWL_DATA 0x69ec ++#define EVERGREEN_DC_LUT_30_COLOR 0x69f0 ++#define EVERGREEN_DC_LUT_VGA_ACCESS_ENABLE 0x69f4 ++#define EVERGREEN_DC_LUT_WRITE_EN_MASK 0x69f8 ++#define EVERGREEN_DC_LUT_AUTOFILL 0x69fc ++#define EVERGREEN_DC_LUT_CONTROL 0x6a00 ++#define EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE 0x6a04 ++#define EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN 0x6a08 ++#define EVERGREEN_DC_LUT_BLACK_OFFSET_RED 0x6a0c ++#define EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE 0x6a10 ++#define EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN 0x6a14 ++#define EVERGREEN_DC_LUT_WHITE_OFFSET_RED 0x6a18 ++ ++#define EVERGREEN_DATA_FORMAT 0x6b00 ++# define EVERGREEN_INTERLEAVE_EN (1 << 0) ++#define EVERGREEN_DESKTOP_HEIGHT 0x6b04 ++ ++#define EVERGREEN_VIEWPORT_START 0x6d70 ++#define EVERGREEN_VIEWPORT_SIZE 0x6d74 ++ ++/* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ ++#define EVERGREEN_CRTC0_REGISTER_OFFSET (0x6df0 - 0x6df0) ++#define EVERGREEN_CRTC1_REGISTER_OFFSET (0x79f0 - 0x6df0) ++#define EVERGREEN_CRTC2_REGISTER_OFFSET (0x105f0 - 0x6df0) ++#define EVERGREEN_CRTC3_REGISTER_OFFSET (0x111f0 - 0x6df0) ++#define EVERGREEN_CRTC4_REGISTER_OFFSET (0x11df0 - 0x6df0) ++#define EVERGREEN_CRTC5_REGISTER_OFFSET (0x129f0 - 0x6df0) ++ ++/* CRTC blocks at 0x6df0, 0x79f0, 0x105f0, 0x111f0, 0x11df0, 0x129f0 */ ++#define EVERGREEN_CRTC_CONTROL 0x6e70 ++# define EVERGREEN_CRTC_MASTER_EN (1 << 0) ++#define EVERGREEN_CRTC_UPDATE_LOCK 0x6ed4 ++ ++#define EVERGREEN_DC_GPIO_HPD_MASK 0x64b0 ++#define EVERGREEN_DC_GPIO_HPD_A 0x64b4 ++#define EVERGREEN_DC_GPIO_HPD_EN 0x64b8 ++#define EVERGREEN_DC_GPIO_HPD_Y 0x64bc ++ ++#endif +diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h +index c0356bb..d564c62 100644 +--- a/drivers/gpu/drm/radeon/radeon.h ++++ b/drivers/gpu/drm/radeon/radeon.h +@@ -138,11 +138,14 @@ void radeon_dummy_page_fini(struct radeon_device *rdev); + struct radeon_clock { + struct radeon_pll p1pll; + struct radeon_pll p2pll; ++ struct radeon_pll dcpll; + struct radeon_pll spll; + struct radeon_pll mpll; + /* 10 Khz units */ + uint32_t default_mclk; + uint32_t default_sclk; ++ uint32_t default_dispclk; ++ uint32_t dp_extclk; + }; + + /* +@@ -830,6 +833,7 @@ struct radeon_device { + struct r600_ih ih; /* r6/700 interrupt ring */ + struct workqueue_struct *wq; + struct work_struct hotplug_work; ++ int num_crtc; /* number of crtcs */ + + /* audio stuff */ + struct timer_list audio_timer; +@@ -956,7 +960,7 @@ void r100_pll_errata_after_index(struct radeon_device *rdev); + #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) + #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) + #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) +- ++#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) + + /* + * BIOS helpers. +@@ -1189,6 +1193,14 @@ extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder, + uint8_t status_bits, + uint8_t category_code); + ++/* evergreen */ ++struct evergreen_mc_save { ++ u32 vga_control[6]; ++ u32 vga_render_control; ++ u32 vga_hdp_control; ++ u32 crtc_control[6]; ++}; ++ + #include "radeon_object.h" + + #endif +diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h +index 05ee1ae..f7734c3 100644 +--- a/drivers/gpu/drm/radeon/radeon_asic.h ++++ b/drivers/gpu/drm/radeon/radeon_asic.h +@@ -539,7 +539,7 @@ static struct radeon_asic r600_asic = { + .get_memory_clock = &radeon_atom_get_memory_clock, + .set_memory_clock = &radeon_atom_set_memory_clock, + .set_pcie_lanes = NULL, +- .set_clock_gating = &radeon_atom_set_clock_gating, ++ .set_clock_gating = NULL, + .set_surface_reg = r600_set_surface_reg, + .clear_surface_reg = r600_clear_surface_reg, + .bandwidth_update = &rv515_bandwidth_update, +@@ -595,4 +595,54 @@ static struct radeon_asic rv770_asic = { + .ioctl_wait_idle = r600_ioctl_wait_idle, + }; + ++/* ++ * evergreen ++ */ ++int evergreen_init(struct radeon_device *rdev); ++void evergreen_fini(struct radeon_device *rdev); ++int evergreen_suspend(struct radeon_device *rdev); ++int evergreen_resume(struct radeon_device *rdev); ++int evergreen_gpu_reset(struct radeon_device *rdev); ++void evergreen_bandwidth_update(struct radeon_device *rdev); ++void evergreen_hpd_init(struct radeon_device *rdev); ++void evergreen_hpd_fini(struct radeon_device *rdev); ++bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); ++void evergreen_hpd_set_polarity(struct radeon_device *rdev, ++ enum radeon_hpd_id hpd); ++ ++static struct radeon_asic evergreen_asic = { ++ .init = &evergreen_init, ++ .fini = &evergreen_fini, ++ .suspend = &evergreen_suspend, ++ .resume = &evergreen_resume, ++ .cp_commit = NULL, ++ .gpu_reset = &evergreen_gpu_reset, ++ .vga_set_state = &r600_vga_set_state, ++ .gart_tlb_flush = &r600_pcie_gart_tlb_flush, ++ .gart_set_page = &rs600_gart_set_page, ++ .ring_test = NULL, ++ .ring_ib_execute = NULL, ++ .irq_set = NULL, ++ .irq_process = NULL, ++ .get_vblank_counter = NULL, ++ .fence_ring_emit = NULL, ++ .cs_parse = NULL, ++ .copy_blit = NULL, ++ .copy_dma = NULL, ++ .copy = NULL, ++ .get_engine_clock = &radeon_atom_get_engine_clock, ++ .set_engine_clock = &radeon_atom_set_engine_clock, ++ .get_memory_clock = &radeon_atom_get_memory_clock, ++ .set_memory_clock = &radeon_atom_set_memory_clock, ++ .set_pcie_lanes = NULL, ++ .set_clock_gating = NULL, ++ .set_surface_reg = r600_set_surface_reg, ++ .clear_surface_reg = r600_clear_surface_reg, ++ .bandwidth_update = &evergreen_bandwidth_update, ++ .hpd_init = &evergreen_hpd_init, ++ .hpd_fini = &evergreen_hpd_fini, ++ .hpd_sense = &evergreen_hpd_sense, ++ .hpd_set_polarity = &evergreen_hpd_set_polarity, ++}; ++ + #endif +diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c +index 4d88315..381ebdd 100644 +--- a/drivers/gpu/drm/radeon/radeon_atombios.c ++++ b/drivers/gpu/drm/radeon/radeon_atombios.c +@@ -159,8 +159,15 @@ static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device + struct radeon_gpio_rec *gpio) + { + struct radeon_hpd hpd; ++ u32 reg; ++ ++ if (ASIC_IS_DCE4(rdev)) ++ reg = EVERGREEN_DC_GPIO_HPD_A; ++ else ++ reg = AVIVO_DC_GPIO_HPD_A; ++ + hpd.gpio = *gpio; +- if (gpio->reg == AVIVO_DC_GPIO_HPD_A) { ++ if (gpio->reg == reg) { + switch(gpio->mask) { + case (1 << 0): + hpd.hpd = RADEON_HPD_1; +@@ -574,6 +581,9 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) + ddc_bus.valid = false; + } + ++ /* needed for aux chan transactions */ ++ ddc_bus.hpd_id = hpd.hpd ? (hpd.hpd - 1) : 0; ++ + conn_id = le16_to_cpu(path->usConnObjectId); + + if (!radeon_atom_apply_quirks +@@ -838,6 +848,7 @@ union firmware_info { + ATOM_FIRMWARE_INFO_V1_2 info_12; + ATOM_FIRMWARE_INFO_V1_3 info_13; + ATOM_FIRMWARE_INFO_V1_4 info_14; ++ ATOM_FIRMWARE_INFO_V2_1 info_21; + }; + + bool radeon_atom_get_clock_info(struct drm_device *dev) +@@ -849,6 +860,7 @@ bool radeon_atom_get_clock_info(struct drm_device *dev) + uint8_t frev, crev; + struct radeon_pll *p1pll = &rdev->clock.p1pll; + struct radeon_pll *p2pll = &rdev->clock.p2pll; ++ struct radeon_pll *dcpll = &rdev->clock.dcpll; + struct radeon_pll *spll = &rdev->clock.spll; + struct radeon_pll *mpll = &rdev->clock.mpll; + uint16_t data_offset; +@@ -951,8 +963,19 @@ bool radeon_atom_get_clock_info(struct drm_device *dev) + rdev->clock.default_mclk = + le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); + ++ if (ASIC_IS_DCE4(rdev)) { ++ rdev->clock.default_dispclk = ++ le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); ++ if (rdev->clock.default_dispclk == 0) ++ rdev->clock.default_dispclk = 60000; /* 600 Mhz */ ++ rdev->clock.dp_extclk = ++ le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); ++ } ++ *dcpll = *p1pll; ++ + return true; + } ++ + return false; + } + +@@ -1395,16 +1418,6 @@ void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) + atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); + } + +-void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable) +-{ +- ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args; +- int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt); +- +- args.ucEnable = enable; +- +- atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); +-} +- + uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev) + { + GET_ENGINE_CLOCK_PS_ALLOCATION args; +diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c +index 73c4405..f64936c 100644 +--- a/drivers/gpu/drm/radeon/radeon_clocks.c ++++ b/drivers/gpu/drm/radeon/radeon_clocks.c +@@ -96,6 +96,7 @@ void radeon_get_clock_info(struct drm_device *dev) + struct radeon_device *rdev = dev->dev_private; + struct radeon_pll *p1pll = &rdev->clock.p1pll; + struct radeon_pll *p2pll = &rdev->clock.p2pll; ++ struct radeon_pll *dcpll = &rdev->clock.dcpll; + struct radeon_pll *spll = &rdev->clock.spll; + struct radeon_pll *mpll = &rdev->clock.mpll; + int ret; +@@ -204,6 +205,17 @@ void radeon_get_clock_info(struct drm_device *dev) + p2pll->max_frac_feedback_div = 0; + } + ++ /* dcpll is DCE4 only */ ++ dcpll->min_post_div = 2; ++ dcpll->max_post_div = 0x7f; ++ dcpll->min_frac_feedback_div = 0; ++ dcpll->max_frac_feedback_div = 9; ++ dcpll->min_ref_div = 2; ++ dcpll->max_ref_div = 0x3ff; ++ dcpll->min_feedback_div = 4; ++ dcpll->max_feedback_div = 0xfff; ++ dcpll->best_vco = 0; ++ + p1pll->min_ref_div = 2; + p1pll->max_ref_div = 0x3ff; + p1pll->min_feedback_div = 4; +@@ -846,8 +858,10 @@ int radeon_static_clocks_init(struct drm_device *dev) + /* XXX make sure engine is idle */ + + if (radeon_dynclks != -1) { +- if (radeon_dynclks) +- radeon_set_clock_gating(rdev, 1); ++ if (radeon_dynclks) { ++ if (rdev->asic->set_clock_gating) ++ radeon_set_clock_gating(rdev, 1); ++ } + } + radeon_apply_clock_quirks(rdev); + return 0; +diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c +index e7b1944..e3388a9 100644 +--- a/drivers/gpu/drm/radeon/radeon_combios.c ++++ b/drivers/gpu/drm/radeon/radeon_combios.c +@@ -507,6 +507,7 @@ static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rde + } + i2c.mm_i2c = false; + i2c.i2c_id = 0; ++ i2c.hpd_id = 0; + + if (ddc_line) + i2c.valid = true; +diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c +index 28772a3..7ecf5e1 100644 +--- a/drivers/gpu/drm/radeon/radeon_cursor.c ++++ b/drivers/gpu/drm/radeon/radeon_cursor.c +@@ -36,7 +36,14 @@ static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock) + struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); + uint32_t cur_lock; + +- if (ASIC_IS_AVIVO(rdev)) { ++ if (ASIC_IS_DCE4(rdev)) { ++ cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset); ++ if (lock) ++ cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK; ++ else ++ cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK; ++ WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); ++ } else if (ASIC_IS_AVIVO(rdev)) { + cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); + if (lock) + cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK; +@@ -58,7 +65,10 @@ static void radeon_hide_cursor(struct drm_crtc *crtc) + struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); + struct radeon_device *rdev = crtc->dev->dev_private; + +- if (ASIC_IS_AVIVO(rdev)) { ++ if (ASIC_IS_DCE4(rdev)) { ++ WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); ++ WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT)); ++ } else if (ASIC_IS_AVIVO(rdev)) { + WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); + WREG32(RADEON_MM_DATA, (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); + } else { +@@ -81,10 +91,14 @@ static void radeon_show_cursor(struct drm_crtc *crtc) + struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); + struct radeon_device *rdev = crtc->dev->dev_private; + +- if (ASIC_IS_AVIVO(rdev)) { ++ if (ASIC_IS_DCE4(rdev)) { ++ WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); ++ WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN | ++ EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT)); ++ } else if (ASIC_IS_AVIVO(rdev)) { + WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); + WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | +- (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); ++ (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); + } else { + switch (radeon_crtc->crtc_id) { + case 0: +@@ -109,7 +123,10 @@ static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj, + struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); + struct radeon_device *rdev = crtc->dev->dev_private; + +- if (ASIC_IS_AVIVO(rdev)) { ++ if (ASIC_IS_DCE4(rdev)) { ++ WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 0); ++ WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr); ++ } else if (ASIC_IS_AVIVO(rdev)) { + if (rdev->family >= CHIP_RV770) { + if (radeon_crtc->crtc_id) + WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, 0); +@@ -201,7 +218,20 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc, + yorigin = CURSOR_HEIGHT - 1; + + radeon_lock_cursor(crtc, true); +- if (ASIC_IS_AVIVO(rdev)) { ++ if (ASIC_IS_DCE4(rdev)) { ++ /* cursors are offset into the total surface */ ++ x += crtc->x; ++ y += crtc->y; ++ DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); ++ ++ /* XXX: check if evergreen has the same issues as avivo chips */ ++ WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, ++ ((xorigin ? 0 : x) << 16) | ++ (yorigin ? 0 : y)); ++ WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); ++ WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset, ++ ((radeon_crtc->cursor_width - 1) << 16) | (radeon_crtc->cursor_height - 1)); ++ } else if (ASIC_IS_AVIVO(rdev)) { + int w = radeon_crtc->cursor_width; + int i = 0; + struct drm_crtc *crtc_p; +diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c +index 768b150..4ca5ddc 100644 +--- a/drivers/gpu/drm/radeon/radeon_device.c ++++ b/drivers/gpu/drm/radeon/radeon_device.c +@@ -182,7 +182,16 @@ bool radeon_card_posted(struct radeon_device *rdev) + uint32_t reg; + + /* first check CRTCs */ +- if (ASIC_IS_AVIVO(rdev)) { ++ if (ASIC_IS_DCE4(rdev)) { ++ reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | ++ RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | ++ RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | ++ RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | ++ RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | ++ RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); ++ if (reg & EVERGREEN_CRTC_MASTER_EN) ++ return true; ++ } else if (ASIC_IS_AVIVO(rdev)) { + reg = RREG32(AVIVO_D1CRTC_CONTROL) | + RREG32(AVIVO_D2CRTC_CONTROL); + if (reg & AVIVO_CRTC_EN) { +@@ -310,7 +319,7 @@ void radeon_register_accessor_init(struct radeon_device *rdev) + rdev->mc_rreg = &rs600_mc_rreg; + rdev->mc_wreg = &rs600_mc_wreg; + } +- if (rdev->family >= CHIP_R600) { ++ if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) { + rdev->pciep_rreg = &r600_pciep_rreg; + rdev->pciep_wreg = &r600_pciep_wreg; + } +@@ -387,6 +396,13 @@ int radeon_asic_init(struct radeon_device *rdev) + case CHIP_RV740: + rdev->asic = &rv770_asic; + break; ++ case CHIP_CEDAR: ++ case CHIP_REDWOOD: ++ case CHIP_JUNIPER: ++ case CHIP_CYPRESS: ++ case CHIP_HEMLOCK: ++ rdev->asic = &evergreen_asic; ++ break; + default: + /* FIXME: not supported yet */ + return -EINVAL; +diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c +index 7e17a36..86a9f01 100644 +--- a/drivers/gpu/drm/radeon/radeon_display.c ++++ b/drivers/gpu/drm/radeon/radeon_display.c +@@ -68,6 +68,36 @@ static void avivo_crtc_load_lut(struct drm_crtc *crtc) + WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); + } + ++static void evergreen_crtc_load_lut(struct drm_crtc *crtc) ++{ ++ struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); ++ struct drm_device *dev = crtc->dev; ++ struct radeon_device *rdev = dev->dev_private; ++ int i; ++ ++ DRM_DEBUG("%d\n", radeon_crtc->crtc_id); ++ WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); ++ ++ WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); ++ WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); ++ WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); ++ ++ WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); ++ WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); ++ WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); ++ ++ WREG32(EVERGREEN_DC_LUT_RW_MODE, radeon_crtc->crtc_id); ++ WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK, 0x00000007); ++ ++ WREG32(EVERGREEN_DC_LUT_RW_INDEX, 0); ++ for (i = 0; i < 256; i++) { ++ WREG32(EVERGREEN_DC_LUT_30_COLOR, ++ (radeon_crtc->lut_r[i] << 20) | ++ (radeon_crtc->lut_g[i] << 10) | ++ (radeon_crtc->lut_b[i] << 0)); ++ } ++} ++ + static void legacy_crtc_load_lut(struct drm_crtc *crtc) + { + struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); +@@ -100,7 +130,9 @@ void radeon_crtc_load_lut(struct drm_crtc *crtc) + if (!crtc->enabled) + return; + +- if (ASIC_IS_AVIVO(rdev)) ++ if (ASIC_IS_DCE4(rdev)) ++ evergreen_crtc_load_lut(crtc); ++ else if (ASIC_IS_AVIVO(rdev)) + avivo_crtc_load_lut(crtc); + else + legacy_crtc_load_lut(crtc); +@@ -819,7 +851,7 @@ static int radeon_modeset_create_props(struct radeon_device *rdev) + + int radeon_modeset_init(struct radeon_device *rdev) + { +- int num_crtc = 2, i; ++ int i; + int ret; + + drm_mode_config_init(rdev->ddev); +@@ -843,10 +875,16 @@ int radeon_modeset_init(struct radeon_device *rdev) + } + + if (rdev->flags & RADEON_SINGLE_CRTC) +- num_crtc = 1; ++ rdev->num_crtc = 1; ++ else { ++ if (ASIC_IS_DCE4(rdev)) ++ rdev->num_crtc = 6; ++ else ++ rdev->num_crtc = 2; ++ } + + /* allocate crtcs */ +- for (i = 0; i < num_crtc; i++) { ++ for (i = 0; i < rdev->num_crtc; i++) { + radeon_crtc_init(rdev->ddev, i); + } + +diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c +index 3c91724..cac9e06 100644 +--- a/drivers/gpu/drm/radeon/radeon_encoders.c ++++ b/drivers/gpu/drm/radeon/radeon_encoders.c +@@ -53,7 +53,7 @@ static uint32_t radeon_encoder_clones(struct drm_encoder *encoder) + /* DVO requires 2x ppll clocks depending on tmds chip */ + if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) + return index_mask; +- ++ + count = -1; + list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) { + struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder); +@@ -228,6 +228,32 @@ radeon_get_connector_for_encoder(struct drm_encoder *encoder) + return NULL; + } + ++static struct radeon_connector_atom_dig * ++radeon_get_atom_connector_priv_from_encoder(struct drm_encoder *encoder) ++{ ++ struct drm_device *dev = encoder->dev; ++ struct radeon_device *rdev = dev->dev_private; ++ struct drm_connector *connector; ++ struct radeon_connector *radeon_connector; ++ struct radeon_connector_atom_dig *dig_connector; ++ ++ if (!rdev->is_atom_bios) ++ return NULL; ++ ++ connector = radeon_get_connector_for_encoder(encoder); ++ if (!connector) ++ return NULL; ++ ++ radeon_connector = to_radeon_connector(connector); ++ ++ if (!radeon_connector->con_priv) ++ return NULL; ++ ++ dig_connector = radeon_connector->con_priv; ++ ++ return dig_connector; ++} ++ + static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +@@ -273,7 +299,7 @@ static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, + } + + if (ASIC_IS_DCE3(rdev) && +- (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT))) { ++ (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) { + struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); + radeon_dp_set_link_config(connector, mode); + } +@@ -458,34 +484,20 @@ atombios_digital_setup(struct drm_encoder *encoder, int action) + struct drm_device *dev = encoder->dev; + struct radeon_device *rdev = dev->dev_private; + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); ++ struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; ++ struct radeon_connector_atom_dig *dig_connector = ++ radeon_get_atom_connector_priv_from_encoder(encoder); + union lvds_encoder_control args; + int index = 0; + int hdmi_detected = 0; + uint8_t frev, crev; +- struct radeon_encoder_atom_dig *dig; +- struct drm_connector *connector; +- struct radeon_connector *radeon_connector; +- struct radeon_connector_atom_dig *dig_connector; +- +- connector = radeon_get_connector_for_encoder(encoder); +- if (!connector) +- return; +- +- radeon_connector = to_radeon_connector(connector); + +- if (!radeon_encoder->enc_priv) ++ if (!dig || !dig_connector) + return; + +- dig = radeon_encoder->enc_priv; +- +- if (!radeon_connector->con_priv) +- return; +- +- if (drm_detect_hdmi_monitor(radeon_connector->edid)) ++ if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) + hdmi_detected = 1; + +- dig_connector = radeon_connector->con_priv; +- + memset(&args, 0, sizeof(args)); + + switch (radeon_encoder->encoder_id) { +@@ -586,7 +598,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) + { + struct drm_connector *connector; + struct radeon_connector *radeon_connector; +- struct radeon_connector_atom_dig *radeon_dig_connector; ++ struct radeon_connector_atom_dig *dig_connector; + + connector = radeon_get_connector_for_encoder(encoder); + if (!connector) +@@ -617,9 +629,9 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) + break; + case DRM_MODE_CONNECTOR_DisplayPort: + case DRM_MODE_CONNECTOR_eDP: +- radeon_dig_connector = radeon_connector->con_priv; +- if ((radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || +- (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) ++ dig_connector = radeon_connector->con_priv; ++ if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || ++ (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) + return ATOM_ENCODER_MODE_DP; + else if (drm_detect_hdmi_monitor(radeon_connector->edid)) + return ATOM_ENCODER_MODE_HDMI; +@@ -656,6 +668,18 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) + * - 2 DIG encoder blocks. + * DIG1/2 can drive UNIPHY0/1/2 link A or link B + * ++ * DCE 4.0 ++ * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B). ++ * Supports up to 6 digital outputs ++ * - 6 DIG encoder blocks. ++ * - DIG to PHY mapping is hardcoded ++ * DIG1 drives UNIPHY0 link A, A+B ++ * DIG2 drives UNIPHY0 link B ++ * DIG3 drives UNIPHY1 link A, A+B ++ * DIG4 drives UNIPHY1 link B ++ * DIG5 drives UNIPHY2 link A, A+B ++ * DIG6 drives UNIPHY2 link B ++ * + * Routing + * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) + * Examples: +@@ -664,88 +688,77 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) + * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS + * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI + */ +-static void ++ ++union dig_encoder_control { ++ DIG_ENCODER_CONTROL_PS_ALLOCATION v1; ++ DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; ++ DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; ++}; ++ ++void + atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) + { + struct drm_device *dev = encoder->dev; + struct radeon_device *rdev = dev->dev_private; + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); +- DIG_ENCODER_CONTROL_PS_ALLOCATION args; +- int index = 0, num = 0; ++ struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; ++ struct radeon_connector_atom_dig *dig_connector = ++ radeon_get_atom_connector_priv_from_encoder(encoder); ++ union dig_encoder_control args; ++ int index = 0; + uint8_t frev, crev; +- struct radeon_encoder_atom_dig *dig; +- struct drm_connector *connector; +- struct radeon_connector *radeon_connector; +- struct radeon_connector_atom_dig *dig_connector; +- +- connector = radeon_get_connector_for_encoder(encoder); +- if (!connector) +- return; +- +- radeon_connector = to_radeon_connector(connector); + +- if (!radeon_connector->con_priv) ++ if (!dig || !dig_connector) + return; + +- dig_connector = radeon_connector->con_priv; +- +- if (!radeon_encoder->enc_priv) +- return; +- +- dig = radeon_encoder->enc_priv; +- + memset(&args, 0, sizeof(args)); + +- if (dig->dig_encoder) +- index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); +- else +- index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); +- num = dig->dig_encoder + 1; ++ if (ASIC_IS_DCE4(rdev)) ++ index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); ++ else { ++ if (dig->dig_encoder) ++ index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); ++ else ++ index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); ++ } + + atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); + +- args.ucAction = action; +- args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); ++ args.v1.ucAction = action; ++ args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); ++ args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); + +- if (ASIC_IS_DCE32(rdev)) { ++ if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) { ++ if (dig_connector->dp_clock == 270000) ++ args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; ++ args.v1.ucLaneNum = dig_connector->dp_lane_count; ++ } else if (radeon_encoder->pixel_clock > 165000) ++ args.v1.ucLaneNum = 8; ++ else ++ args.v1.ucLaneNum = 4; ++ ++ if (ASIC_IS_DCE4(rdev)) { ++ args.v3.acConfig.ucDigSel = dig->dig_encoder; ++ args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR; ++ } else { + switch (radeon_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: +- args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; ++ args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: +- args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; ++ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: ++ args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: +- args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; +- break; +- } +- } else { +- switch (radeon_encoder->encoder_id) { +- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: +- args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1; +- break; +- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: +- args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2; ++ args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; + break; + } ++ if (dig_connector->linkb) ++ args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; ++ else ++ args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; + } + +- args.ucEncoderMode = atombios_get_encoder_mode(encoder); +- +- if (args.ucEncoderMode == ATOM_ENCODER_MODE_DP) { +- if (dig_connector->dp_clock == 270000) +- args.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; +- args.ucLaneNum = dig_connector->dp_lane_count; +- } else if (radeon_encoder->pixel_clock > 165000) +- args.ucLaneNum = 8; +- else +- args.ucLaneNum = 4; +- +- if (dig_connector->linkb) +- args.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; +- else +- args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; +- + atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); + + } +@@ -753,6 +766,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action) + union dig_transmitter_control { + DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; + DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; ++ DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; + }; + + void +@@ -761,37 +775,29 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t + struct drm_device *dev = encoder->dev; + struct radeon_device *rdev = dev->dev_private; + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); +- union dig_transmitter_control args; +- int index = 0, num = 0; +- uint8_t frev, crev; +- struct radeon_encoder_atom_dig *dig; ++ struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; ++ struct radeon_connector_atom_dig *dig_connector = ++ radeon_get_atom_connector_priv_from_encoder(encoder); + struct drm_connector *connector; + struct radeon_connector *radeon_connector; +- struct radeon_connector_atom_dig *dig_connector; ++ union dig_transmitter_control args; ++ int index = 0; ++ uint8_t frev, crev; + bool is_dp = false; ++ int pll_id = 0; + +- connector = radeon_get_connector_for_encoder(encoder); +- if (!connector) ++ if (!dig || !dig_connector) + return; + ++ connector = radeon_get_connector_for_encoder(encoder); + radeon_connector = to_radeon_connector(connector); + +- if (!radeon_encoder->enc_priv) +- return; +- +- dig = radeon_encoder->enc_priv; +- +- if (!radeon_connector->con_priv) +- return; +- +- dig_connector = radeon_connector->con_priv; +- + if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) + is_dp = true; + + memset(&args, 0, sizeof(args)); + +- if (ASIC_IS_DCE32(rdev)) ++ if (ASIC_IS_DCE32(rdev) || ASIC_IS_DCE4(rdev)) + index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); + else { + switch (radeon_encoder->encoder_id) { +@@ -821,24 +827,64 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t + else + args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); + } +- if (ASIC_IS_DCE32(rdev)) { +- if (dig->dig_encoder == 1) +- args.v2.acConfig.ucEncoderSel = 1; ++ if (ASIC_IS_DCE4(rdev)) { ++ if (is_dp) ++ args.v3.ucLaneNum = dig_connector->dp_lane_count; ++ else if (radeon_encoder->pixel_clock > 165000) ++ args.v3.ucLaneNum = 8; ++ else ++ args.v3.ucLaneNum = 4; ++ ++ if (dig_connector->linkb) { ++ args.v3.acConfig.ucLinkSel = 1; ++ args.v3.acConfig.ucEncoderSel = 1; ++ } ++ ++ /* Select the PLL for the PHY ++ * DP PHY should be clocked from external src if there is ++ * one. ++ */ ++ if (encoder->crtc) { ++ struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); ++ pll_id = radeon_crtc->pll_id; ++ } ++ if (is_dp && rdev->clock.dp_extclk) ++ args.v3.acConfig.ucRefClkSource = 2; /* external src */ ++ else ++ args.v3.acConfig.ucRefClkSource = pll_id; ++ ++ switch (radeon_encoder->encoder_id) { ++ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: ++ args.v3.acConfig.ucTransmitterSel = 0; ++ break; ++ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: ++ args.v3.acConfig.ucTransmitterSel = 1; ++ break; ++ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: ++ args.v3.acConfig.ucTransmitterSel = 2; ++ break; ++ } ++ ++ if (is_dp) ++ args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ ++ else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { ++ if (dig->coherent_mode) ++ args.v3.acConfig.fCoherentMode = 1; ++ } ++ } else if (ASIC_IS_DCE32(rdev)) { ++ args.v2.acConfig.ucEncoderSel = dig->dig_encoder; + if (dig_connector->linkb) + args.v2.acConfig.ucLinkSel = 1; + + switch (radeon_encoder->encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + args.v2.acConfig.ucTransmitterSel = 0; +- num = 0; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + args.v2.acConfig.ucTransmitterSel = 1; +- num = 1; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + args.v2.acConfig.ucTransmitterSel = 2; +- num = 2; + break; + } + +@@ -849,7 +895,6 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t + args.v2.acConfig.fCoherentMode = 1; + } + } else { +- + args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; + + if (dig->dig_encoder) +@@ -857,31 +902,25 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t + else + args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; + +- switch (radeon_encoder->encoder_id) { +- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: +- if (rdev->flags & RADEON_IS_IGP) { +- if (radeon_encoder->pixel_clock > 165000) { +- if (dig_connector->igp_lane_info & 0x3) +- args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; +- else if (dig_connector->igp_lane_info & 0xc) +- args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; +- } else { +- if (dig_connector->igp_lane_info & 0x1) +- args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; +- else if (dig_connector->igp_lane_info & 0x2) +- args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; +- else if (dig_connector->igp_lane_info & 0x4) +- args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; +- else if (dig_connector->igp_lane_info & 0x8) +- args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; +- } ++ if ((rdev->flags & RADEON_IS_IGP) && ++ (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { ++ if (is_dp || (radeon_encoder->pixel_clock <= 165000)) { ++ if (dig_connector->igp_lane_info & 0x1) ++ args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; ++ else if (dig_connector->igp_lane_info & 0x2) ++ args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; ++ else if (dig_connector->igp_lane_info & 0x4) ++ args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; ++ else if (dig_connector->igp_lane_info & 0x8) ++ args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; ++ } else { ++ if (dig_connector->igp_lane_info & 0x3) ++ args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; ++ else if (dig_connector->igp_lane_info & 0xc) ++ args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; + } +- break; + } + +- if (radeon_encoder->pixel_clock > 165000) +- args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; +- + if (dig_connector->linkb) + args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; + else +@@ -892,6 +931,8 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t + else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { + if (dig->coherent_mode) + args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; ++ if (radeon_encoder->pixel_clock > 165000) ++ args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; + } + } + +@@ -998,16 +1039,25 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) + if (is_dig) { + switch (mode) { + case DRM_MODE_DPMS_ON: +- atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); +- { ++ if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { + struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); ++ + dp_link_train(encoder, connector); ++ if (ASIC_IS_DCE4(rdev)) ++ atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON); + } ++ if (!ASIC_IS_DCE4(rdev)) ++ atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); + break; + case DRM_MODE_DPMS_STANDBY: + case DRM_MODE_DPMS_SUSPEND: + case DRM_MODE_DPMS_OFF: +- atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); ++ if (!ASIC_IS_DCE4(rdev)) ++ atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); ++ if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) { ++ if (ASIC_IS_DCE4(rdev)) ++ atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF); ++ } + break; + } + } else { +@@ -1026,7 +1076,7 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) + radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); + } + +-union crtc_sourc_param { ++union crtc_source_param { + SELECT_CRTC_SOURCE_PS_ALLOCATION v1; + SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; + }; +@@ -1038,7 +1088,7 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder) + struct radeon_device *rdev = dev->dev_private; + struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); +- union crtc_sourc_param args; ++ union crtc_source_param args; + int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); + uint8_t frev, crev; + struct radeon_encoder_atom_dig *dig; +@@ -1107,10 +1157,26 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder) + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: + dig = radeon_encoder->enc_priv; +- if (dig->dig_encoder) +- args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; +- else ++ switch (dig->dig_encoder) { ++ case 0: + args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; ++ break; ++ case 1: ++ args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; ++ break; ++ case 2: ++ args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; ++ break; ++ case 3: ++ args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; ++ break; ++ case 4: ++ args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; ++ break; ++ case 5: ++ args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; ++ break; ++ } + break; + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: + args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; +@@ -1167,6 +1233,7 @@ atombios_apply_encoder_quirks(struct drm_encoder *encoder, + } + + /* set scaler clears this on some chips */ ++ /* XXX check DCE4 */ + if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) { + if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE)) + WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, +@@ -1183,6 +1250,33 @@ static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) + struct drm_encoder *test_encoder; + struct radeon_encoder_atom_dig *dig; + uint32_t dig_enc_in_use = 0; ++ ++ if (ASIC_IS_DCE4(rdev)) { ++ struct radeon_connector_atom_dig *dig_connector = ++ radeon_get_atom_connector_priv_from_encoder(encoder); ++ ++ switch (radeon_encoder->encoder_id) { ++ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: ++ if (dig_connector->linkb) ++ return 1; ++ else ++ return 0; ++ break; ++ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: ++ if (dig_connector->linkb) ++ return 3; ++ else ++ return 2; ++ break; ++ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: ++ if (dig_connector->linkb) ++ return 5; ++ else ++ return 4; ++ break; ++ } ++ } ++ + /* on DCE32 and encoder can driver any block so just crtc id */ + if (ASIC_IS_DCE32(rdev)) { + return radeon_crtc->crtc_id; +@@ -1254,15 +1348,26 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: +- /* disable the encoder and transmitter */ +- atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); +- atombios_dig_encoder_setup(encoder, ATOM_DISABLE); +- +- /* setup and enable the encoder and transmitter */ +- atombios_dig_encoder_setup(encoder, ATOM_ENABLE); +- atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); +- atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); +- atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); ++ if (ASIC_IS_DCE4(rdev)) { ++ /* disable the transmitter */ ++ atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); ++ /* setup and enable the encoder */ ++ atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP); ++ ++ /* init and enable the transmitter */ ++ atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); ++ atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); ++ } else { ++ /* disable the encoder and transmitter */ ++ atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); ++ atombios_dig_encoder_setup(encoder, ATOM_DISABLE); ++ ++ /* setup and enable the encoder and transmitter */ ++ atombios_dig_encoder_setup(encoder, ATOM_ENABLE); ++ atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); ++ atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); ++ atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); ++ } + break; + case ENCODER_OBJECT_ID_INTERNAL_DDI: + atombios_ddia_setup(encoder, ATOM_ENABLE); +@@ -1282,7 +1387,9 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder, + } + atombios_apply_encoder_quirks(encoder, adjusted_mode); + +- r600_hdmi_setmode(encoder, adjusted_mode); ++ /* XXX */ ++ if (!ASIC_IS_DCE4(rdev)) ++ r600_hdmi_setmode(encoder, adjusted_mode); + } + + static bool +@@ -1480,10 +1587,18 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su + return; + + encoder = &radeon_encoder->base; +- if (rdev->flags & RADEON_SINGLE_CRTC) ++ switch (rdev->num_crtc) { ++ case 1: + encoder->possible_crtcs = 0x1; +- else ++ break; ++ case 2: ++ default: + encoder->possible_crtcs = 0x3; ++ break; ++ case 6: ++ encoder->possible_crtcs = 0x3f; ++ break; ++ } + + radeon_encoder->enc_priv = NULL; + +diff --git a/drivers/gpu/drm/radeon/radeon_family.h b/drivers/gpu/drm/radeon/radeon_family.h +index 797972e..93c7d5d 100644 +--- a/drivers/gpu/drm/radeon/radeon_family.h ++++ b/drivers/gpu/drm/radeon/radeon_family.h +@@ -75,6 +75,11 @@ enum radeon_family { + CHIP_RV730, + CHIP_RV710, + CHIP_RV740, ++ CHIP_CEDAR, ++ CHIP_REDWOOD, ++ CHIP_JUNIPER, ++ CHIP_CYPRESS, ++ CHIP_HEMLOCK, + CHIP_LAST, + }; + +diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c +index d71e346..0059242 100644 +--- a/drivers/gpu/drm/radeon/radeon_fb.c ++++ b/drivers/gpu/drm/radeon/radeon_fb.c +@@ -148,7 +148,6 @@ int radeonfb_create(struct drm_device *dev, + unsigned long tmp; + bool fb_tiled = false; /* useful for testing */ + u32 tiling_flags = 0; +- int crtc_count; + + mode_cmd.width = surface_width; + mode_cmd.height = surface_height; +@@ -239,11 +238,7 @@ int radeonfb_create(struct drm_device *dev, + rfbdev = info->par; + rfbdev->helper.funcs = &radeon_fb_helper_funcs; + rfbdev->helper.dev = dev; +- if (rdev->flags & RADEON_SINGLE_CRTC) +- crtc_count = 1; +- else +- crtc_count = 2; +- ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, crtc_count, ++ ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, rdev->num_crtc, + RADEONFB_CONN_LIMIT); + if (ret) + goto out_unref; +diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h +index e81b2ae..2f582a2 100644 +--- a/drivers/gpu/drm/radeon/radeon_mode.h ++++ b/drivers/gpu/drm/radeon/radeon_mode.h +@@ -83,6 +83,8 @@ struct radeon_i2c_bus_rec { + bool valid; + /* id used by atom */ + uint8_t i2c_id; ++ /* id used by atom */ ++ uint8_t hpd_id; + /* can be used with hw i2c engine */ + bool hw_capable; + /* uses multi-media i2c engine */ +@@ -193,7 +195,7 @@ struct radeon_mode_info { + struct card_info *atom_card_info; + enum radeon_connector_table connector_table; + bool mode_config_initialized; +- struct radeon_crtc *crtcs[2]; ++ struct radeon_crtc *crtcs[6]; + /* DVI-I properties */ + struct drm_property *coherent_mode_property; + /* DAC enable load detect */ +@@ -237,6 +239,7 @@ struct radeon_crtc { + fixed20_12 vsc; + fixed20_12 hsc; + struct drm_display_mode native_mode; ++ int pll_id; + }; + + struct radeon_encoder_primary_dac { +@@ -398,6 +401,7 @@ extern void dp_link_train(struct drm_encoder *encoder, + struct drm_connector *connector); + extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); + extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); ++extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action); + extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, + int action, uint8_t lane_num, + uint8_t lane_set); +diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h +index 6d0a009..7f0c752 100644 +--- a/drivers/gpu/drm/radeon/radeon_reg.h ++++ b/drivers/gpu/drm/radeon/radeon_reg.h +@@ -54,7 +54,7 @@ + #include "r300_reg.h" + #include "r500_reg.h" + #include "r600_reg.h" +- ++#include "evergreen_reg.h" + + #define RADEON_MC_AGP_LOCATION 0x014c + #define RADEON_MC_AGP_START_MASK 0x0000FFFF +diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h +index a1367ab..9506f8c 100644 +--- a/drivers/gpu/drm/radeon/rv770d.h ++++ b/drivers/gpu/drm/radeon/rv770d.h +@@ -343,4 +343,6 @@ + + #define WAIT_UNTIL 0x8040 + ++#define SRBM_STATUS 0x0E50 ++ + #endif +diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h +index e6f3b12..403490c 100644 +--- a/include/drm/drm_pciids.h ++++ b/include/drm/drm_pciids.h +@@ -141,6 +141,41 @@ + {0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x6880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x6888, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x6889, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x688A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x6898, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x6899, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x689c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HEMLOCK|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x689d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HEMLOCK|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x689e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x68a0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x68a1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x68a8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x68a9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x68b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x68b8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x68b9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x68be, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x68c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x68c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x68c8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x68c9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x68d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x68d9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x68da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x68de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x68e0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x68e1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x68e4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x68e5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x68e8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x68e9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x68f1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x68f8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x68f9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \ ++ {0x1002, 0x68fe, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x7100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x7101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ + {0x1002, 0x7102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ diff --git a/debian/patches/features/all/ipheth-add.patch b/debian/patches/features/all/ipheth-add.patch new file mode 100644 index 000000000..9a4a26294 --- /dev/null +++ b/debian/patches/features/all/ipheth-add.patch @@ -0,0 +1,638 @@ +Subject: drivers/net/usb: Add new driver ipheth +Date: Sun, 18 Apr 2010 08:35:16 -0000 +From: Diego Giagio + +Add new driver to use tethering with an iPhone device. After initial submission, +apply fixes to fit the new driver into the kernel standards. + +There are still a couple of minor (almost cosmetic-level) issues, but the driver +is fully functional right now. + +Signed-off-by: L. Alberto Giménez +Signed-off-by: Diego Giagio + +--- + drivers/net/Makefile | 1 + + drivers/net/usb/Kconfig | 12 + + drivers/net/usb/Makefile | 1 + + drivers/net/usb/ipheth.c | 568 ++++++++++++++++++++++++++++++++++++++++++++++ + 4 files changed, 582 insertions(+), 0 deletions(-) + create mode 100644 drivers/net/usb/ipheth.c + +diff --git a/drivers/net/Makefile b/drivers/net/Makefile +index a583b50..12b280a 100644 +--- a/drivers/net/Makefile ++++ b/drivers/net/Makefile +@@ -273,6 +273,7 @@ obj-$(CONFIG_USB_RTL8150) += usb/ + obj-$(CONFIG_USB_HSO) += usb/ + obj-$(CONFIG_USB_USBNET) += usb/ + obj-$(CONFIG_USB_ZD1201) += usb/ ++obj-$(CONFIG_USB_IPHETH) += usb/ + + obj-y += wireless/ + obj-$(CONFIG_NET_TULIP) += tulip/ +diff --git a/drivers/net/usb/Kconfig b/drivers/net/usb/Kconfig +index ba56ce4..63be4ca 100644 +--- a/drivers/net/usb/Kconfig ++++ b/drivers/net/usb/Kconfig +@@ -385,4 +385,16 @@ config USB_CDC_PHONET + cellular modem, as found on most Nokia handsets with the + "PC suite" USB profile. + ++config USB_IPHETH ++ tristate "Apple iPhone USB Ethernet driver" ++ default n ++ ---help--- ++ Module used to share Internet connection (tethering) from your ++ iPhone (Original, 3G and 3GS) to your system. ++ Note that you need userspace libraries and programs that are needed ++ to pair your device with your system and that understand the iPhone ++ protocol. ++ ++ For more information: http://giagio.com/wiki/moin.cgi/iPhoneEthernetDriver ++ + endmenu +diff --git a/drivers/net/usb/Makefile b/drivers/net/usb/Makefile +index 82ea629..edb09c0 100644 +--- a/drivers/net/usb/Makefile ++++ b/drivers/net/usb/Makefile +@@ -23,4 +23,5 @@ obj-$(CONFIG_USB_NET_MCS7830) += mcs7830.o + obj-$(CONFIG_USB_USBNET) += usbnet.o + obj-$(CONFIG_USB_NET_INT51X1) += int51x1.o + obj-$(CONFIG_USB_CDC_PHONET) += cdc-phonet.o ++obj-$(CONFIG_USB_IPHETH) += ipheth.o + +diff --git a/drivers/net/usb/ipheth.c b/drivers/net/usb/ipheth.c +new file mode 100644 +index 0000000..fd10331 +--- /dev/null ++++ b/drivers/net/usb/ipheth.c +@@ -0,0 +1,568 @@ ++/* ++ * ipheth.c - Apple iPhone USB Ethernet driver ++ * ++ * Copyright (c) 2009 Diego Giagio ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. Neither the name of GIAGIO.COM nor the names of its contributors ++ * may be used to endorse or promote products derived from this software ++ * without specific prior written permission. ++ * ++ * Alternatively, provided that this notice is retained in full, this ++ * software may be distributed under the terms of the GNU General ++ * Public License ("GPL") version 2, in which case the provisions of the ++ * GPL apply INSTEAD OF those given above. ++ * ++ * The provided data structures and external interfaces from this code ++ * are not restricted to be used by modules with a GPL compatible license. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ++ * ++ * Attention: iPhone device must be paired, otherwise it won't respond to our ++ * driver. For more info: http://giagio.com/wiki/moin.cgi/iPhoneEthernetDriver ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define USB_VENDOR_APPLE 0x05ac ++#define USB_PRODUCT_IPHONE 0x1290 ++#define USB_PRODUCT_IPHONE_3G 0x1292 ++#define USB_PRODUCT_IPHONE_3GS 0x1294 ++ ++#define IPHETH_USBINTF_CLASS 255 ++#define IPHETH_USBINTF_SUBCLASS 253 ++#define IPHETH_USBINTF_PROTO 1 ++ ++#define IPHETH_BUF_SIZE 1516 ++#define IPHETH_TX_TIMEOUT (5 * HZ) ++ ++#define IPHETH_INTFNUM 2 ++#define IPHETH_ALT_INTFNUM 1 ++ ++#define IPHETH_CTRL_ENDP 0x00 ++#define IPHETH_CTRL_BUF_SIZE 0x40 ++#define IPHETH_CTRL_TIMEOUT (5 * HZ) ++ ++#define IPHETH_CMD_GET_MACADDR 0x00 ++#define IPHETH_CMD_CARRIER_CHECK 0x45 ++ ++#define IPHETH_CARRIER_CHECK_TIMEOUT round_jiffies_relative(1 * HZ) ++#define IPHETH_CARRIER_ON 0x04 ++ ++static struct usb_device_id ipheth_table[] = { ++ { USB_DEVICE_AND_INTERFACE_INFO( ++ USB_VENDOR_APPLE, USB_PRODUCT_IPHONE, ++ IPHETH_USBINTF_CLASS, IPHETH_USBINTF_SUBCLASS, ++ IPHETH_USBINTF_PROTO) }, ++ { USB_DEVICE_AND_INTERFACE_INFO( ++ USB_VENDOR_APPLE, USB_PRODUCT_IPHONE_3G, ++ IPHETH_USBINTF_CLASS, IPHETH_USBINTF_SUBCLASS, ++ IPHETH_USBINTF_PROTO) }, ++ { USB_DEVICE_AND_INTERFACE_INFO( ++ USB_VENDOR_APPLE, USB_PRODUCT_IPHONE_3GS, ++ IPHETH_USBINTF_CLASS, IPHETH_USBINTF_SUBCLASS, ++ IPHETH_USBINTF_PROTO) }, ++ { } ++}; ++MODULE_DEVICE_TABLE(usb, ipheth_table); ++ ++struct ipheth_device { ++ struct usb_device *udev; ++ struct usb_interface *intf; ++ struct net_device *net; ++ struct sk_buff *tx_skb; ++ struct urb *tx_urb; ++ struct urb *rx_urb; ++ unsigned char *tx_buf; ++ unsigned char *rx_buf; ++ unsigned char *ctrl_buf; ++ u8 bulk_in; ++ u8 bulk_out; ++ struct delayed_work carrier_work; ++}; ++ ++static int ipheth_rx_submit(struct ipheth_device *dev, gfp_t mem_flags); ++ ++static int ipheth_alloc_urbs(struct ipheth_device *iphone) ++{ ++ struct urb *tx_urb = NULL; ++ struct urb *rx_urb = NULL; ++ u8 *tx_buf = NULL; ++ u8 *rx_buf = NULL; ++ ++ tx_urb = usb_alloc_urb(0, GFP_KERNEL); ++ if (tx_urb == NULL) ++ goto error; ++ ++ rx_urb = usb_alloc_urb(0, GFP_KERNEL); ++ if (rx_urb == NULL) ++ goto error; ++ ++ tx_buf = usb_buffer_alloc(iphone->udev, ++ IPHETH_BUF_SIZE, ++ GFP_KERNEL, ++ &tx_urb->transfer_dma); ++ if (tx_buf == NULL) ++ goto error; ++ ++ rx_buf = usb_buffer_alloc(iphone->udev, ++ IPHETH_BUF_SIZE, ++ GFP_KERNEL, ++ &rx_urb->transfer_dma); ++ if (rx_buf == NULL) ++ goto error; ++ ++ ++ iphone->tx_urb = tx_urb; ++ iphone->rx_urb = rx_urb; ++ iphone->tx_buf = tx_buf; ++ iphone->rx_buf = rx_buf; ++ return 0; ++ ++error: ++ usb_buffer_free(iphone->udev, IPHETH_BUF_SIZE, rx_buf, ++ rx_urb->transfer_dma); ++ usb_buffer_free(iphone->udev, IPHETH_BUF_SIZE, tx_buf, ++ tx_urb->transfer_dma); ++ usb_free_urb(rx_urb); ++ usb_free_urb(tx_urb); ++ return -ENOMEM; ++} ++ ++static void ipheth_free_urbs(struct ipheth_device *iphone) ++{ ++ usb_buffer_free(iphone->udev, IPHETH_BUF_SIZE, iphone->rx_buf, ++ iphone->rx_urb->transfer_dma); ++ usb_buffer_free(iphone->udev, IPHETH_BUF_SIZE, iphone->tx_buf, ++ iphone->tx_urb->transfer_dma); ++ usb_free_urb(iphone->rx_urb); ++ usb_free_urb(iphone->tx_urb); ++} ++ ++static void ipheth_kill_urbs(struct ipheth_device *dev) ++{ ++ usb_kill_urb(dev->tx_urb); ++ usb_kill_urb(dev->rx_urb); ++} ++ ++static void ipheth_rcvbulk_callback(struct urb *urb) ++{ ++ struct ipheth_device *dev; ++ struct sk_buff *skb; ++ int status; ++ char *buf; ++ int len; ++ ++ dev = urb->context; ++ if (dev == NULL) ++ return; ++ ++ status = urb->status; ++ switch (status) { ++ case -ENOENT: ++ case -ECONNRESET: ++ case -ESHUTDOWN: ++ return; ++ case 0: ++ break; ++ default: ++ err("%s: urb status: %d", __func__, urb->status); ++ return; ++ } ++ ++ len = urb->actual_length; ++ buf = urb->transfer_buffer; ++ ++ skb = dev_alloc_skb(NET_IP_ALIGN + len); ++ if (!skb) { ++ err("%s: dev_alloc_skb: -ENOMEM", __func__); ++ dev->net->stats.rx_dropped++; ++ return; ++ } ++ ++ skb_reserve(skb, NET_IP_ALIGN); ++ memcpy(skb_put(skb, len), buf + NET_IP_ALIGN, len - NET_IP_ALIGN); ++ skb->dev = dev->net; ++ skb->protocol = eth_type_trans(skb, dev->net); ++ ++ dev->net->stats.rx_packets++; ++ dev->net->stats.rx_bytes += len; ++ ++ netif_rx(skb); ++ ipheth_rx_submit(dev, GFP_ATOMIC); ++} ++ ++static void ipheth_sndbulk_callback(struct urb *urb) ++{ ++ struct ipheth_device *dev; ++ ++ dev = urb->context; ++ if (dev == NULL) ++ return; ++ ++ if (urb->status != 0 && ++ urb->status != -ENOENT && ++ urb->status != -ECONNRESET && ++ urb->status != -ESHUTDOWN) ++ err("%s: urb status: %d", __func__, urb->status); ++ ++ dev_kfree_skb_irq(dev->tx_skb); ++ netif_wake_queue(dev->net); ++} ++ ++static int ipheth_carrier_set(struct ipheth_device *dev) ++{ ++ struct usb_device *udev = dev->udev; ++ int retval; ++ ++ retval = usb_control_msg(udev, ++ usb_rcvctrlpipe(udev, IPHETH_CTRL_ENDP), ++ IPHETH_CMD_CARRIER_CHECK, /* request */ ++ 0xc0, /* request type */ ++ 0x00, /* value */ ++ 0x02, /* index */ ++ dev->ctrl_buf, IPHETH_CTRL_BUF_SIZE, ++ IPHETH_CTRL_TIMEOUT); ++ if (retval < 0) { ++ err("%s: usb_control_msg: %d", __func__, retval); ++ return retval; ++ } ++ ++ if (dev->ctrl_buf[0] == IPHETH_CARRIER_ON) ++ netif_carrier_on(dev->net); ++ else ++ netif_carrier_off(dev->net); ++ ++ return 0; ++} ++ ++static void ipheth_carrier_check_work(struct work_struct *work) ++{ ++ struct ipheth_device *dev = container_of(work, struct ipheth_device, ++ carrier_work.work); ++ ++ ipheth_carrier_set(dev); ++ schedule_delayed_work(&dev->carrier_work, IPHETH_CARRIER_CHECK_TIMEOUT); ++} ++ ++static int ipheth_get_macaddr(struct ipheth_device *dev) ++{ ++ struct usb_device *udev = dev->udev; ++ struct net_device *net = dev->net; ++ int retval; ++ ++ retval = usb_control_msg(udev, ++ usb_rcvctrlpipe(udev, IPHETH_CTRL_ENDP), ++ IPHETH_CMD_GET_MACADDR, /* request */ ++ 0xc0, /* request type */ ++ 0x00, /* value */ ++ 0x02, /* index */ ++ dev->ctrl_buf, ++ IPHETH_CTRL_BUF_SIZE, ++ IPHETH_CTRL_TIMEOUT); ++ if (retval < 0) { ++ err("%s: usb_control_msg: %d", __func__, retval); ++ } else if (retval < ETH_ALEN) { ++ err("%s: usb_control_msg: short packet: %d bytes", ++ __func__, retval); ++ retval = -EINVAL; ++ } else { ++ memcpy(net->dev_addr, dev->ctrl_buf, ETH_ALEN); ++ retval = 0; ++ } ++ ++ return retval; ++} ++ ++static int ipheth_rx_submit(struct ipheth_device *dev, gfp_t mem_flags) ++{ ++ struct usb_device *udev = dev->udev; ++ int retval; ++ ++ usb_fill_bulk_urb(dev->rx_urb, udev, ++ usb_rcvbulkpipe(udev, dev->bulk_in), ++ dev->rx_buf, IPHETH_BUF_SIZE, ++ ipheth_rcvbulk_callback, ++ dev); ++ dev->rx_urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; ++ ++ retval = usb_submit_urb(dev->rx_urb, mem_flags); ++ if (retval) ++ err("%s: usb_submit_urb: %d", __func__, retval); ++ return retval; ++} ++ ++static int ipheth_open(struct net_device *net) ++{ ++ struct ipheth_device *dev = netdev_priv(net); ++ struct usb_device *udev = dev->udev; ++ int retval = 0; ++ ++ usb_set_interface(udev, IPHETH_INTFNUM, IPHETH_ALT_INTFNUM); ++ ++ retval = ipheth_carrier_set(dev); ++ if (retval) ++ return retval; ++ ++ retval = ipheth_rx_submit(dev, GFP_KERNEL); ++ if (retval) ++ return retval; ++ ++ schedule_delayed_work(&dev->carrier_work, IPHETH_CARRIER_CHECK_TIMEOUT); ++ netif_start_queue(net); ++ return retval; ++} ++ ++static int ipheth_close(struct net_device *net) ++{ ++ struct ipheth_device *dev = netdev_priv(net); ++ ++ cancel_delayed_work_sync(&dev->carrier_work); ++ netif_stop_queue(net); ++ return 0; ++} ++ ++static int ipheth_tx(struct sk_buff *skb, struct net_device *net) ++{ ++ struct ipheth_device *dev = netdev_priv(net); ++ struct usb_device *udev = dev->udev; ++ int retval; ++ ++ /* Paranoid */ ++ if (skb->len > IPHETH_BUF_SIZE) { ++ WARN(1, "%s: skb too large: %d bytes", __func__, skb->len); ++ dev->net->stats.tx_dropped++; ++ dev_kfree_skb_irq(skb); ++ return NETDEV_TX_OK; ++ } ++ ++ memcpy(dev->tx_buf, skb->data, skb->len); ++ if (skb->len < IPHETH_BUF_SIZE) ++ memset(dev->tx_buf + skb->len, 0, IPHETH_BUF_SIZE - skb->len); ++ ++ usb_fill_bulk_urb(dev->tx_urb, udev, ++ usb_sndbulkpipe(udev, dev->bulk_out), ++ dev->tx_buf, IPHETH_BUF_SIZE, ++ ipheth_sndbulk_callback, ++ dev); ++ dev->tx_urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; ++ ++ retval = usb_submit_urb(dev->tx_urb, GFP_ATOMIC); ++ if (retval) { ++ err("%s: usb_submit_urb: %d", __func__, retval); ++ dev->net->stats.tx_errors++; ++ dev_kfree_skb_irq(skb); ++ } else { ++ dev->tx_skb = skb; ++ ++ dev->net->stats.tx_packets++; ++ dev->net->stats.tx_bytes += skb->len; ++ netif_stop_queue(net); ++ } ++ ++ return NETDEV_TX_OK; ++} ++ ++static void ipheth_tx_timeout(struct net_device *net) ++{ ++ struct ipheth_device *dev = netdev_priv(net); ++ ++ err("%s: TX timeout", __func__); ++ dev->net->stats.tx_errors++; ++ usb_unlink_urb(dev->tx_urb); ++} ++ ++static struct net_device_stats *ipheth_stats(struct net_device *net) ++{ ++ struct ipheth_device *dev = netdev_priv(net); ++ return &dev->net->stats; ++} ++ ++static u32 ipheth_ethtool_op_get_link(struct net_device *net) ++{ ++ struct ipheth_device *dev = netdev_priv(net); ++ return netif_carrier_ok(dev->net); ++} ++ ++static struct ethtool_ops ops = { ++ .get_link = ipheth_ethtool_op_get_link ++}; ++ ++static const struct net_device_ops ipheth_netdev_ops = { ++ .ndo_open = &ipheth_open, ++ .ndo_stop = &ipheth_close, ++ .ndo_start_xmit = &ipheth_tx, ++ .ndo_tx_timeout = &ipheth_tx_timeout, ++ .ndo_get_stats = &ipheth_stats, ++}; ++ ++static struct device_type ipheth_type = { ++ .name = "wwan", ++}; ++ ++static int ipheth_probe(struct usb_interface *intf, ++ const struct usb_device_id *id) ++{ ++ struct usb_device *udev = interface_to_usbdev(intf); ++ struct usb_host_interface *hintf; ++ struct usb_endpoint_descriptor *endp; ++ struct ipheth_device *dev; ++ struct net_device *netdev; ++ int i; ++ int retval; ++ ++ netdev = alloc_etherdev(sizeof(struct ipheth_device)); ++ if (!netdev) ++ return -ENOMEM; ++ ++ netdev->netdev_ops = &ipheth_netdev_ops; ++ netdev->watchdog_timeo = IPHETH_TX_TIMEOUT; ++ strcpy(netdev->name, "wwan%d"); ++ ++ dev = netdev_priv(netdev); ++ dev->udev = udev; ++ dev->net = netdev; ++ dev->intf = intf; ++ ++ /* Set up endpoints */ ++ hintf = usb_altnum_to_altsetting(intf, IPHETH_ALT_INTFNUM); ++ if (hintf == NULL) { ++ retval = -ENODEV; ++ err("Unable to find alternate settings interface"); ++ goto err_endpoints; ++ } ++ ++ for (i = 0; i < hintf->desc.bNumEndpoints; i++) { ++ endp = &hintf->endpoint[i].desc; ++ if (usb_endpoint_is_bulk_in(endp)) ++ dev->bulk_in = endp->bEndpointAddress; ++ else if (usb_endpoint_is_bulk_out(endp)) ++ dev->bulk_out = endp->bEndpointAddress; ++ } ++ if (!(dev->bulk_in && dev->bulk_out)) { ++ retval = -ENODEV; ++ err("Unable to find endpoints"); ++ goto err_endpoints; ++ } ++ ++ dev->ctrl_buf = kmalloc(IPHETH_CTRL_BUF_SIZE, GFP_KERNEL); ++ if (dev->ctrl_buf == NULL) { ++ retval = -ENOMEM; ++ goto err_alloc_ctrl_buf; ++ } ++ ++ retval = ipheth_get_macaddr(dev); ++ if (retval) ++ goto err_get_macaddr; ++ ++ INIT_DELAYED_WORK(&dev->carrier_work, ipheth_carrier_check_work); ++ ++ retval = ipheth_alloc_urbs(dev); ++ if (retval) { ++ err("error allocating urbs: %d", retval); ++ goto err_alloc_urbs; ++ } ++ ++ usb_set_intfdata(intf, dev); ++ ++ SET_NETDEV_DEV(netdev, &intf->dev); ++ SET_ETHTOOL_OPS(netdev, &ops); ++ SET_NETDEV_DEVTYPE(netdev, &ipheth_type); ++ ++ retval = register_netdev(netdev); ++ if (retval) { ++ err("error registering netdev: %d", retval); ++ retval = -EIO; ++ goto err_register_netdev; ++ } ++ ++ dev_info(&intf->dev, "Apple iPhone USB Ethernet device attached\n"); ++ return 0; ++ ++err_register_netdev: ++ ipheth_free_urbs(dev); ++err_alloc_urbs: ++err_get_macaddr: ++err_alloc_ctrl_buf: ++ kfree(dev->ctrl_buf); ++err_endpoints: ++ free_netdev(netdev); ++ return retval; ++} ++ ++static void ipheth_disconnect(struct usb_interface *intf) ++{ ++ struct ipheth_device *dev; ++ ++ dev = usb_get_intfdata(intf); ++ if (dev != NULL) { ++ unregister_netdev(dev->net); ++ ipheth_kill_urbs(dev); ++ ipheth_free_urbs(dev); ++ kfree(dev->ctrl_buf); ++ free_netdev(dev->net); ++ } ++ usb_set_intfdata(intf, NULL); ++ dev_info(&intf->dev, "Apple iPhone USB Ethernet now disconnected\n"); ++} ++ ++static struct usb_driver ipheth_driver = { ++ .name = "ipheth", ++ .probe = ipheth_probe, ++ .disconnect = ipheth_disconnect, ++ .id_table = ipheth_table, ++}; ++ ++static int __init ipheth_init(void) ++{ ++ int retval; ++ ++ retval = usb_register(&ipheth_driver); ++ if (retval) { ++ err("usb_register failed: %d", retval); ++ return retval; ++ } ++ return 0; ++} ++ ++static void __exit ipheth_exit(void) ++{ ++ usb_deregister(&ipheth_driver); ++} ++ ++module_init(ipheth_init); ++module_exit(ipheth_exit); ++ ++MODULE_AUTHOR("Diego Giagio "); ++MODULE_DESCRIPTION("Apple iPhone USB Ethernet driver"); ++MODULE_LICENSE("Dual BSD/GPL"); diff --git a/debian/patches/features/all/phylib-Add-module-table-to-all-existing-phy-drivers.patch b/debian/patches/features/all/phylib-Add-module-table-to-all-existing-phy-drivers.patch new file mode 100644 index 000000000..afb4c17b7 --- /dev/null +++ b/debian/patches/features/all/phylib-Add-module-table-to-all-existing-phy-drivers.patch @@ -0,0 +1,266 @@ +From 4e4f10f6498bc5038c0a110b5f21682fcb5578d7 Mon Sep 17 00:00:00 2001 +From: David Woodhouse +Date: Fri, 2 Apr 2010 01:05:56 +0000 +Subject: [PATCH 2/2] phylib: Add module table to all existing phy drivers + +Signed-off-by: David Woodhouse +Signed-off-by: David S. Miller +--- + drivers/net/phy/bcm63xx.c | 8 ++++++++ + drivers/net/phy/broadcom.c | 16 ++++++++++++++++ + drivers/net/phy/cicada.c | 8 ++++++++ + drivers/net/phy/davicom.c | 9 +++++++++ + drivers/net/phy/et1011c.c | 7 +++++++ + drivers/net/phy/icplus.c | 7 +++++++ + drivers/net/phy/lxt.c | 8 ++++++++ + drivers/net/phy/marvell.c | 13 +++++++++++++ + drivers/net/phy/national.c | 7 +++++++ + drivers/net/phy/qsemi.c | 7 +++++++ + drivers/net/phy/realtek.c | 7 +++++++ + drivers/net/phy/smsc.c | 11 +++++++++++ + drivers/net/phy/ste10Xp.c | 8 ++++++++ + drivers/net/phy/vitesse.c | 8 ++++++++ + 14 files changed, 124 insertions(+), 0 deletions(-) + +diff --git a/drivers/net/phy/bcm63xx.c b/drivers/net/phy/bcm63xx.c +index 4fed95e..ac5e498 100644 +--- a/drivers/net/phy/bcm63xx.c ++++ b/drivers/net/phy/bcm63xx.c +@@ -130,3 +130,11 @@ static void __exit bcm63xx_phy_exit(void) + + module_init(bcm63xx_phy_init); + module_exit(bcm63xx_phy_exit); ++ ++static struct mdio_device_id bcm63xx_tbl[] = { ++ { 0x00406000, 0xfffffc00 }, ++ { 0x002bdc00, 0xfffffc00 }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(mdio, bcm64xx_tbl); +diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c +index f482fc4..cecdbbd 100644 +--- a/drivers/net/phy/broadcom.c ++++ b/drivers/net/phy/broadcom.c +@@ -908,3 +908,19 @@ static void __exit broadcom_exit(void) + + module_init(broadcom_init); + module_exit(broadcom_exit); ++ ++static struct mdio_device_id broadcom_tbl[] = { ++ { 0x00206070, 0xfffffff0 }, ++ { 0x002060e0, 0xfffffff0 }, ++ { 0x002060c0, 0xfffffff0 }, ++ { 0x002060b0, 0xfffffff0 }, ++ { 0x0143bca0, 0xfffffff0 }, ++ { 0x0143bcb0, 0xfffffff0 }, ++ { PHY_ID_BCM50610, 0xfffffff0 }, ++ { PHY_ID_BCM50610M, 0xfffffff0 }, ++ { PHY_ID_BCM57780, 0xfffffff0 }, ++ { PHY_ID_BCMAC131, 0xfffffff0 }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(mdio, broadcom_tbl); +diff --git a/drivers/net/phy/cicada.c b/drivers/net/phy/cicada.c +index a1bd599..efc608f 100644 +--- a/drivers/net/phy/cicada.c ++++ b/drivers/net/phy/cicada.c +@@ -159,3 +159,11 @@ static void __exit cicada_exit(void) + + module_init(cicada_init); + module_exit(cicada_exit); ++ ++static struct mdio_device_id cicada_tbl[] = { ++ { 0x000fc410, 0x000ffff0 }, ++ { 0x000fc440, 0x000fffc0 }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(mdio, cicada_tbl); +diff --git a/drivers/net/phy/davicom.c b/drivers/net/phy/davicom.c +index d926168..e02b18c 100644 +--- a/drivers/net/phy/davicom.c ++++ b/drivers/net/phy/davicom.c +@@ -219,3 +219,12 @@ static void __exit davicom_exit(void) + + module_init(davicom_init); + module_exit(davicom_exit); ++ ++static struct mdio_device_id davicom_tbl[] = { ++ { 0x0181b880, 0x0ffffff0 }, ++ { 0x0181b8a0, 0x0ffffff0 }, ++ { 0x00181b80, 0x0ffffff0 }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(mdio, davicom_tbl); +diff --git a/drivers/net/phy/et1011c.c b/drivers/net/phy/et1011c.c +index b031fa2..500f0fd 100644 +--- a/drivers/net/phy/et1011c.c ++++ b/drivers/net/phy/et1011c.c +@@ -111,3 +111,10 @@ static void __exit et1011c_exit(void) + + module_init(et1011c_init); + module_exit(et1011c_exit); ++ ++static struct mdio_device_id et1011c_tbl[] = { ++ { 0x0282f014, 0xfffffff0 }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(mdio, et1011c_tbl); +diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c +index af3f1f2..e661e90 100644 +--- a/drivers/net/phy/icplus.c ++++ b/drivers/net/phy/icplus.c +@@ -132,3 +132,10 @@ static void __exit ip175c_exit(void) + + module_init(ip175c_init); + module_exit(ip175c_exit); ++ ++static struct mdio_device_id icplus_tbl[] = { ++ { 0x02430d80, 0x0ffffff0 }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(mdio, icplus_tbl); +diff --git a/drivers/net/phy/lxt.c b/drivers/net/phy/lxt.c +index 4cf3324..1d94f1d 100644 +--- a/drivers/net/phy/lxt.c ++++ b/drivers/net/phy/lxt.c +@@ -174,3 +174,11 @@ static void __exit lxt_exit(void) + + module_init(lxt_init); + module_exit(lxt_exit); ++ ++static struct mdio_device_id lxt_tbl[] = { ++ { 0x78100000, 0xfffffff0 }, ++ { 0x001378e0, 0xfffffff0 }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(mdio, lxt_tbl); +diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c +index 65ed385..c7e5b9f 100644 +--- a/drivers/net/phy/marvell.c ++++ b/drivers/net/phy/marvell.c +@@ -649,3 +649,16 @@ static void __exit marvell_exit(void) + + module_init(marvell_init); + module_exit(marvell_exit); ++ ++static struct mdio_device_id marvell_tbl[] = { ++ { 0x01410c60, 0xfffffff0 }, ++ { 0x01410c90, 0xfffffff0 }, ++ { 0x01410cc0, 0xfffffff0 }, ++ { 0x01410e10, 0xfffffff0 }, ++ { 0x01410cb0, 0xfffffff0 }, ++ { 0x01410cd0, 0xfffffff0 }, ++ { 0x01410e30, 0xfffffff0 }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(mdio, marvell_tbl); +diff --git a/drivers/net/phy/national.c b/drivers/net/phy/national.c +index 6c636eb..729ab29 100644 +--- a/drivers/net/phy/national.c ++++ b/drivers/net/phy/national.c +@@ -153,3 +153,10 @@ MODULE_LICENSE("GPL"); + + module_init(ns_init); + module_exit(ns_exit); ++ ++static struct mdio_device_id ns_tbl[] = { ++ { DP83865_PHY_ID, 0xfffffff0 }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(mdio, ns_tbl); +diff --git a/drivers/net/phy/qsemi.c b/drivers/net/phy/qsemi.c +index 23062d0..3ec9610 100644 +--- a/drivers/net/phy/qsemi.c ++++ b/drivers/net/phy/qsemi.c +@@ -138,3 +138,10 @@ static void __exit qs6612_exit(void) + + module_init(qs6612_init); + module_exit(qs6612_exit); ++ ++static struct mdio_device_id qs6612_tbl[] = { ++ { 0x00181440, 0xfffffff0 }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(mdio, qs6612_tbl); +diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c +index a052a67..f567c0e 100644 +--- a/drivers/net/phy/realtek.c ++++ b/drivers/net/phy/realtek.c +@@ -78,3 +78,10 @@ static void __exit realtek_exit(void) + + module_init(realtek_init); + module_exit(realtek_exit); ++ ++static struct mdio_device_id realtek_tbl[] = { ++ { 0x001cc912, 0x001fffff }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(mdio, realtek_tbl); +diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c +index ed2644a..78fa988 100644 +--- a/drivers/net/phy/smsc.c ++++ b/drivers/net/phy/smsc.c +@@ -253,3 +253,14 @@ MODULE_LICENSE("GPL"); + + module_init(smsc_init); + module_exit(smsc_exit); ++ ++static struct mdio_device_id smsc_tbl[] = { ++ { 0x0007c0a0, 0xfffffff0 }, ++ { 0x0007c0b0, 0xfffffff0 }, ++ { 0x0007c0c0, 0xfffffff0 }, ++ { 0x0007c0d0, 0xfffffff0 }, ++ { 0x0007c0f0, 0xfffffff0 }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(mdio, smsc_tbl); +diff --git a/drivers/net/phy/ste10Xp.c b/drivers/net/phy/ste10Xp.c +index 6bdb0d5..7229009 100644 +--- a/drivers/net/phy/ste10Xp.c ++++ b/drivers/net/phy/ste10Xp.c +@@ -132,6 +132,14 @@ static void __exit ste10Xp_exit(void) + module_init(ste10Xp_init); + module_exit(ste10Xp_exit); + ++static struct mdio_device_id ste10Xp_tbl[] = { ++ { STE101P_PHY_ID, 0xfffffff0 }, ++ { STE100P_PHY_ID, 0xffffffff }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(mdio, ste10Xp_tbl); ++ + MODULE_DESCRIPTION("STMicroelectronics STe10Xp PHY driver"); + MODULE_AUTHOR("Giuseppe Cavallaro "); + MODULE_LICENSE("GPL"); +diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c +index dd3b244..45cce50 100644 +--- a/drivers/net/phy/vitesse.c ++++ b/drivers/net/phy/vitesse.c +@@ -191,3 +191,11 @@ static void __exit vsc82xx_exit(void) + + module_init(vsc82xx_init); + module_exit(vsc82xx_exit); ++ ++static struct mdio_device_id vitesse_tbl[] = { ++ { PHY_ID_VSC8244, 0x000fffc0 }, ++ { PHY_ID_VSC8221, 0x000ffff0 }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(mdio, vitesse_tbl); +-- +1.7.0.3 + diff --git a/debian/patches/features/all/phylib-Support-phy-module-autoloading.patch b/debian/patches/features/all/phylib-Support-phy-module-autoloading.patch new file mode 100644 index 000000000..ab5410093 --- /dev/null +++ b/debian/patches/features/all/phylib-Support-phy-module-autoloading.patch @@ -0,0 +1,53 @@ +From 8626d3b4328061f5b82b11ae1d6918a0c3602f42 Mon Sep 17 00:00:00 2001 +From: David Woodhouse +Date: Fri, 2 Apr 2010 01:05:27 +0000 +Subject: [PATCH 1/2] phylib: Support phy module autoloading + +We don't use the normal hotplug mechanism because it doesn't work. It will +load the module some time after the device appears, but that's not good +enough for us -- we need the driver loaded _immediately_ because otherwise +the NIC driver may just abort and then the phy 'device' goes away. + +[bwh: s/phy/mdio/ in module alias, kerneldoc for struct mdio_device_id] + +Signed-off-by: David Woodhouse +Signed-off-by: Ben Hutchings +Acked-by: Andy Fleming +Signed-off-by: David S. Miller +--- + drivers/net/phy/phy_device.c | 12 ++++++++++++ + 1 files changed, 12 insertions(+), 0 deletions(-) + +diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c +index db17945..1a99bb2 100644 +--- a/drivers/net/phy/phy_device.c ++++ b/drivers/net/phy/phy_device.c +@@ -149,6 +149,7 @@ EXPORT_SYMBOL(phy_scan_fixups); + struct phy_device* phy_device_create(struct mii_bus *bus, int addr, int phy_id) + { + struct phy_device *dev; ++ + /* We allocate the device, and initialize the + * default values */ + dev = kzalloc(sizeof(*dev), GFP_KERNEL); +@@ -179,6 +180,17 @@ struct phy_device* phy_device_create(struct mii_bus *bus, int addr, int phy_id) + mutex_init(&dev->lock); + INIT_DELAYED_WORK(&dev->state_queue, phy_state_machine); + ++ /* Request the appropriate module unconditionally; don't ++ bother trying to do so only if it isn't already loaded, ++ because that gets complicated. A hotplug event would have ++ done an unconditional modprobe anyway. ++ We don't do normal hotplug because it won't work for MDIO ++ -- because it relies on the device staying around for long ++ enough for the driver to get loaded. With MDIO, the NIC ++ driver will get bored and give up as soon as it finds that ++ there's no driver _already_ loaded. */ ++ request_module(MDIO_MODULE_PREFIX MDIO_ID_FMT, MDIO_ID_ARGS(phy_id)); ++ + return dev; + } + EXPORT_SYMBOL(phy_device_create); +-- +1.7.0.3 + diff --git a/debian/patches/features/arm/dns323-rev-a1-gpio-request.patch b/debian/patches/features/arm/dns323-rev-a1-gpio-request.patch new file mode 100644 index 000000000..dd264fe0a --- /dev/null +++ b/debian/patches/features/arm/dns323-rev-a1-gpio-request.patch @@ -0,0 +1,31 @@ +From: Arnaud Patard +Date: Sat, 3 Apr 2010 08:31:33 +0000 (+0200) +Subject: [ARM] dns323-setup.c: fix WARN() when booting +X-Git-Url: http://git.marvell.com/?p=orion.git;a=commitdiff_plain;h=5efda86f74aa62f589297d0638c400b3f3fc6c64 + +[ARM] dns323-setup.c: fix WARN() when booting + +Since commit b2a731aa5cbca7e0252da75e16de7ae5feb1313a, dns323_init() is +setting the power led gpio direction with gpio_direction_output() but +doesn't request the gpio before (which is not permitted by the gpio +layer afaik). This behaviour is triggering a WARN() at boot time. + +Tested-by: Christian Samsel +Cc: Martin Michlmayr +Signed-off-by: Arnaud Patard +Signed-off-by: Nicolas Pitre + [ Part 2: "Attached Text" ] +--- + +diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c +index 421b82f..685f34a 100644 +--- a/arch/arm/mach-orion5x/dns323-setup.c ++++ b/arch/arm/mach-orion5x/dns323-setup.c +@@ -439,6 +439,7 @@ static void __init dns323_init(void) + */ + if (dns323_dev_id() == MV88F5181_DEV_ID) { + dns323_leds[0].active_low = 1; ++ gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable"); + gpio_direction_output(DNS323_GPIO_LED_POWER1, 0); + } + diff --git a/debian/patches/series/base b/debian/patches/series/base index a72bb129d..c9d24c66d 100644 --- a/debian/patches/series/base +++ b/debian/patches/series/base @@ -59,3 +59,38 @@ + debian/arch-sh4-fix-uimage-build.patch + bugfix/all/stable/2.6.33.3.patch + ++ features/all/phylib-Support-phy-module-autoloading.patch ++ features/all/phylib-Add-module-table-to-all-existing-phy-drivers.patch + ++ bugfix/x86/PCI-Disable-MSI-for-MCP55-on-P5N32-E-SLI.patch ++ bugfix/all/phylib-fix-typo-in-bcm6xx-PHY-driver-table.patch ++ features/arm/dns323-rev-a1-gpio-request.patch ++ bugfix/all/drm-i915-Stop-trying-to-use-ACPI-lid-status-to-deter.patch ++ bugfix/all/forcedeth-fix-tx-limit2-flag-check.patch ++ bugfix/all/reiserfs-fix-permissions-on-reiserfs_priv.patch ++ bugfix/all/libata-ata_piix-clear-spurious-IRQ.patch ++ bugfix/all/block-blk_abort_request-lock-fix.patch ++ bugfix/mips/enable-pata-platform.patch ++ bugfix/all/rndis_host-Poll-status-channel-before-control-channel.patch ++ features/all/ipheth-add.patch ++ bugfix/all/ipheth-potential-null-dereferences-on-error-path.patch ++ bugfix/all/libata-fix-accesses-at-LBA28-boundary.patch ++ bugfix/all/thinkpad-acpi-add-x100e.patch ++ features/all/drm-radeon-evergreen.patch ++ bugfix/all/drm-radeon-kms-further-spread-spectrum-fixes.patch ++ bugfix/all/p54pci-move-tx-cleanup-into-tasklet.patch ++ bugfix/all/p54pci-revise-tx-locking.patch ++ bugfix/all/p54usb-Add-usbid-for-Corega-CG-WLUSB2GT.patch ++ bugfix/all/drivers-net-wireless-p54-txrx.c-Fix-off-by-one-error.patch ++ bugfix/all/p54pci-prevent-stuck-rx-ring.patch ++ bugfix/all/p54pci-fix-serious-sparse-warning.patch ++ bugfix/all/p54pci-fix-bugs-in-p54p_check_tx_ring.patch ++ bugfix/all/p54pci-fix-regression.patch ++ bugfix/all/hugetlb-fix-infinite-loop-in-get_futex_key-when-backed-by-huge-pages.patch ++ bugfix/all/ext4-issue-discard-operation-before-releasing-blocks.patch ++ bugfix/all/libiscsi-regression-fix-header-digest-errors.patch ++ bugfix/all/sctp-fix-skb_over_panic-resulting-from-multiple-invalid-parameter-errors.patch ++ bugfix/all/cifs-allow-null-nd-on-create.patch ++ bugfix/all/tipc-fix-oops-on-send-prior-to-entering-networked-mode.patch ++ bugfix/powerpc/kgdb-dont-needlessly-skip-PAGE_USER-test-for-Fsl-booke.patch diff --git a/debian/templates/control.main.in b/debian/templates/control.main.in index ee290fa13..261ee2b07 100644 --- a/debian/templates/control.main.in +++ b/debian/templates/control.main.in @@ -79,7 +79,8 @@ Description: Support files for Linux @upstreamversion@ Package: linux-base Architecture: all -Depends: libapt-pkg-perl, libuuid-perl, ${misc:Depends} +Depends: libapt-pkg-perl, libuuid-perl, ${misc:Depends}, + util-linux (>= 2.16-1) | udev (<< 146-1) Description: Linux image base package This package contains files and support scripts for all Linux images. diff --git a/debian/templates/temp.image.plain/postrm b/debian/templates/temp.image.plain/postrm index 23cd777d3..912b4d06c 100755 --- a/debian/templates/temp.image.plain/postrm +++ b/debian/templates/temp.image.plain/postrm @@ -315,6 +315,7 @@ my @files_to_remove = qw{ modules.symbols build source modules.ofmap modules.seriomap modules.alias.bin modules.dep.bin modules.symbols.bin + modules.softdep }; foreach my $extra_file (@files_to_remove) {