diff --git a/debian/changelog b/debian/changelog index 9d2d45991..f01265843 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,3 +1,9 @@ +linux-2.6 (2.6.29-4) unstable; urgency=low + + * drm/i915: allow tiled front buffers on 965+. + + -- maximilian attems Fri, 17 Apr 2009 11:30:55 +0200 + linux-2.6 (2.6.29-3) unstable; urgency=low [ maximilian attems ] diff --git a/debian/patches/bugfix/all/drm-intel.git-f544847fbaf099278343f875987a983f2b913134.patch b/debian/patches/bugfix/all/drm-intel.git-f544847fbaf099278343f875987a983f2b913134.patch new file mode 100644 index 000000000..0db842e37 --- /dev/null +++ b/debian/patches/bugfix/all/drm-intel.git-f544847fbaf099278343f875987a983f2b913134.patch @@ -0,0 +1,65 @@ +From: Jesse Barnes +Date: Tue, 14 Apr 2009 21:17:47 +0000 (-0700) +Subject: drm/i915: allow tiled front buffers on 965+ +X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fanholt%2Fdrm-intel.git;a=commitdiff_plain;h=f544847fbaf099278343f875987a983f2b913134;hp=cd97824994042b809493807ea644ba26c0c23290 + +drm/i915: allow tiled front buffers on 965+ + +This patch corrects a pretty big oversight in the KMS code for 965+ +chips. The current code is missing tiled surface register programming, +so userland can allocate a tiled surface and use it for mode setting, +resulting in corruption. This patch fixes that, allowing for tiled +front buffers on 965+. + +Cc: stable@kernel.org +Tested-by: Arkadiusz Miskiewicz +Signed-off-by: Jesse Barnes +Signed-off-by: Eric Anholt +--- + +diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h +index e805b59..5211947 100644 +--- a/drivers/gpu/drm/i915/i915_reg.h ++++ b/drivers/gpu/drm/i915/i915_reg.h +@@ -1446,6 +1446,7 @@ + #define DISPPLANE_NO_LINE_DOUBLE 0 + #define DISPPLANE_STEREO_POLARITY_FIRST 0 + #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) ++#define DISPPLANE_TILED (1<<10) + #define DSPAADDR 0x70184 + #define DSPASTRIDE 0x70188 + #define DSPAPOS 0x7018C /* reserved */ +diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c +index c2c8e95..bdcda36 100644 +--- a/drivers/gpu/drm/i915/intel_display.c ++++ b/drivers/gpu/drm/i915/intel_display.c +@@ -657,6 +657,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, + int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR); + int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF); + int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE; ++ int dsptileoff = (pipe == 0 ? DSPATILEOFF : DSPBTILEOFF); + int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; + u32 dspcntr, alignment; + int ret; +@@ -733,6 +734,13 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, + mutex_unlock(&dev->struct_mutex); + return -EINVAL; + } ++ if (IS_I965G(dev)) { ++ if (obj_priv->tiling_mode != I915_TILING_NONE) ++ dspcntr |= DISPPLANE_TILED; ++ else ++ dspcntr &= ~DISPPLANE_TILED; ++ } ++ + I915_WRITE(dspcntr_reg, dspcntr); + + Start = obj_priv->gtt_offset; +@@ -745,6 +753,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, + I915_READ(dspbase); + I915_WRITE(dspsurf, Start); + I915_READ(dspsurf); ++ I915_WRITE(dsptileoff, (y << 16) | x); + } else { + I915_WRITE(dspbase, Start + Offset); + I915_READ(dspbase); diff --git a/debian/patches/series/4 b/debian/patches/series/4 new file mode 100644 index 000000000..ee0ce5b06 --- /dev/null +++ b/debian/patches/series/4 @@ -0,0 +1 @@ ++ bugfix/all/drm-intel.git-f544847fbaf099278343f875987a983f2b913134.patch