Bump ABI to 2

Commit 1df9e416e647 "Kbuild: always define endianess in kconfig.h"
fixed several cases where some types (and inline functions) might not
be correctly defined according to the host byte order.  It might be
possible to avoid an ABI bump, but it would require a lot of work.
Also, the problem may affect OOT modules that therefore should be
rebuilt with the fix.

debian/changelog

@@ -395,13 +395,6 @@ linux (4.15.9-1) UNRELEASED; urgency=medium
   * firmware_class: Refer to Debian wiki page when logging missing firmware
     (Closes: #888405)
   * nospec: Kill array_index_nospec_mask_check()
-  * [x86] cpu: Avoid ABI change in 4.15.5
-  * [x86] Revert "x86/cpu: Rename cpu_data.x86_mask to cpu_data.x86_stepping"
-    to avoid an ABI change
-  * [x86] Revert "x86/mm: Rename flush_tlb_single() and flush_tlb_one() to
-    __flush_tlb_one_[user|kernel]()" to avoid an ABI change
-  * [x86] Revert "x86/debug: Use UD2 for WARN()" to avoid an ABI change
-  * drm/atomic: Avoid ABI change in 4.15.7
   * amdgpu: Abort probing if firmware is not installed, as we do in radeon
 
   [ Uwe Kleine-König ]

debian/config/defines

@@ -65,8 +65,6 @@ ignore-changes:
  debugfs_create_automount
 # ignore changes to inv_mpu6050/*
  module:drivers/iio/imu/inv_mpu6050/*
-# Exported for KVM only
- __ibp_barrier
 
 [base]
 arches:

debian/patches/debian/drm-atomic-avoid-abi-change-in-4.15.7.patch

@@ -1,29 +0,0 @@
-From: Ben Hutchings <ben@decadent.org.uk>
-Date: Wed, 14 Mar 2018 01:09:10 +0000
-Subject: drm/atomic: Avoid ABI change in 4.15.7
-Forwarded: not-needed
-
-The new field drm_crtc_commit::abort_completion is only used in
-drm_atomic_helper.c, which is the same place the structure is
-allocated.  Therefore we can safely hide it from genksyms and
-avoid an ABI change.
-
----
---- a/include/drm/drm_atomic.h
-+++ b/include/drm/drm_atomic.h
-@@ -135,6 +135,7 @@ struct drm_crtc_commit {
- 	 */
- 	struct drm_pending_vblank_event *event;
- 
-+#ifndef __GENKSYMS__
- 	/**
- 	 * @abort_completion:
- 	 *
-@@ -143,6 +144,7 @@ struct drm_crtc_commit {
- 	 * the free code to remove the second reference if commit fails.
- 	 */
- 	bool abort_completion;
-+#endif
- };
- 
- struct __drm_planes_state {

debian/patches/debian/revert-x86-cpu-rename-cpu_data.x86_mask-to-cpu_data..patch

@@ -1,792 +0,0 @@
-From: Ben Hutchings <ben@decadent.org.uk>
-Date: Wed, 14 Mar 2018 00:48:34 +0000
-Subject: Revert "x86/cpu: Rename cpu_data.x86_mask to cpu_data.x86_stepping"
-Forwarded: not-needed
-
-This reverts commit 7d6446416778e695ddba589a25aa2dabcaba5d2d, which
-was commit b399151cb48db30ad1e0e93dd40d68c6d007b637 upstream.  This
-is an unnecessary ABI change.
----
- arch/x86/events/intel/core.c          |  2 +-
- arch/x86/events/intel/lbr.c           |  2 +-
- arch/x86/events/intel/p6.c            |  2 +-
- arch/x86/include/asm/acpi.h           |  2 +-
- arch/x86/include/asm/processor.h      |  2 +-
- arch/x86/kernel/amd_nb.c              |  2 +-
- arch/x86/kernel/apic/apic.c           |  6 +++---
- arch/x86/kernel/asm-offsets_32.c      |  2 +-
- arch/x86/kernel/cpu/amd.c             | 28 ++++++++++++++--------------
- arch/x86/kernel/cpu/centaur.c         |  4 ++--
- arch/x86/kernel/cpu/common.c          |  8 ++++----
- arch/x86/kernel/cpu/cyrix.c           |  2 +-
- arch/x86/kernel/cpu/intel.c           | 18 +++++++++---------
- arch/x86/kernel/cpu/intel_rdt.c       |  2 +-
- arch/x86/kernel/cpu/microcode/intel.c |  4 ++--
- arch/x86/kernel/cpu/mtrr/generic.c    |  2 +-
- arch/x86/kernel/cpu/mtrr/main.c       |  4 ++--
- arch/x86/kernel/cpu/proc.c            |  4 ++--
- arch/x86/kernel/head_32.S             |  4 ++--
- arch/x86/kernel/mpparse.c             |  2 +-
- arch/x86/lib/cpu.c                    |  2 +-
- drivers/char/hw_random/via-rng.c      |  2 +-
- drivers/cpufreq/acpi-cpufreq.c        |  2 +-
- drivers/cpufreq/longhaul.c            |  6 +++---
- drivers/cpufreq/p4-clockmod.c         |  2 +-
- drivers/cpufreq/powernow-k7.c         |  2 +-
- drivers/cpufreq/speedstep-centrino.c  |  4 ++--
- drivers/cpufreq/speedstep-lib.c       |  6 +++---
- drivers/crypto/padlock-aes.c          |  2 +-
- drivers/edac/amd64_edac.c             |  2 +-
- drivers/hwmon/coretemp.c              |  6 +++---
- drivers/hwmon/hwmon-vid.c             |  2 +-
- drivers/hwmon/k10temp.c               |  2 +-
- drivers/hwmon/k8temp.c                |  2 +-
- drivers/video/fbdev/geode/video_gx.c  |  2 +-
- 35 files changed, 73 insertions(+), 73 deletions(-)
-
-diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
-index 56457cb73448..731153a4681e 100644
---- a/arch/x86/events/intel/core.c
-+++ b/arch/x86/events/intel/core.c
-@@ -3559,7 +3559,7 @@ static int intel_snb_pebs_broken(int cpu)
- 		break;
- 
- 	case INTEL_FAM6_SANDYBRIDGE_X:
--		switch (cpu_data(cpu).x86_stepping) {
-+		switch (cpu_data(cpu).x86_mask) {
- 		case 6: rev = 0x618; break;
- 		case 7: rev = 0x70c; break;
- 		}
-diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
-index cf372b90557e..ae64d0b69729 100644
---- a/arch/x86/events/intel/lbr.c
-+++ b/arch/x86/events/intel/lbr.c
-@@ -1186,7 +1186,7 @@ void __init intel_pmu_lbr_init_atom(void)
- 	 * on PMU interrupt
- 	 */
- 	if (boot_cpu_data.x86_model == 28
--	    && boot_cpu_data.x86_stepping < 10) {
-+	    && boot_cpu_data.x86_mask < 10) {
- 		pr_cont("LBR disabled due to erratum");
- 		return;
- 	}
-diff --git a/arch/x86/events/intel/p6.c b/arch/x86/events/intel/p6.c
-index 408879b0c0d4..a5604c352930 100644
---- a/arch/x86/events/intel/p6.c
-+++ b/arch/x86/events/intel/p6.c
-@@ -234,7 +234,7 @@ static __initconst const struct x86_pmu p6_pmu = {
- 
- static __init void p6_pmu_rdpmc_quirk(void)
- {
--	if (boot_cpu_data.x86_stepping < 9) {
-+	if (boot_cpu_data.x86_mask < 9) {
- 		/*
- 		 * PPro erratum 26; fixed in stepping 9 and above.
- 		 */
-diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h
-index f077401869ee..8d0ec9df1cbe 100644
---- a/arch/x86/include/asm/acpi.h
-+++ b/arch/x86/include/asm/acpi.h
-@@ -94,7 +94,7 @@ static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate)
- 	if (boot_cpu_data.x86 == 0x0F &&
- 	    boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
- 	    boot_cpu_data.x86_model <= 0x05 &&
--	    boot_cpu_data.x86_stepping < 0x0A)
-+	    boot_cpu_data.x86_mask < 0x0A)
- 		return 1;
- 	else if (boot_cpu_has(X86_BUG_AMD_APIC_C1E))
- 		return 1;
-diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
-index 44c2c4ec6d60..bf787ee25466 100644
---- a/arch/x86/include/asm/processor.h
-+++ b/arch/x86/include/asm/processor.h
-@@ -91,7 +91,7 @@ struct cpuinfo_x86 {
- 	__u8			x86;		/* CPU family */
- 	__u8			x86_vendor;	/* CPU vendor */
- 	__u8			x86_model;
--	__u8			x86_stepping;
-+	__u8			x86_mask;
- #ifdef CONFIG_X86_64
- 	/* Number of 4K pages in DTLB/ITLB combined(in pages): */
- 	int			x86_tlbsize;
-diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
-index c88e0b127810..6db28f17ff28 100644
---- a/arch/x86/kernel/amd_nb.c
-+++ b/arch/x86/kernel/amd_nb.c
-@@ -235,7 +235,7 @@ int amd_cache_northbridges(void)
- 	if (boot_cpu_data.x86 == 0x10 &&
- 	    boot_cpu_data.x86_model >= 0x8 &&
- 	    (boot_cpu_data.x86_model > 0x9 ||
--	     boot_cpu_data.x86_stepping >= 0x1))
-+	     boot_cpu_data.x86_mask >= 0x1))
- 		amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
- 
- 	if (boot_cpu_data.x86 == 0x15)
-diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
-index b203af0855b5..25ddf02598d2 100644
---- a/arch/x86/kernel/apic/apic.c
-+++ b/arch/x86/kernel/apic/apic.c
-@@ -546,7 +546,7 @@ static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
- 
- static u32 hsx_deadline_rev(void)
- {
--	switch (boot_cpu_data.x86_stepping) {
-+	switch (boot_cpu_data.x86_mask) {
- 	case 0x02: return 0x3a; /* EP */
- 	case 0x04: return 0x0f; /* EX */
- 	}
-@@ -556,7 +556,7 @@ static u32 hsx_deadline_rev(void)
- 
- static u32 bdx_deadline_rev(void)
- {
--	switch (boot_cpu_data.x86_stepping) {
-+	switch (boot_cpu_data.x86_mask) {
- 	case 0x02: return 0x00000011;
- 	case 0x03: return 0x0700000e;
- 	case 0x04: return 0x0f00000c;
-@@ -568,7 +568,7 @@ static u32 bdx_deadline_rev(void)
- 
- static u32 skx_deadline_rev(void)
- {
--	switch (boot_cpu_data.x86_stepping) {
-+	switch (boot_cpu_data.x86_mask) {
- 	case 0x03: return 0x01000136;
- 	case 0x04: return 0x02000014;
- 	}
-diff --git a/arch/x86/kernel/asm-offsets_32.c b/arch/x86/kernel/asm-offsets_32.c
-index f91ba53e06c8..fa1261eefa16 100644
---- a/arch/x86/kernel/asm-offsets_32.c
-+++ b/arch/x86/kernel/asm-offsets_32.c
-@@ -18,7 +18,7 @@ void foo(void)
- 	OFFSET(CPUINFO_x86, cpuinfo_x86, x86);
- 	OFFSET(CPUINFO_x86_vendor, cpuinfo_x86, x86_vendor);
- 	OFFSET(CPUINFO_x86_model, cpuinfo_x86, x86_model);
--	OFFSET(CPUINFO_x86_stepping, cpuinfo_x86, x86_stepping);
-+	OFFSET(CPUINFO_x86_mask, cpuinfo_x86, x86_mask);
- 	OFFSET(CPUINFO_cpuid_level, cpuinfo_x86, cpuid_level);
- 	OFFSET(CPUINFO_x86_capability, cpuinfo_x86, x86_capability);
- 	OFFSET(CPUINFO_x86_vendor_id, cpuinfo_x86, x86_vendor_id);
-diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
-index e7d5a7883632..ea831c858195 100644
---- a/arch/x86/kernel/cpu/amd.c
-+++ b/arch/x86/kernel/cpu/amd.c
-@@ -119,7 +119,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
- 		return;
- 	}
- 
--	if (c->x86_model == 6 && c->x86_stepping == 1) {
-+	if (c->x86_model == 6 && c->x86_mask == 1) {
- 		const int K6_BUG_LOOP = 1000000;
- 		int n;
- 		void (*f_vide)(void);
-@@ -149,7 +149,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
- 
- 	/* K6 with old style WHCR */
- 	if (c->x86_model < 8 ||
--	   (c->x86_model == 8 && c->x86_stepping < 8)) {
-+	   (c->x86_model == 8 && c->x86_mask < 8)) {
- 		/* We can only write allocate on the low 508Mb */
- 		if (mbytes > 508)
- 			mbytes = 508;
-@@ -168,7 +168,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
- 		return;
- 	}
- 
--	if ((c->x86_model == 8 && c->x86_stepping > 7) ||
-+	if ((c->x86_model == 8 && c->x86_mask > 7) ||
- 	     c->x86_model == 9 || c->x86_model == 13) {
- 		/* The more serious chips .. */
- 
-@@ -221,7 +221,7 @@ static void init_amd_k7(struct cpuinfo_x86 *c)
- 	 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
- 	 * As per AMD technical note 27212 0.2
- 	 */
--	if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
-+	if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
- 		rdmsr(MSR_K7_CLK_CTL, l, h);
- 		if ((l & 0xfff00000) != 0x20000000) {
- 			pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
-@@ -241,12 +241,12 @@ static void init_amd_k7(struct cpuinfo_x86 *c)
- 	 * but they are not certified as MP capable.
- 	 */
- 	/* Athlon 660/661 is valid. */
--	if ((c->x86_model == 6) && ((c->x86_stepping == 0) ||
--	    (c->x86_stepping == 1)))
-+	if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
-+	    (c->x86_mask == 1)))
- 		return;
- 
- 	/* Duron 670 is valid */
--	if ((c->x86_model == 7) && (c->x86_stepping == 0))
-+	if ((c->x86_model == 7) && (c->x86_mask == 0))
- 		return;
- 
- 	/*
-@@ -256,8 +256,8 @@ static void init_amd_k7(struct cpuinfo_x86 *c)
- 	 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
- 	 * more.
- 	 */
--	if (((c->x86_model == 6) && (c->x86_stepping >= 2)) ||
--	    ((c->x86_model == 7) && (c->x86_stepping >= 1)) ||
-+	if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
-+	    ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
- 	     (c->x86_model > 7))
- 		if (cpu_has(c, X86_FEATURE_MP))
- 			return;
-@@ -583,7 +583,7 @@ static void early_init_amd(struct cpuinfo_x86 *c)
- 	/*  Set MTRR capability flag if appropriate */
- 	if (c->x86 == 5)
- 		if (c->x86_model == 13 || c->x86_model == 9 ||
--		    (c->x86_model == 8 && c->x86_stepping >= 8))
-+		    (c->x86_model == 8 && c->x86_mask >= 8))
- 			set_cpu_cap(c, X86_FEATURE_K6_MTRR);
- #endif
- #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
-@@ -769,7 +769,7 @@ static void init_amd_zn(struct cpuinfo_x86 *c)
- 	 * Fix erratum 1076: CPB feature bit not being set in CPUID. It affects
- 	 * all up to and including B1.
- 	 */
--	if (c->x86_model <= 1 && c->x86_stepping <= 1)
-+	if (c->x86_model <= 1 && c->x86_mask <= 1)
- 		set_cpu_cap(c, X86_FEATURE_CPB);
- }
- 
-@@ -880,11 +880,11 @@ static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
- 	/* AMD errata T13 (order #21922) */
- 	if ((c->x86 == 6)) {
- 		/* Duron Rev A0 */
--		if (c->x86_model == 3 && c->x86_stepping == 0)
-+		if (c->x86_model == 3 && c->x86_mask == 0)
- 			size = 64;
- 		/* Tbird rev A1/A2 */
- 		if (c->x86_model == 4 &&
--			(c->x86_stepping == 0 || c->x86_stepping == 1))
-+			(c->x86_mask == 0 || c->x86_mask == 1))
- 			size = 256;
- 	}
- 	return size;
-@@ -1021,7 +1021,7 @@ static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
- 	}
- 
- 	/* OSVW unavailable or ID unknown, match family-model-stepping range */
--	ms = (cpu->x86_model << 4) | cpu->x86_stepping;
-+	ms = (cpu->x86_model << 4) | cpu->x86_mask;
- 	while ((range = *erratum++))
- 		if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
- 		    (ms >= AMD_MODEL_RANGE_START(range)) &&
-diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
-index 595be776727d..68bc6d9b3132 100644
---- a/arch/x86/kernel/cpu/centaur.c
-+++ b/arch/x86/kernel/cpu/centaur.c
-@@ -136,7 +136,7 @@ static void init_centaur(struct cpuinfo_x86 *c)
- 			clear_cpu_cap(c, X86_FEATURE_TSC);
- 			break;
- 		case 8:
--			switch (c->x86_stepping) {
-+			switch (c->x86_mask) {
- 			default:
- 			name = "2";
- 				break;
-@@ -211,7 +211,7 @@ centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
- 	 *  - Note, it seems this may only be in engineering samples.
- 	 */
- 	if ((c->x86 == 6) && (c->x86_model == 9) &&
--				(c->x86_stepping == 1) && (size == 65))
-+				(c->x86_mask == 1) && (size == 65))
- 		size -= 1;
- 	return size;
- }
-diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
-index 824aee0117bb..a37fd008d24b 100644
---- a/arch/x86/kernel/cpu/common.c
-+++ b/arch/x86/kernel/cpu/common.c
-@@ -731,7 +731,7 @@ void cpu_detect(struct cpuinfo_x86 *c)
- 		cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
- 		c->x86		= x86_family(tfms);
- 		c->x86_model	= x86_model(tfms);
--		c->x86_stepping	= x86_stepping(tfms);
-+		c->x86_mask	= x86_stepping(tfms);
- 
- 		if (cap0 & (1<<19)) {
- 			c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
-@@ -1186,7 +1186,7 @@ static void identify_cpu(struct cpuinfo_x86 *c)
- 	c->loops_per_jiffy = loops_per_jiffy;
- 	c->x86_cache_size = 0;
- 	c->x86_vendor = X86_VENDOR_UNKNOWN;
--	c->x86_model = c->x86_stepping = 0;	/* So far unknown... */
-+	c->x86_model = c->x86_mask = 0;	/* So far unknown... */
- 	c->x86_vendor_id[0] = '\0'; /* Unset */
- 	c->x86_model_id[0] = '\0';  /* Unset */
- 	c->x86_max_cores = 1;
-@@ -1378,8 +1378,8 @@ void print_cpu_info(struct cpuinfo_x86 *c)
- 
- 	pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
- 
--	if (c->x86_stepping || c->cpuid_level >= 0)
--		pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
-+	if (c->x86_mask || c->cpuid_level >= 0)
-+		pr_cont(", stepping: 0x%x)\n", c->x86_mask);
- 	else
- 		pr_cont(")\n");
- }
-diff --git a/arch/x86/kernel/cpu/cyrix.c b/arch/x86/kernel/cpu/cyrix.c
-index 8949b7ae6d92..6b4bb335641f 100644
---- a/arch/x86/kernel/cpu/cyrix.c
-+++ b/arch/x86/kernel/cpu/cyrix.c
-@@ -215,7 +215,7 @@ static void init_cyrix(struct cpuinfo_x86 *c)
- 
- 	/* common case step number/rev -- exceptions handled below */
- 	c->x86_model = (dir1 >> 4) + 1;
--	c->x86_stepping = dir1 & 0xf;
-+	c->x86_mask = dir1 & 0xf;
- 
- 	/* Now cook; the original recipe is by Channing Corn, from Cyrix.
- 	 * We do the same thing for each generation: we work out
-diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
-index d19e903214b4..ef796f14f7ae 100644
---- a/arch/x86/kernel/cpu/intel.c
-+++ b/arch/x86/kernel/cpu/intel.c
-@@ -146,7 +146,7 @@ static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
- 
- 	for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
- 		if (c->x86_model == spectre_bad_microcodes[i].model &&
--		    c->x86_stepping == spectre_bad_microcodes[i].stepping)
-+		    c->x86_mask == spectre_bad_microcodes[i].stepping)
- 			return (c->microcode <= spectre_bad_microcodes[i].microcode);
- 	}
- 	return false;
-@@ -193,7 +193,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
- 	 * need the microcode to have already been loaded... so if it is
- 	 * not, recommend a BIOS update and disable large pages.
- 	 */
--	if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&
-+	if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
- 	    c->microcode < 0x20e) {
- 		pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
- 		clear_cpu_cap(c, X86_FEATURE_PSE);
-@@ -209,7 +209,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
- 
- 	/* CPUID workaround for 0F33/0F34 CPU */
- 	if (c->x86 == 0xF && c->x86_model == 0x3
--	    && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))
-+	    && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
- 		c->x86_phys_bits = 36;
- 
- 	/*
-@@ -307,7 +307,7 @@ int ppro_with_ram_bug(void)
- 	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
- 	    boot_cpu_data.x86 == 6 &&
- 	    boot_cpu_data.x86_model == 1 &&
--	    boot_cpu_data.x86_stepping < 8) {
-+	    boot_cpu_data.x86_mask < 8) {
- 		pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
- 		return 1;
- 	}
-@@ -324,7 +324,7 @@ static void intel_smp_check(struct cpuinfo_x86 *c)
- 	 * Mask B, Pentium, but not Pentium MMX
- 	 */
- 	if (c->x86 == 5 &&
--	    c->x86_stepping >= 1 && c->x86_stepping <= 4 &&
-+	    c->x86_mask >= 1 && c->x86_mask <= 4 &&
- 	    c->x86_model <= 3) {
- 		/*
- 		 * Remember we have B step Pentia with bugs
-@@ -367,7 +367,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
- 	 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
- 	 * model 3 mask 3
- 	 */
--	if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)
-+	if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
- 		clear_cpu_cap(c, X86_FEATURE_SEP);
- 
- 	/*
-@@ -385,7 +385,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
- 	 * P4 Xeon erratum 037 workaround.
- 	 * Hardware prefetcher may cause stale data to be loaded into the cache.
- 	 */
--	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {
-+	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
- 		if (msr_set_bit(MSR_IA32_MISC_ENABLE,
- 				MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
- 			pr_info("CPU: C0 stepping P4 Xeon detected.\n");
-@@ -400,7 +400,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
- 	 * Specification Update").
- 	 */
- 	if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
--	    (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
-+	    (c->x86_mask < 0x6 || c->x86_mask == 0xb))
- 		set_cpu_bug(c, X86_BUG_11AP);
- 
- 
-@@ -647,7 +647,7 @@ static void init_intel(struct cpuinfo_x86 *c)
- 		case 6:
- 			if (l2 == 128)
- 				p = "Celeron (Mendocino)";
--			else if (c->x86_stepping == 0 || c->x86_stepping == 5)
-+			else if (c->x86_mask == 0 || c->x86_mask == 5)
- 				p = "Celeron-A";
- 			break;
- 
-diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
-index 18dd8f22e353..99442370de40 100644
---- a/arch/x86/kernel/cpu/intel_rdt.c
-+++ b/arch/x86/kernel/cpu/intel_rdt.c
-@@ -771,7 +771,7 @@ static __init void rdt_quirks(void)
- 			cache_alloc_hsw_probe();
- 		break;
- 	case INTEL_FAM6_SKYLAKE_X:
--		if (boot_cpu_data.x86_stepping <= 4)
-+		if (boot_cpu_data.x86_mask <= 4)
- 			set_rdt_options("!cmt,!mbmtotal,!mbmlocal,!l3cat");
- 	}
- }
-diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
-index a15db2b4e0d6..e5edb92c9172 100644
---- a/arch/x86/kernel/cpu/microcode/intel.c
-+++ b/arch/x86/kernel/cpu/microcode/intel.c
-@@ -921,7 +921,7 @@ static bool is_blacklisted(unsigned int cpu)
- 	 */
- 	if (c->x86 == 6 &&
- 	    c->x86_model == INTEL_FAM6_BROADWELL_X &&
--	    c->x86_stepping == 0x01 &&
-+	    c->x86_mask == 0x01 &&
- 	    llc_size_per_core > 2621440 &&
- 	    c->microcode < 0x0b000021) {
- 		pr_err_once("Erratum BDF90: late loading with revision < 0x0b000021 (0x%x) disabled.\n", c->microcode);
-@@ -944,7 +944,7 @@ static enum ucode_state request_microcode_fw(int cpu, struct device *device,
- 		return UCODE_NFOUND;
- 
- 	sprintf(name, "intel-ucode/%02x-%02x-%02x",
--		c->x86, c->x86_model, c->x86_stepping);
-+		c->x86, c->x86_model, c->x86_mask);
- 
- 	if (request_firmware_direct(&firmware, name, device)) {
- 		pr_debug("data file %s load failed\n", name);
-diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c
-index e12ee86906c6..fdc55215d44d 100644
---- a/arch/x86/kernel/cpu/mtrr/generic.c
-+++ b/arch/x86/kernel/cpu/mtrr/generic.c
-@@ -859,7 +859,7 @@ int generic_validate_add_page(unsigned long base, unsigned long size,
- 	 */
- 	if (is_cpu(INTEL) && boot_cpu_data.x86 == 6 &&
- 	    boot_cpu_data.x86_model == 1 &&
--	    boot_cpu_data.x86_stepping <= 7) {
-+	    boot_cpu_data.x86_mask <= 7) {
- 		if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) {
- 			pr_warn("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base);
- 			return -EINVAL;
-diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c
-index 7468de429087..40d5a8a75212 100644
---- a/arch/x86/kernel/cpu/mtrr/main.c
-+++ b/arch/x86/kernel/cpu/mtrr/main.c
-@@ -711,8 +711,8 @@ void __init mtrr_bp_init(void)
- 			if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
- 			    boot_cpu_data.x86 == 0xF &&
- 			    boot_cpu_data.x86_model == 0x3 &&
--			    (boot_cpu_data.x86_stepping == 0x3 ||
--			     boot_cpu_data.x86_stepping == 0x4))
-+			    (boot_cpu_data.x86_mask == 0x3 ||
-+			     boot_cpu_data.x86_mask == 0x4))
- 				phys_addr = 36;
- 
- 			size_or_mask = SIZE_OR_MASK_BITS(phys_addr);
-diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
-index 2c8522a39ed5..f3da3bb1e29e 100644
---- a/arch/x86/kernel/cpu/proc.c
-+++ b/arch/x86/kernel/cpu/proc.c
-@@ -72,8 +72,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
- 		   c->x86_model,
- 		   c->x86_model_id[0] ? c->x86_model_id : "unknown");
- 
--	if (c->x86_stepping || c->cpuid_level >= 0)
--		seq_printf(m, "stepping\t: %d\n", c->x86_stepping);
-+	if (c->x86_mask || c->cpuid_level >= 0)
-+		seq_printf(m, "stepping\t: %d\n", c->x86_mask);
- 	else
- 		seq_puts(m, "stepping\t: unknown\n");
- 	if (c->microcode)
-diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S
-index b59e4fb40fd9..c29020907886 100644
---- a/arch/x86/kernel/head_32.S
-+++ b/arch/x86/kernel/head_32.S
-@@ -37,7 +37,7 @@
- #define X86		new_cpu_data+CPUINFO_x86
- #define X86_VENDOR	new_cpu_data+CPUINFO_x86_vendor
- #define X86_MODEL	new_cpu_data+CPUINFO_x86_model
--#define X86_STEPPING	new_cpu_data+CPUINFO_x86_stepping
-+#define X86_MASK	new_cpu_data+CPUINFO_x86_mask
- #define X86_HARD_MATH	new_cpu_data+CPUINFO_hard_math
- #define X86_CPUID	new_cpu_data+CPUINFO_cpuid_level
- #define X86_CAPABILITY	new_cpu_data+CPUINFO_x86_capability
-@@ -332,7 +332,7 @@ ENTRY(startup_32_smp)
- 	shrb $4,%al
- 	movb %al,X86_MODEL
- 	andb $0x0f,%cl		# mask mask revision
--	movb %cl,X86_STEPPING
-+	movb %cl,X86_MASK
- 	movl %edx,X86_CAPABILITY
- 
- .Lis486:
-diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c
-index bc6bc6689e68..3a4b12809ab5 100644
---- a/arch/x86/kernel/mpparse.c
-+++ b/arch/x86/kernel/mpparse.c
-@@ -407,7 +407,7 @@ static inline void __init construct_default_ISA_mptable(int mpc_default_type)
- 	processor.apicver = mpc_default_type > 4 ? 0x10 : 0x01;
- 	processor.cpuflag = CPU_ENABLED;
- 	processor.cpufeature = (boot_cpu_data.x86 << 8) |
--	    (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_stepping;
-+	    (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
- 	processor.featureflag = boot_cpu_data.x86_capability[CPUID_1_EDX];
- 	processor.reserved[0] = 0;
- 	processor.reserved[1] = 0;
-diff --git a/arch/x86/lib/cpu.c b/arch/x86/lib/cpu.c
-index 2dd1fe13a37b..d6f848d1211d 100644
---- a/arch/x86/lib/cpu.c
-+++ b/arch/x86/lib/cpu.c
-@@ -18,7 +18,7 @@ unsigned int x86_model(unsigned int sig)
- {
- 	unsigned int fam, model;
- 
--	fam = x86_family(sig);
-+	 fam = x86_family(sig);
- 
- 	model = (sig >> 4) & 0xf;
- 
-diff --git a/drivers/char/hw_random/via-rng.c b/drivers/char/hw_random/via-rng.c
-index 6e9df558325b..d1f5bb534e0e 100644
---- a/drivers/char/hw_random/via-rng.c
-+++ b/drivers/char/hw_random/via-rng.c
-@@ -162,7 +162,7 @@ static int via_rng_init(struct hwrng *rng)
- 	/* Enable secondary noise source on CPUs where it is present. */
- 
- 	/* Nehemiah stepping 8 and higher */
--	if ((c->x86_model == 9) && (c->x86_stepping > 7))
-+	if ((c->x86_model == 9) && (c->x86_mask > 7))
- 		lo |= VIA_NOISESRC2;
- 
- 	/* Esther */
-diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c
-index d0c34df0529c..3a2ca0f79daf 100644
---- a/drivers/cpufreq/acpi-cpufreq.c
-+++ b/drivers/cpufreq/acpi-cpufreq.c
-@@ -629,7 +629,7 @@ static int acpi_cpufreq_blacklist(struct cpuinfo_x86 *c)
- 	if (c->x86_vendor == X86_VENDOR_INTEL) {
- 		if ((c->x86 == 15) &&
- 		    (c->x86_model == 6) &&
--		    (c->x86_stepping == 8)) {
-+		    (c->x86_mask == 8)) {
- 			pr_info("Intel(R) Xeon(R) 7100 Errata AL30, processors may lock up on frequency changes: disabling acpi-cpufreq\n");
- 			return -ENODEV;
- 		    }
-diff --git a/drivers/cpufreq/longhaul.c b/drivers/cpufreq/longhaul.c
-index d5e27bc7585a..c46a12df40dd 100644
---- a/drivers/cpufreq/longhaul.c
-+++ b/drivers/cpufreq/longhaul.c
-@@ -775,7 +775,7 @@ static int longhaul_cpu_init(struct cpufreq_policy *policy)
- 		break;
- 
- 	case 7:
--		switch (c->x86_stepping) {
-+		switch (c->x86_mask) {
- 		case 0:
- 			longhaul_version = TYPE_LONGHAUL_V1;
- 			cpu_model = CPU_SAMUEL2;
-@@ -787,7 +787,7 @@ static int longhaul_cpu_init(struct cpufreq_policy *policy)
- 			break;
- 		case 1 ... 15:
- 			longhaul_version = TYPE_LONGHAUL_V2;
--			if (c->x86_stepping < 8) {
-+			if (c->x86_mask < 8) {
- 				cpu_model = CPU_SAMUEL2;
- 				cpuname = "C3 'Samuel 2' [C5B]";
- 			} else {
-@@ -814,7 +814,7 @@ static int longhaul_cpu_init(struct cpufreq_policy *policy)
- 		numscales = 32;
- 		memcpy(mults, nehemiah_mults, sizeof(nehemiah_mults));
- 		memcpy(eblcr, nehemiah_eblcr, sizeof(nehemiah_eblcr));
--		switch (c->x86_stepping) {
-+		switch (c->x86_mask) {
- 		case 0 ... 1:
- 			cpu_model = CPU_NEHEMIAH;
- 			cpuname = "C3 'Nehemiah A' [C5XLOE]";
-diff --git a/drivers/cpufreq/p4-clockmod.c b/drivers/cpufreq/p4-clockmod.c
-index a25741b1281b..fd77812313f3 100644
---- a/drivers/cpufreq/p4-clockmod.c
-+++ b/drivers/cpufreq/p4-clockmod.c
-@@ -168,7 +168,7 @@ static int cpufreq_p4_cpu_init(struct cpufreq_policy *policy)
- #endif
- 
- 	/* Errata workaround */
--	cpuid = (c->x86 << 8) | (c->x86_model << 4) | c->x86_stepping;
-+	cpuid = (c->x86 << 8) | (c->x86_model << 4) | c->x86_mask;
- 	switch (cpuid) {
- 	case 0x0f07:
- 	case 0x0f0a:
-diff --git a/drivers/cpufreq/powernow-k7.c b/drivers/cpufreq/powernow-k7.c
-index 302e9ce793a0..80ac313e6c59 100644
---- a/drivers/cpufreq/powernow-k7.c
-+++ b/drivers/cpufreq/powernow-k7.c
-@@ -131,7 +131,7 @@ static int check_powernow(void)
- 		return 0;
- 	}
- 
--	if ((c->x86_model == 6) && (c->x86_stepping == 0)) {
-+	if ((c->x86_model == 6) && (c->x86_mask == 0)) {
- 		pr_info("K7 660[A0] core detected, enabling errata workarounds\n");
- 		have_a0 = 1;
- 	}
-diff --git a/drivers/cpufreq/speedstep-centrino.c b/drivers/cpufreq/speedstep-centrino.c
-index 4fa5adf16c70..41bc5397f4bb 100644
---- a/drivers/cpufreq/speedstep-centrino.c
-+++ b/drivers/cpufreq/speedstep-centrino.c
-@@ -37,7 +37,7 @@ struct cpu_id
- {
- 	__u8	x86;            /* CPU family */
- 	__u8	x86_model;	/* model */
--	__u8	x86_stepping;	/* stepping */
-+	__u8	x86_mask;	/* stepping */
- };
- 
- enum {
-@@ -277,7 +277,7 @@ static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
- {
- 	if ((c->x86 == x->x86) &&
- 	    (c->x86_model == x->x86_model) &&
--	    (c->x86_stepping == x->x86_stepping))
-+	    (c->x86_mask == x->x86_mask))
- 		return 1;
- 	return 0;
- }
-diff --git a/drivers/cpufreq/speedstep-lib.c b/drivers/cpufreq/speedstep-lib.c
-index e3a9962ee410..8085ec9000d1 100644
---- a/drivers/cpufreq/speedstep-lib.c
-+++ b/drivers/cpufreq/speedstep-lib.c
-@@ -272,9 +272,9 @@ unsigned int speedstep_detect_processor(void)
- 		ebx = cpuid_ebx(0x00000001);
- 		ebx &= 0x000000FF;
- 
--		pr_debug("ebx value is %x, x86_stepping is %x\n", ebx, c->x86_stepping);
-+		pr_debug("ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask);
- 
--		switch (c->x86_stepping) {
-+		switch (c->x86_mask) {
- 		case 4:
- 			/*
- 			 * B-stepping [M-P4-M]
-@@ -361,7 +361,7 @@ unsigned int speedstep_detect_processor(void)
- 				msr_lo, msr_hi);
- 		if ((msr_hi & (1<<18)) &&
- 		    (relaxed_check ? 1 : (msr_hi & (3<<24)))) {
--			if (c->x86_stepping == 0x01) {
-+			if (c->x86_mask == 0x01) {
- 				pr_debug("early PIII version\n");
- 				return SPEEDSTEP_CPU_PIII_C_EARLY;
- 			} else
-diff --git a/drivers/crypto/padlock-aes.c b/drivers/crypto/padlock-aes.c
-index 1c6cbda56afe..4b6642a25df5 100644
---- a/drivers/crypto/padlock-aes.c
-+++ b/drivers/crypto/padlock-aes.c
-@@ -512,7 +512,7 @@ static int __init padlock_init(void)
- 
- 	printk(KERN_NOTICE PFX "Using VIA PadLock ACE for AES algorithm.\n");
- 
--	if (c->x86 == 6 && c->x86_model == 15 && c->x86_stepping == 2) {
-+	if (c->x86 == 6 && c->x86_model == 15 && c->x86_mask == 2) {
- 		ecb_fetch_blocks = MAX_ECB_FETCH_BLOCKS;
- 		cbc_fetch_blocks = MAX_CBC_FETCH_BLOCKS;
- 		printk(KERN_NOTICE PFX "VIA Nano stepping 2 detected: enabling workaround.\n");
-diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
-index 329cb96f886f..8b16ec595fa7 100644
---- a/drivers/edac/amd64_edac.c
-+++ b/drivers/edac/amd64_edac.c
-@@ -3147,7 +3147,7 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt)
- 	struct amd64_family_type *fam_type = NULL;
- 
- 	pvt->ext_model  = boot_cpu_data.x86_model >> 4;
--	pvt->stepping	= boot_cpu_data.x86_stepping;
-+	pvt->stepping	= boot_cpu_data.x86_mask;
- 	pvt->model	= boot_cpu_data.x86_model;
- 	pvt->fam	= boot_cpu_data.x86;
- 
-diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
-index a42744c7665b..c13a4fd86b3c 100644
---- a/drivers/hwmon/coretemp.c
-+++ b/drivers/hwmon/coretemp.c
-@@ -268,13 +268,13 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
- 	for (i = 0; i < ARRAY_SIZE(tjmax_model_table); i++) {
- 		const struct tjmax_model *tm = &tjmax_model_table[i];
- 		if (c->x86_model == tm->model &&
--		    (tm->mask == ANY || c->x86_stepping == tm->mask))
-+		    (tm->mask == ANY || c->x86_mask == tm->mask))
- 			return tm->tjmax;
- 	}
- 
- 	/* Early chips have no MSR for TjMax */
- 
--	if (c->x86_model == 0xf && c->x86_stepping < 4)
-+	if (c->x86_model == 0xf && c->x86_mask < 4)
- 		usemsr_ee = 0;
- 
- 	if (c->x86_model > 0xe && usemsr_ee) {
-@@ -425,7 +425,7 @@ static int chk_ucode_version(unsigned int cpu)
- 	 * Readings might stop update when processor visited too deep sleep,
- 	 * fixed for stepping D0 (6EC).
- 	 */
--	if (c->x86_model == 0xe && c->x86_stepping < 0xc && c->microcode < 0x39) {
-+	if (c->x86_model == 0xe && c->x86_mask < 0xc && c->microcode < 0x39) {
- 		pr_err("Errata AE18 not fixed, update BIOS or microcode of the CPU!\n");
- 		return -ENODEV;
- 	}
-diff --git a/drivers/hwmon/hwmon-vid.c b/drivers/hwmon/hwmon-vid.c
-index 84e91286fc4f..ef91b8a67549 100644
---- a/drivers/hwmon/hwmon-vid.c
-+++ b/drivers/hwmon/hwmon-vid.c
-@@ -293,7 +293,7 @@ u8 vid_which_vrm(void)
- 	if (c->x86 < 6)		/* Any CPU with family lower than 6 */
- 		return 0;	/* doesn't have VID */
- 
--	vrm_ret = find_vrm(c->x86, c->x86_model, c->x86_stepping, c->x86_vendor);
-+	vrm_ret = find_vrm(c->x86, c->x86_model, c->x86_mask, c->x86_vendor);
- 	if (vrm_ret == 134)
- 		vrm_ret = get_via_model_d_vrm();
- 	if (vrm_ret == 0)
-diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
-index b960015cb073..0721e175664a 100644
---- a/drivers/hwmon/k10temp.c
-+++ b/drivers/hwmon/k10temp.c
-@@ -226,7 +226,7 @@ static bool has_erratum_319(struct pci_dev *pdev)
- 	 * and AM3 formats, but that's the best we can do.
- 	 */
- 	return boot_cpu_data.x86_model < 4 ||
--	       (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
-+	       (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_mask <= 2);
- }
- 
- static int k10temp_probe(struct pci_dev *pdev,
-diff --git a/drivers/hwmon/k8temp.c b/drivers/hwmon/k8temp.c
-index e59f9113fb93..5a632bcf869b 100644
---- a/drivers/hwmon/k8temp.c
-+++ b/drivers/hwmon/k8temp.c
-@@ -187,7 +187,7 @@ static int k8temp_probe(struct pci_dev *pdev,
- 		return -ENOMEM;
- 
- 	model = boot_cpu_data.x86_model;
--	stepping = boot_cpu_data.x86_stepping;
-+	stepping = boot_cpu_data.x86_mask;
- 
- 	/* feature available since SH-C0, exclude older revisions */
- 	if ((model == 4 && stepping == 0) ||
-diff --git a/drivers/video/fbdev/geode/video_gx.c b/drivers/video/fbdev/geode/video_gx.c
-index 67773e8bbb95..6082f653c68a 100644
---- a/drivers/video/fbdev/geode/video_gx.c
-+++ b/drivers/video/fbdev/geode/video_gx.c
-@@ -127,7 +127,7 @@ void gx_set_dclk_frequency(struct fb_info *info)
- 	int timeout = 1000;
- 
- 	/* Rev. 1 Geode GXs use a 14 MHz reference clock instead of 48 MHz. */
--	if (cpu_data(0).x86_stepping == 1) {
-+	if (cpu_data(0).x86_mask == 1) {
- 		pll_table = gx_pll_table_14MHz;
- 		pll_table_len = ARRAY_SIZE(gx_pll_table_14MHz);
- 	} else {

debian/patches/debian/revert-x86-debug-use-ud2-for-warn.patch

@@ -1,68 +0,0 @@
-From: Ben Hutchings <ben@decadent.org.uk>
-Date: Wed, 14 Mar 2018 00:50:58 +0000
-Subject: Revert "x86/debug: Use UD2 for WARN()"
-Forwarded: not-needed
-
-This reverts commit 9a01e5477fa4535be47f6d7a8756cef7d3e90507, which
-was commit 3b3a371cc9bc980429baabe0a8e5f307f3d1f463 upstream.  This
-is an unnecessary ABI change.
----
- arch/x86/include/asm/bug.h | 15 +++++++++------
- arch/x86/kernel/traps.c    |  2 +-
- 2 files changed, 10 insertions(+), 7 deletions(-)
-
-diff --git a/arch/x86/include/asm/bug.h b/arch/x86/include/asm/bug.h
-index 6804d6642767..71e6f4bf9161 100644
---- a/arch/x86/include/asm/bug.h
-+++ b/arch/x86/include/asm/bug.h
-@@ -5,20 +5,23 @@
- #include <linux/stringify.h>
- 
- /*
-- * Despite that some emulators terminate on UD2, we use it for WARN().
-+ * Since some emulators terminate on UD2, we cannot use it for WARN.
-+ * Since various instruction decoders disagree on the length of UD1,
-+ * we cannot use it either. So use UD0 for WARN.
-  *
-- * Since various instruction decoders/specs disagree on the encoding of
-- * UD0/UD1.
-+ * (binutils knows about "ud1" but {en,de}codes it as 2 bytes, whereas
-+ *  our kernel decoder thinks it takes a ModRM byte, which seems consistent
-+ *  with various things like the Intel SDM instruction encoding rules)
-  */
- 
--#define ASM_UD0		".byte 0x0f, 0xff" /* + ModRM (for Intel) */
-+#define ASM_UD0		".byte 0x0f, 0xff"
- #define ASM_UD1		".byte 0x0f, 0xb9" /* + ModRM */
- #define ASM_UD2		".byte 0x0f, 0x0b"
- 
- #define INSN_UD0	0xff0f
- #define INSN_UD2	0x0b0f
- 
--#define LEN_UD2		2
-+#define LEN_UD0		2
- 
- #ifdef CONFIG_GENERIC_BUG
- 
-@@ -76,7 +79,7 @@ do {								\
- 
- #define __WARN_FLAGS(flags)					\
- do {								\
--	_BUG_FLAGS(ASM_UD2, BUGFLAG_WARNING|(flags));		\
-+	_BUG_FLAGS(ASM_UD0, BUGFLAG_WARNING|(flags));		\
- 	annotate_reachable();					\
- } while (0)
- 
-diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
-index 3d9b2308e7fa..446c9ef8cfc3 100644
---- a/arch/x86/kernel/traps.c
-+++ b/arch/x86/kernel/traps.c
-@@ -181,7 +181,7 @@ int fixup_bug(struct pt_regs *regs, int trapnr)
- 		break;
- 
- 	case BUG_TRAP_TYPE_WARN:
--		regs->ip += LEN_UD2;
-+		regs->ip += LEN_UD0;
- 		return 1;
- 	}
- 

debian/patches/debian/revert-x86-mm-rename-flush_tlb_single-and-flush_tlb_.patch

@@ -1,286 +0,0 @@
-From: Ben Hutchings <ben@decadent.org.uk>
-Date: Wed, 14 Mar 2018 00:50:19 +0000
-Subject: Revert "x86/mm: Rename flush_tlb_single() and flush_tlb_one() to
- __flush_tlb_one_[user|kernel]()"
-Forwarded: not-needed
-
-This reverts commit 3786b49d826096bd72568a4eac8aab337a29b7a7, which
-was commit 1299ef1d8870d2d9f09a5aadf2f8b2c887c2d033 upstream.  This
-is an unnecessary ABI change.
----
- arch/x86/include/asm/paravirt.h       |  4 ++--
- arch/x86/include/asm/paravirt_types.h |  2 +-
- arch/x86/include/asm/pgtable_32.h     |  2 +-
- arch/x86/include/asm/tlbflush.h       | 27 +++++++--------------------
- arch/x86/kernel/paravirt.c            |  6 +++---
- arch/x86/mm/init_64.c                 |  2 +-
- arch/x86/mm/ioremap.c                 |  2 +-
- arch/x86/mm/kmmio.c                   |  2 +-
- arch/x86/mm/pgtable_32.c              |  2 +-
- arch/x86/mm/tlb.c                     |  6 +++---
- arch/x86/platform/uv/tlb_uv.c         |  2 +-
- arch/x86/xen/mmu_pv.c                 |  6 +++---
- include/trace/events/xen.h            |  2 +-
- 13 files changed, 26 insertions(+), 39 deletions(-)
-
-diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
-index 554841fab717..892df375b615 100644
---- a/arch/x86/include/asm/paravirt.h
-+++ b/arch/x86/include/asm/paravirt.h
-@@ -297,9 +297,9 @@ static inline void __flush_tlb_global(void)
- {
- 	PVOP_VCALL0(pv_mmu_ops.flush_tlb_kernel);
- }
--static inline void __flush_tlb_one_user(unsigned long addr)
-+static inline void __flush_tlb_single(unsigned long addr)
- {
--	PVOP_VCALL1(pv_mmu_ops.flush_tlb_one_user, addr);
-+	PVOP_VCALL1(pv_mmu_ops.flush_tlb_single, addr);
- }
- 
- static inline void flush_tlb_others(const struct cpumask *cpumask,
-diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/paravirt_types.h
-index f624f1f10316..6ec54d01972d 100644
---- a/arch/x86/include/asm/paravirt_types.h
-+++ b/arch/x86/include/asm/paravirt_types.h
-@@ -217,7 +217,7 @@ struct pv_mmu_ops {
- 	/* TLB operations */
- 	void (*flush_tlb_user)(void);
- 	void (*flush_tlb_kernel)(void);
--	void (*flush_tlb_one_user)(unsigned long addr);
-+	void (*flush_tlb_single)(unsigned long addr);
- 	void (*flush_tlb_others)(const struct cpumask *cpus,
- 				 const struct flush_tlb_info *info);
- 
-diff --git a/arch/x86/include/asm/pgtable_32.h b/arch/x86/include/asm/pgtable_32.h
-index b3ec519e3982..282ad8715f75 100644
---- a/arch/x86/include/asm/pgtable_32.h
-+++ b/arch/x86/include/asm/pgtable_32.h
-@@ -62,7 +62,7 @@ void sync_initial_page_table(void);
- #define kpte_clear_flush(ptep, vaddr)		\
- do {						\
- 	pte_clear(&init_mm, (vaddr), (ptep));	\
--	__flush_tlb_one_kernel((vaddr));		\
-+	__flush_tlb_one((vaddr));		\
- } while (0)
- 
- #endif /* !__ASSEMBLY__ */
-diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
-index 84137c22fdfa..2b8f18ca5874 100644
---- a/arch/x86/include/asm/tlbflush.h
-+++ b/arch/x86/include/asm/tlbflush.h
-@@ -140,7 +140,7 @@ static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
- #else
- #define __flush_tlb() __native_flush_tlb()
- #define __flush_tlb_global() __native_flush_tlb_global()
--#define __flush_tlb_one_user(addr) __native_flush_tlb_one_user(addr)
-+#define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
- #endif
- 
- static inline bool tlb_defer_switch_to_init_mm(void)
-@@ -400,7 +400,7 @@ static inline void __native_flush_tlb_global(void)
- /*
-  * flush one page in the user mapping
-  */
--static inline void __native_flush_tlb_one_user(unsigned long addr)
-+static inline void __native_flush_tlb_single(unsigned long addr)
- {
- 	u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
- 
-@@ -437,31 +437,18 @@ static inline void __flush_tlb_all(void)
- /*
-  * flush one page in the kernel mapping
-  */
--static inline void __flush_tlb_one_kernel(unsigned long addr)
-+static inline void __flush_tlb_one(unsigned long addr)
- {
- 	count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
--
--	/*
--	 * If PTI is off, then __flush_tlb_one_user() is just INVLPG or its
--	 * paravirt equivalent.  Even with PCID, this is sufficient: we only
--	 * use PCID if we also use global PTEs for the kernel mapping, and
--	 * INVLPG flushes global translations across all address spaces.
--	 *
--	 * If PTI is on, then the kernel is mapped with non-global PTEs, and
--	 * __flush_tlb_one_user() will flush the given address for the current
--	 * kernel address space and for its usermode counterpart, but it does
--	 * not flush it for other address spaces.
--	 */
--	__flush_tlb_one_user(addr);
-+	__flush_tlb_single(addr);
- 
- 	if (!static_cpu_has(X86_FEATURE_PTI))
- 		return;
- 
- 	/*
--	 * See above.  We need to propagate the flush to all other address
--	 * spaces.  In principle, we only need to propagate it to kernelmode
--	 * address spaces, but the extra bookkeeping we would need is not
--	 * worth it.
-+	 * __flush_tlb_single() will have cleared the TLB entry for this ASID,
-+	 * but since kernel space is replicated across all, we must also
-+	 * invalidate all others.
- 	 */
- 	invalidate_other_asid();
- }
-diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c
-index 99dc79e76bdc..041096bdef86 100644
---- a/arch/x86/kernel/paravirt.c
-+++ b/arch/x86/kernel/paravirt.c
-@@ -200,9 +200,9 @@ static void native_flush_tlb_global(void)
- 	__native_flush_tlb_global();
- }
- 
--static void native_flush_tlb_one_user(unsigned long addr)
-+static void native_flush_tlb_single(unsigned long addr)
- {
--	__native_flush_tlb_one_user(addr);
-+	__native_flush_tlb_single(addr);
- }
- 
- struct static_key paravirt_steal_enabled;
-@@ -401,7 +401,7 @@ struct pv_mmu_ops pv_mmu_ops __ro_after_init = {
- 
- 	.flush_tlb_user = native_flush_tlb,
- 	.flush_tlb_kernel = native_flush_tlb_global,
--	.flush_tlb_one_user = native_flush_tlb_one_user,
-+	.flush_tlb_single = native_flush_tlb_single,
- 	.flush_tlb_others = native_flush_tlb_others,
- 
- 	.pgd_alloc = __paravirt_pgd_alloc,
-diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
-index 60ae1fe3609f..4a837289f2ad 100644
---- a/arch/x86/mm/init_64.c
-+++ b/arch/x86/mm/init_64.c
-@@ -256,7 +256,7 @@ static void __set_pte_vaddr(pud_t *pud, unsigned long vaddr, pte_t new_pte)
- 	 * It's enough to flush this one mapping.
- 	 * (PGE mappings get flushed as well)
- 	 */
--	__flush_tlb_one_kernel(vaddr);
-+	__flush_tlb_one(vaddr);
- }
- 
- void set_pte_vaddr_p4d(p4d_t *p4d_page, unsigned long vaddr, pte_t new_pte)
-diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c
-index e2db83bebc3b..c45b6ec5357b 100644
---- a/arch/x86/mm/ioremap.c
-+++ b/arch/x86/mm/ioremap.c
-@@ -820,5 +820,5 @@ void __init __early_set_fixmap(enum fixed_addresses idx,
- 		set_pte(pte, pfn_pte(phys >> PAGE_SHIFT, flags));
- 	else
- 		pte_clear(&init_mm, addr, pte);
--	__flush_tlb_one_kernel(addr);
-+	__flush_tlb_one(addr);
- }
-diff --git a/arch/x86/mm/kmmio.c b/arch/x86/mm/kmmio.c
-index 7c8686709636..58477ec3d66d 100644
---- a/arch/x86/mm/kmmio.c
-+++ b/arch/x86/mm/kmmio.c
-@@ -168,7 +168,7 @@ static int clear_page_presence(struct kmmio_fault_page *f, bool clear)
- 		return -1;
- 	}
- 
--	__flush_tlb_one_kernel(f->addr);
-+	__flush_tlb_one(f->addr);
- 	return 0;
- }
- 
-diff --git a/arch/x86/mm/pgtable_32.c b/arch/x86/mm/pgtable_32.c
-index 9bb7f0ab9fe6..c3c5274410a9 100644
---- a/arch/x86/mm/pgtable_32.c
-+++ b/arch/x86/mm/pgtable_32.c
-@@ -63,7 +63,7 @@ void set_pte_vaddr(unsigned long vaddr, pte_t pteval)
- 	 * It's enough to flush this one mapping.
- 	 * (PGE mappings get flushed as well)
- 	 */
--	__flush_tlb_one_kernel(vaddr);
-+	__flush_tlb_one(vaddr);
- }
- 
- unsigned long __FIXADDR_TOP = 0xfffff000;
-diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
-index 0c936435ea93..012d02624848 100644
---- a/arch/x86/mm/tlb.c
-+++ b/arch/x86/mm/tlb.c
-@@ -492,7 +492,7 @@ static void flush_tlb_func_common(const struct flush_tlb_info *f,
- 	 *    flush that changes context.tlb_gen from 2 to 3.  If they get
- 	 *    processed on this CPU in reverse order, we'll see
- 	 *     local_tlb_gen == 1, mm_tlb_gen == 3, and end != TLB_FLUSH_ALL.
--	 *    If we were to use __flush_tlb_one_user() and set local_tlb_gen to
-+	 *    If we were to use __flush_tlb_single() and set local_tlb_gen to
- 	 *    3, we'd be break the invariant: we'd update local_tlb_gen above
- 	 *    1 without the full flush that's needed for tlb_gen 2.
- 	 *
-@@ -513,7 +513,7 @@ static void flush_tlb_func_common(const struct flush_tlb_info *f,
- 
- 		addr = f->start;
- 		while (addr < f->end) {
--			__flush_tlb_one_user(addr);
-+			__flush_tlb_single(addr);
- 			addr += PAGE_SIZE;
- 		}
- 		if (local)
-@@ -660,7 +660,7 @@ static void do_kernel_range_flush(void *info)
- 
- 	/* flush range by one by one 'invlpg' */
- 	for (addr = f->start; addr < f->end; addr += PAGE_SIZE)
--		__flush_tlb_one_kernel(addr);
-+		__flush_tlb_one(addr);
- }
- 
- void flush_tlb_kernel_range(unsigned long start, unsigned long end)
-diff --git a/arch/x86/platform/uv/tlb_uv.c b/arch/x86/platform/uv/tlb_uv.c
-index 7d5d53f36a7a..8538a6723171 100644
---- a/arch/x86/platform/uv/tlb_uv.c
-+++ b/arch/x86/platform/uv/tlb_uv.c
-@@ -299,7 +299,7 @@ static void bau_process_message(struct msg_desc *mdp, struct bau_control *bcp,
- 		local_flush_tlb();
- 		stat->d_alltlb++;
- 	} else {
--		__flush_tlb_one_user(msg->address);
-+		__flush_tlb_single(msg->address);
- 		stat->d_onetlb++;
- 	}
- 	stat->d_requestee++;
-diff --git a/arch/x86/xen/mmu_pv.c b/arch/x86/xen/mmu_pv.c
-index aae88fec9941..d85076223a69 100644
---- a/arch/x86/xen/mmu_pv.c
-+++ b/arch/x86/xen/mmu_pv.c
-@@ -1300,12 +1300,12 @@ static void xen_flush_tlb(void)
- 	preempt_enable();
- }
- 
--static void xen_flush_tlb_one_user(unsigned long addr)
-+static void xen_flush_tlb_single(unsigned long addr)
- {
- 	struct mmuext_op *op;
- 	struct multicall_space mcs;
- 
--	trace_xen_mmu_flush_tlb_one_user(addr);
-+	trace_xen_mmu_flush_tlb_single(addr);
- 
- 	preempt_disable();
- 
-@@ -2370,7 +2370,7 @@ static const struct pv_mmu_ops xen_mmu_ops __initconst = {
- 
- 	.flush_tlb_user = xen_flush_tlb,
- 	.flush_tlb_kernel = xen_flush_tlb,
--	.flush_tlb_one_user = xen_flush_tlb_one_user,
-+	.flush_tlb_single = xen_flush_tlb_single,
- 	.flush_tlb_others = xen_flush_tlb_others,
- 
- 	.pgd_alloc = xen_pgd_alloc,
-diff --git a/include/trace/events/xen.h b/include/trace/events/xen.h
-index 7dd8f34c37df..b8adf05c534e 100644
---- a/include/trace/events/xen.h
-+++ b/include/trace/events/xen.h
-@@ -368,7 +368,7 @@ TRACE_EVENT(xen_mmu_flush_tlb,
- 	    TP_printk("%s", "")
- 	);
- 
--TRACE_EVENT(xen_mmu_flush_tlb_one_user,
-+TRACE_EVENT(xen_mmu_flush_tlb_single,
- 	    TP_PROTO(unsigned long addr),
- 	    TP_ARGS(addr),
- 	    TP_STRUCT__entry(

debian/patches/debian/x86-cpu-avoid-abi-change-in-4.15.5.patch

@@ -1,26 +0,0 @@
-From: Ben Hutchings <ben@decadent.org.uk>
-Date: Wed, 14 Mar 2018 00:40:53 +0000
-Subject: x86/cpu: Avoid ABI change in 4.15.5
-Forwarded: not-needed
-
-The type of cpuinfo_x86::x86_cache_size was changed from int to
-unsigned int, and the "unknown" value was changed from -1 to 0.  Only
-one in-tree user of the field seems to have checked for the "unknown"
-value, so this is probably not an ABI change in practice.  Just hide
-the type change from genksyms.
-
----
---- a/arch/x86/include/asm/processor.h
-+++ b/arch/x86/include/asm/processor.h
-@@ -109,7 +109,11 @@ struct cpuinfo_x86 {
- 	char			x86_vendor_id[16];
- 	char			x86_model_id[64];
- 	/* in KB - valid for CPUS which support this call: */
-+#ifndef __GENKSYMS__
- 	unsigned int		x86_cache_size;
-+#else
-+	int			x86_cache_size;
-+#endif
- 	int			x86_cache_alignment;	/* In bytes */
- 	/* Cache QoS architectural values: */
- 	int			x86_cache_max_rmid;	/* max index */

debian/patches/series

@@ -142,8 +142,3 @@ bugfix/arm64/ARM64-dts-meson-reduce-odroid-c2-eMMC-maximum-rate.patch
 features/arm64/tegra210-smp/0001-arm64-tegra-Add-CPU-and-PSCI-nodes-for-NVIDIA-Tegra2.patch
 
 # ABI maintenance
-debian/x86-cpu-avoid-abi-change-in-4.15.5.patch
-debian/revert-x86-cpu-rename-cpu_data.x86_mask-to-cpu_data..patch
-debian/revert-x86-mm-rename-flush_tlb_single-and-flush_tlb_.patch
-debian/revert-x86-debug-use-ud2-for-warn.patch
-debian/drm-atomic-avoid-abi-change-in-4.15.7.patch