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remove mips patches merged in rc6 

svn path=/dists/trunk/linux-2.6/; revision=6181
This commit is contained in:
Martin Michlmayr 2006-03-13 18:38:00 +00:00
parent 70667db083
commit 972d653e1f
6 changed files with 1 additions and 611 deletions
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53
debian/patches/mips-fix_iomap_nonpci.patch vendored
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@ -1,53 +0,0 @@
## DP: Fix build error on processors that don's support copy-on-write
## DP: Patch author: Ralf Baechle <ralf@linux-mips.org>
## DP: Upstream status: in Linus git (went in after rc5)
From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 28 Feb 2006 17:04:20 +0000 (+0000)
Subject: [MIPS] Fix build error on processors that don's support copy-on-write.
X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=778e2ac5970e445f8c6b7d8aa597ac162afe270a
[MIPS] Fix build error on processors that don's support copy-on-write.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
--- a/arch/mips/lib/iomap.c
+++ b/arch/mips/lib/iomap.c
@@ -63,7 +63,7 @@ void __iomem *pci_iomap(struct pci_dev *
return ioport_map(start, len);
if (flags & IORESOURCE_MEM) {
if (flags & IORESOURCE_CACHEABLE)
- return ioremap_cacheable_cow(start, len);
+ return ioremap_cachable(start, len);
return ioremap_nocache(start, len);
}
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -283,6 +283,24 @@ static inline void __iomem * __ioremap_m
__ioremap_mode((offset), (size), _CACHE_UNCACHED)
/*
+ * ioremap_cachable - map bus memory into CPU space
+ * @offset: bus address of the memory
+ * @size: size of the resource to map
+ *
+ * ioremap_nocache performs a platform specific sequence of operations to
+ * make bus memory CPU accessible via the readb/readw/readl/writeb/
+ * writew/writel functions and the other mmio helpers. The returned
+ * address is not guaranteed to be usable directly as a virtual
+ * address.
+ *
+ * This version of ioremap ensures that the memory is marked cachable by
+ * the CPU. Also enables full write-combining. Useful for some
+ * memory-like regions on I/O busses.
+ */
+#define ioremap_cachable(offset, size) \
+ __ioremap_mode((offset), (size), PAGE_CACHABLE_DEFAULT)
+
+/*
* These two are MIPS specific ioremap variant. ioremap_cacheable_cow
* requests a cachable mapping, ioremap_uncached_accelerated requests a
* mapping using the uncached accelerated mode which isn't supported on

28
debian/patches/mips-ip22zilog_oops.patch vendored
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@ -1,28 +0,0 @@
## DP: ip22zilog: Fix oops on runlevel change with serial console
## DP: Patch author: Martin Michlmayr <tbm@cyrius.com>
## DP: Upstream status: submitted to serial sub-system maintainer
[serial] ip22zilog: Fix oops on runlevel change with serial console
Incorrect uart_write_wakeup() calls cause reference to a NULL tty
pointer. This has been fixed in the sunsab and sunzilog serial drivers
in October 2005. Update the ip22zilog, which is based on sunzilog,
accordingly.
Signed-off-by: Martin Michlmayr <tbm@cyrius.com>
--- a/drivers/serial/ip22zilog.c 2006-02-23 22:05:49.000000000 +0000
+++ b/drivers/serial/ip22zilog.c 2006-02-27 09:51:38.000000000 +0000
@@ -420,10 +420,8 @@
if (up->port.info == NULL)
goto ack_tx_int;
xmit = &up->port.info->xmit;
- if (uart_circ_empty(xmit)) {
- uart_write_wakeup(&up->port);
+ if (uart_circ_empty(xmit))
goto ack_tx_int;
- }
if (uart_tx_stopped(&up->port))
goto ack_tx_int;

376
debian/patches/mips-linus-merge-post-rc5 vendored
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@ -1,376 +0,0 @@
MIPS stuff that got committed to Linus' git tree right after rc5
From: Linus Torvalds <torvalds@g5.osdl.org>
Date: Mon, 27 Feb 2006 17:46:24 +0000 (-0800)
Subject: Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=de5f503cfbe4f942492269c6bd97a16a4d61e488
Merge branch 'upstream' of git://ftp.linux-mips.org/upstream-linus
---
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -161,60 +161,6 @@ out:
return error;
}
-struct dirent32 {
- unsigned int d_ino;
- unsigned int d_off;
- unsigned short d_reclen;
- char d_name[NAME_MAX + 1];
-};
-
-static void
-xlate_dirent(void *dirent64, void *dirent32, long n)
-{
- long off;
- struct dirent *dirp;
- struct dirent32 *dirp32;
-
- off = 0;
- while (off < n) {
- dirp = (struct dirent *)(dirent64 + off);
- dirp32 = (struct dirent32 *)(dirent32 + off);
- off += dirp->d_reclen;
- dirp32->d_ino = dirp->d_ino;
- dirp32->d_off = (unsigned int)dirp->d_off;
- dirp32->d_reclen = dirp->d_reclen;
- strncpy(dirp32->d_name, dirp->d_name, dirp->d_reclen - ((3 * 4) + 2));
- }
- return;
-}
-
-asmlinkage long
-sys32_getdents(unsigned int fd, void * dirent32, unsigned int count)
-{
- long n;
- void *dirent64;
-
- dirent64 = (void *)((unsigned long)(dirent32 + (sizeof(long) - 1)) & ~(sizeof(long) - 1));
- if ((n = sys_getdents(fd, dirent64, count - (dirent64 - dirent32))) < 0)
- return(n);
- xlate_dirent(dirent64, dirent32, n);
- return(n);
-}
-
-asmlinkage int old_readdir(unsigned int fd, void * dirent, unsigned int count);
-
-asmlinkage int
-sys32_readdir(unsigned int fd, void * dirent32, unsigned int count)
-{
- int n;
- struct dirent dirent64;
-
- if ((n = old_readdir(fd, &dirent64, count)) < 0)
- return(n);
- xlate_dirent(&dirent64, dirent32, dirent64.d_reclen);
- return(n);
-}
-
asmlinkage int
sys32_waitpid(compat_pid_t pid, unsigned int *stat_addr, int options)
{
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -195,7 +195,7 @@ EXPORT(sysn32_call_table)
PTR sys_fdatasync
PTR sys_truncate
PTR sys_ftruncate /* 6075 */
- PTR sys32_getdents
+ PTR compat_sys_getdents
PTR sys_getcwd
PTR sys_chdir
PTR sys_fchdir
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -293,7 +293,7 @@ sys_call_table:
PTR sys_uselib
PTR sys_swapon
PTR sys_reboot
- PTR sys32_readdir
+ PTR compat_sys_old_readdir
PTR old_mmap /* 4090 */
PTR sys_munmap
PTR sys_truncate
@@ -345,7 +345,7 @@ sys_call_table:
PTR sys_setfsuid
PTR sys_setfsgid
PTR sys32_llseek /* 4140 */
- PTR sys32_getdents
+ PTR compat_sys_getdents
PTR compat_sys_select
PTR sys_flock
PTR sys_msync
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -540,6 +540,9 @@ void __init setup_arch(char **cmdline_p)
sparse_init();
paging_init();
resource_init();
+#ifdef CONFIG_SMP
+ plat_smp_setup();
+#endif
}
int __init fpu_disable(char *s)
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -236,7 +236,7 @@ void __init smp_prepare_cpus(unsigned in
init_new_context(current, &init_mm);
current_thread_info()->cpu = 0;
smp_tune_scheduling();
- prom_prepare_cpus(max_cpus);
+ plat_prepare_cpus(max_cpus);
}
/* preload SMP state for boot cpu */
--- a/arch/mips/kernel/smp_mt.c
+++ b/arch/mips/kernel/smp_mt.c
@@ -143,7 +143,7 @@ static struct irqaction irq_call = {
* Make sure all CPU's are in a sensible state before we boot any of the
* secondarys
*/
-void prom_prepare_cpus(unsigned int max_cpus)
+void plat_smp_setup(void)
{
unsigned long val;
int i, num;
@@ -179,11 +179,9 @@ void prom_prepare_cpus(unsigned int max_
write_vpe_c0_vpeconf0(tmp);
/* Record this as available CPU */
- if (i < max_cpus) {
- cpu_set(i, phys_cpu_present_map);
- __cpu_number_map[i] = ++num;
- __cpu_logical_map[num] = i;
- }
+ cpu_set(i, phys_cpu_present_map);
+ __cpu_number_map[i] = ++num;
+ __cpu_logical_map[num] = i;
}
/* disable multi-threading with TC's */
@@ -241,7 +239,10 @@ void prom_prepare_cpus(unsigned int max_
set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
}
+}
+void __init plat_prepare_cpus(unsigned int max_cpus)
+{
cpu_ipi_resched_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
cpu_ipi_call_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ;
--- a/arch/mips/pmc-sierra/yosemite/smp.c
+++ b/arch/mips/pmc-sierra/yosemite/smp.c
@@ -50,37 +50,25 @@ void __init prom_grab_secondary(void)
* We don't want to start the secondary CPU yet nor do we have a nice probing
* feature in PMON so we just assume presence of the secondary core.
*/
-static char maxcpus_string[] __initdata =
- KERN_WARNING "max_cpus set to 0; using 1 instead\n";
-
-void __init prom_prepare_cpus(unsigned int max_cpus)
+void __init plat_smp_setup(void)
{
- int enabled = 0, i;
-
- if (max_cpus == 0) {
- printk(maxcpus_string);
- max_cpus = 1;
- }
+ int i;
cpus_clear(phys_cpu_present_map);
for (i = 0; i < 2; i++) {
- if (i == max_cpus)
- break;
-
- /*
- * The boot CPU
- */
cpu_set(i, phys_cpu_present_map);
__cpu_number_map[i] = i;
__cpu_logical_map[i] = i;
- enabled++;
}
+}
+void __init plat_prepare_cpus(unsigned int max_cpus)
+{
/*
* Be paranoid. Enable the IPI only if we're really about to go SMP.
*/
- if (enabled > 1)
+ if (cpus_weight(cpu_possible_map))
set_c0_status(STATUSF_IP5);
}
--- a/arch/mips/sgi-ip27/ip27-smp.c
+++ b/arch/mips/sgi-ip27/ip27-smp.c
@@ -140,7 +140,7 @@ static __init void intr_clear_all(nasid_
REMOTE_HUB_CLR_INTR(nasid, i);
}
-void __init prom_prepare_cpus(unsigned int max_cpus)
+void __init plat_smp_setup(void)
{
cnodeid_t cnode;
@@ -161,6 +161,11 @@ void __init prom_prepare_cpus(unsigned i
alloc_cpupda(0, 0);
}
+void __init plat_prepare_cpus(unsigned int max_cpus)
+{
+ /* We already did everything necessary earlier */
+}
+
/*
* Launch a slave into smp_bootstrap(). It doesn't take an argument, and we
* set sp to the kernel stack of the newly created idle process, gp to the proc
--- a/arch/mips/sibyte/cfe/smp.c
+++ b/arch/mips/sibyte/cfe/smp.c
@@ -31,7 +31,7 @@
*
* Common setup before any secondaries are started
*/
-void __init prom_prepare_cpus(unsigned int max_cpus)
+void __init plat_smp_setup(void)
{
int i, num;
@@ -40,14 +40,18 @@ void __init prom_prepare_cpus(unsigned i
__cpu_number_map[0] = 0;
__cpu_logical_map[0] = 0;
- for (i=1, num=0; i<NR_CPUS; i++) {
+ for (i = 1, num = 0; i < NR_CPUS; i++) {
if (cfe_cpu_stop(i) == 0) {
cpu_set(i, phys_cpu_present_map);
__cpu_number_map[i] = ++num;
__cpu_logical_map[num] = i;
}
}
- printk("Detected %i available secondary CPU(s)\n", num);
+ printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
+}
+
+void __init plat_prepare_cpus(unsigned int max_cpus)
+{
}
/*
--- a/include/asm-mips/atomic.h
+++ b/include/asm-mips/atomic.h
@@ -250,7 +250,10 @@ static __inline__ int atomic_sub_if_posi
" subu %0, %1, %3 \n"
" bltz %0, 1f \n"
" sc %0, %2 \n"
+ " .set noreorder \n"
" beqzl %0, 1b \n"
+ " subu %0, %1, %3 \n"
+ " .set reorder \n"
" sync \n"
"1: \n"
" .set mips0 \n"
@@ -266,7 +269,10 @@ static __inline__ int atomic_sub_if_posi
" subu %0, %1, %3 \n"
" bltz %0, 1f \n"
" sc %0, %2 \n"
+ " .set noreorder \n"
" beqz %0, 1b \n"
+ " subu %0, %1, %3 \n"
+ " .set reorder \n"
" sync \n"
"1: \n"
" .set mips0 \n"
@@ -598,7 +604,10 @@ static __inline__ long atomic64_sub_if_p
" dsubu %0, %1, %3 \n"
" bltz %0, 1f \n"
" scd %0, %2 \n"
+ " .set noreorder \n"
" beqzl %0, 1b \n"
+ " dsubu %0, %1, %3 \n"
+ " .set reorder \n"
" sync \n"
"1: \n"
" .set mips0 \n"
@@ -614,7 +623,10 @@ static __inline__ long atomic64_sub_if_p
" dsubu %0, %1, %3 \n"
" bltz %0, 1f \n"
" scd %0, %2 \n"
+ " .set noreorder \n"
" beqz %0, 1b \n"
+ " dsubu %0, %1, %3 \n"
+ " .set reorder \n"
" sync \n"
"1: \n"
" .set mips0 \n"
--- a/include/asm-mips/smp.h
+++ b/include/asm-mips/smp.h
@@ -58,7 +58,9 @@ static inline int num_booting_cpus(void)
return cpus_weight(cpu_callout_map);
}
-/* These are defined by the board-specific code. */
+/*
+ * These are defined by the board-specific code.
+ */
/*
* Cause the function described by call_data to be executed on the passed
@@ -79,7 +81,12 @@ extern void prom_boot_secondary(int cpu,
extern void prom_init_secondary(void);
/*
- * Detect available CPUs, populate phys_cpu_present_map before smp_init
+ * Populate cpu_possible_map before smp_init, called from setup_arch.
+ */
+extern void plat_smp_setup(void);
+
+/*
+ * Called after init_IRQ but before __cpu_up.
*/
extern void prom_prepare_cpus(unsigned int max_cpus);
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -322,7 +322,7 @@ static inline unsigned long __cmpxchg_u3
#endif
"2: \n"
" .set pop \n"
- : "=&r" (retval), "=m" (*m)
+ : "=&r" (retval), "=R" (*m)
: "R" (*m), "Jr" (old), "Jr" (new)
: "memory");
} else if (cpu_has_llsc) {
@@ -342,7 +342,7 @@ static inline unsigned long __cmpxchg_u3
#endif
"2: \n"
" .set pop \n"
- : "=&r" (retval), "=m" (*m)
+ : "=&r" (retval), "=R" (*m)
: "R" (*m), "Jr" (old), "Jr" (new)
: "memory");
} else {
@@ -379,7 +379,7 @@ static inline unsigned long __cmpxchg_u6
#endif
"2: \n"
" .set pop \n"
- : "=&r" (retval), "=m" (*m)
+ : "=&r" (retval), "=R" (*m)
: "R" (*m), "Jr" (old), "Jr" (new)
: "memory");
} else if (cpu_has_llsc) {
@@ -397,7 +397,7 @@ static inline unsigned long __cmpxchg_u6
#endif
"2: \n"
" .set pop \n"
- : "=&r" (retval), "=m" (*m)
+ : "=&r" (retval), "=R" (*m)
: "R" (*m), "Jr" (old), "Jr" (new)
: "memory");
} else {

76
debian/patches/mips-scache-fix.patch vendored
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@ -1,76 +0,0 @@
## DP: Initialize scache flushing functions when CPU has no scache
## DP: Patch author: Ralf Baechle <ralf@linux-mips.org>
## DP: Upstream status: in Linus git (went in after rc5)
From: Ralf Baechle <ralf@linux-mips.org>
Date: Mon, 27 Feb 2006 19:05:55 +0000 (+0000)
Subject: [MIPS] Initialize S-cache function pointers even on S-cache-less CPUs.
X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=4debe4f963f9135771a8c5bc66e84396201dcfd8
[MIPS] Initialize S-cache function pointers even on S-cache-less CPUs.
When a CPU has no scache, the scache flushing functions currently
aren't getting initialized and the NULL pointer is eventually called
as a function. Initialize the scache flushing functions as a noop
when there's no scache.
Initial patch by me and most of the debugging done by Martin Michlmayr.
Signed-off-by: Martin Michlmayr <tbm@cyrius.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -235,7 +235,9 @@ static inline void r4k_blast_scache_page
{
unsigned long sc_lsize = cpu_scache_line_size();
- if (sc_lsize == 16)
+ if (scache_size == 0)
+ r4k_blast_scache_page = (void *)no_sc_noop;
+ else if (sc_lsize == 16)
r4k_blast_scache_page = blast_scache16_page;
else if (sc_lsize == 32)
r4k_blast_scache_page = blast_scache32_page;
@@ -251,7 +253,9 @@ static inline void r4k_blast_scache_page
{
unsigned long sc_lsize = cpu_scache_line_size();
- if (sc_lsize == 16)
+ if (scache_size == 0)
+ r4k_blast_scache_page_indexed = (void *)no_sc_noop;
+ else if (sc_lsize == 16)
r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
else if (sc_lsize == 32)
r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
@@ -267,7 +271,9 @@ static inline void r4k_blast_scache_setu
{
unsigned long sc_lsize = cpu_scache_line_size();
- if (sc_lsize == 16)
+ if (scache_size == 0)
+ r4k_blast_scache = (void *)no_sc_noop;
+ else if (sc_lsize == 16)
r4k_blast_scache = blast_scache16;
else if (sc_lsize == 32)
r4k_blast_scache = blast_scache32;
@@ -482,7 +488,7 @@ static inline void local_r4k_flush_icach
protected_blast_dcache_range(start, end);
}
- if (!cpu_icache_snoops_remote_store) {
+ if (!cpu_icache_snoops_remote_store && scache_size) {
if (end - start > scache_size)
r4k_blast_scache();
else
@@ -651,7 +657,7 @@ static void local_r4k_flush_cache_sigtra
R4600_HIT_CACHEOP_WAR_IMPL;
protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
- if (!cpu_icache_snoops_remote_store)
+ if (!cpu_icache_snoops_remote_store && scache_size)
protected_writeback_scache_line(addr & ~(sc_lsize - 1));
protected_flush_icache_line(addr & ~(ic_lsize - 1));
if (MIPS4K_ICACHE_REFILL_WAR) {

75
debian/patches/mtdpart-redboot-fis-byteswap.patch vendored
View File

@ -1,75 +0,0 @@
## DP: recognise a foreign byte sex partition table
## DP: Patch author: John Bowler <jbowler@acm.org>
## DP: Upstream status: in MTD tree
#
drivers/mtd/redboot.c: recognise a foreign byte sex partition table
The RedBoot boot loader writes flash partition tables containing native
byte sex 32 bit values. When booting an opposite byte sex kernel (e.g. an
LE kernel from BE RedBoot) the current MTD driver fails to handle the
partition table and therefore is unable to generate the correct partition
map for the flash.
The patch recognises that the FIS directory (the partition table) is
byte-reversed by examining the partition table size, which is known to be
one erase block (this is an assumption made elsewhere in redboot.c). If
the size matches the erase block after byte swapping the value then
byte-reversal is assumed, if not no further action is taken. The patched
code is fail safe; should redboot.c be changed to support a partition table
with a modified size field the test will fail and the partition table will
be assumed to have the host byte sex.
If byte-reversal is detected the patch byte swaps the remainder of the 32
bit fields in the copy of the table; this copy is then used to set up the
MTD partition map.
Signed-off-by: John Bowler <jbowler@acm.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Modified slightly and
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Index: drivers/mtd/redboot.c
===================================================================
RCS file: /home/cvs/mtd/drivers/mtd/redboot.c,v
retrieving revision 1.18
retrieving revision 1.19
diff -u -p -r1.18 -r1.19
--- linux-2.6.15/drivers/mtd/redboot.c 1970-01-01 00:00:00.000000000 +0000
+++ linux-2.6.15/drivers/mtd/redboot.c 1970-01-01 00:00:00.000000000 +0000
@@ -89,8 +89,32 @@ static int parse_redboot_partitions(stru
i = numslots;
break;
}
- if (!memcmp(buf[i].name, "FIS directory", 14))
+ if (!memcmp(buf[i].name, "FIS directory", 14)) {
+ /* This is apparently the FIS directory entry for the
+ * FIS directory itself. The FIS directory size is
+ * one erase block; if the buf[i].size field is
+ * swab32(erasesize) then we know we are looking at
+ * a byte swapped FIS directory - swap all the entries!
+ * (NOTE: this is 'size' not 'data_length'; size is
+ * the full size of the entry.)
+ */
+ if (swab32(buf[i].size) == master->erasesize) {
+ int j;
+ for (j = 0; j < numslots && buf[j].name[0] != 0xff; ++j) {
+ /* The unsigned long fields were written with the
+ * wrong byte sex, name and pad have no byte sex.
+ */
+ swab32s(&buf[j].flash_base);
+ swab32s(&buf[j].mem_base);
+ swab32s(&buf[j].size);
+ swab32s(&buf[j].entry_point);
+ swab32s(&buf[j].data_length);
+ swab32s(&buf[j].desc_cksum);
+ swab32s(&buf[j].file_cksum);
+ }
+ }
break;
+ }
}
if (i == numslots) {
/* Didn't find it */

4
debian/patches/series/0experimental.1 vendored
View File

@ -4,7 +4,6 @@
+ modular-ide-pnp.patch
+ version.patch
#
#merged + mtdpart-redboot-fis-byteswap.patch
+ ia64-irq-affinity-upfix.patch
+ powerpc-mkvmlinuz-support.patch
+ powerpc-build-links.patch
@ -16,10 +15,9 @@
+ sparc64-hme-lockup.patch
+ sparc64-atyfb-xl-gr.patch
+ mips-makefile.patch
#maybe merged + mips-arch-makefile.patch
+ mips-arch-makefile.patch
+ mips-gettimeofday.patch
+ mips-ide-scan.patch
+ mips-sb1-probe-ide.patch
#merged + mips-ip22zilog_oops.patch
+ s390-drivers-ccw-uevent-modalias.patch
+ s390-drivers-ccw-uevent-cleanup.patch