diff --git a/debian/changelog b/debian/changelog index 30340e46d..2f972fc26 100644 --- a/debian/changelog +++ b/debian/changelog @@ -32,6 +32,8 @@ linux (3.14.12-2) UNRELEASED; urgency=medium corresponding flavour. * [mips,mipsel] Remove the sb1a-bcm91480b flavour. * [mips,mipsel] Add mips64 and mips64el support (Closes: #749688). + * [mips/octeon] Backport from upstream PCIe2 support and interface + mode detection for Octeon. [ Ben Hutchings ] * net/l2tp: don't fall back on UDP [get|set]sockopt (CVE-2014-4943) diff --git a/debian/patches/features/mips/MIPS-Octeon-Add-PCIe2-support-in-arch_setup_msi_irq.patch b/debian/patches/features/mips/MIPS-Octeon-Add-PCIe2-support-in-arch_setup_msi_irq.patch new file mode 100644 index 000000000..9a2914dee --- /dev/null +++ b/debian/patches/features/mips/MIPS-Octeon-Add-PCIe2-support-in-arch_setup_msi_irq.patch @@ -0,0 +1,45 @@ +From: Eunbong Song +Date: Fri, 11 Apr 2014 08:32:54 +0000 +Subject: MIPS: Octeon: Add PCIe2 support in arch_setup_msi_irq() +Origin: https://git.kernel.org/linus/d19648d7f3b047bac9922fe097f62afbb48fee62 + +In arch_setup_msi_irq(), there is no case for PCIe2. So board which have PCIe2 functionality +fails to boot with "Kernel panic - not syncing: arch_setup_msi_irq: Invalid octeon_dma_bar_type" +message. This patch solve this problem. + +Signed-off-by: Eunbong Song +Cc: linux-mips@linux-mips.org +Cc: linux-kernel@vger.kernel.org +Patchwork: https://patchwork.linux-mips.org/patch/6747/ +Signed-off-by: Ralf Baechle +--- + arch/mips/pci/msi-octeon.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c +index 2b91b0e..ab0c5d1 100644 +--- a/arch/mips/pci/msi-octeon.c ++++ b/arch/mips/pci/msi-octeon.c +@@ -15,6 +15,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -162,6 +163,11 @@ msi_irq_allocated: + msg.address_lo = (0 + CVMX_NPEI_PCIE_MSI_RCV) & 0xffffffff; + msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32; + break; ++ case OCTEON_DMA_BAR_TYPE_PCIE2: ++ /* When using PCIe2, Bar 0 is based at 0 */ ++ msg.address_lo = (0 + CVMX_SLI_PCIE_MSI_RCV) & 0xffffffff; ++ msg.address_hi = (0 + CVMX_SLI_PCIE_MSI_RCV) >> 32; ++ break; + default: + panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type"); + } +-- +2.0.0 + diff --git a/debian/patches/features/mips/MIPS-octeon-Add-interface-mode-detection-for-Octeon-.patch b/debian/patches/features/mips/MIPS-octeon-Add-interface-mode-detection-for-Octeon-.patch new file mode 100644 index 000000000..a8d809287 --- /dev/null +++ b/debian/patches/features/mips/MIPS-octeon-Add-interface-mode-detection-for-Octeon-.patch @@ -0,0 +1,207 @@ +From: Alex Smith +Date: Thu, 29 May 2014 11:10:01 +0100 +Subject: MIPS: octeon: Add interface mode detection for Octeon II +Origin: https://git.kernel.org/linus/d8ce75934b888df0bd73dfd9c030a2b034a04977 + +Add interface mode detection for Octeon II. This is necessary to detect +the interface modes correctly on the UBNT E200 board. Code is taken +from the UBNT GPL source release, with some alterations: SRIO, ILK and +RXAUI interface modes are removed and instead return disabled as these +modes are not currently supported. + +Signed-off-by: Alex Smith +Tested-by: David Daney +Cc: linux-mips@linux-mips.org +Patchwork: https://patchwork.linux-mips.org/patch/7039/ +Signed-off-by: Ralf Baechle +--- + arch/mips/cavium-octeon/executive/cvmx-helper.c | 166 ++++++++++++++++++++++++ + 1 file changed, 166 insertions(+) + +diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c +index 8553ad5..7e5cf7a 100644 +--- a/arch/mips/cavium-octeon/executive/cvmx-helper.c ++++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c +@@ -106,6 +106,158 @@ int cvmx_helper_ports_on_interface(int interface) + EXPORT_SYMBOL_GPL(cvmx_helper_ports_on_interface); + + /** ++ * @INTERNAL ++ * Return interface mode for CN68xx. ++ */ ++static cvmx_helper_interface_mode_t __cvmx_get_mode_cn68xx(int interface) ++{ ++ union cvmx_mio_qlmx_cfg qlm_cfg; ++ switch (interface) { ++ case 0: ++ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0)); ++ /* QLM is disabled when QLM SPD is 15. */ ++ if (qlm_cfg.s.qlm_spd == 15) ++ return CVMX_HELPER_INTERFACE_MODE_DISABLED; ++ ++ if (qlm_cfg.s.qlm_cfg == 2) ++ return CVMX_HELPER_INTERFACE_MODE_SGMII; ++ else if (qlm_cfg.s.qlm_cfg == 3) ++ return CVMX_HELPER_INTERFACE_MODE_XAUI; ++ else ++ return CVMX_HELPER_INTERFACE_MODE_DISABLED; ++ case 2: ++ case 3: ++ case 4: ++ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(interface)); ++ /* QLM is disabled when QLM SPD is 15. */ ++ if (qlm_cfg.s.qlm_spd == 15) ++ return CVMX_HELPER_INTERFACE_MODE_DISABLED; ++ ++ if (qlm_cfg.s.qlm_cfg == 2) ++ return CVMX_HELPER_INTERFACE_MODE_SGMII; ++ else if (qlm_cfg.s.qlm_cfg == 3) ++ return CVMX_HELPER_INTERFACE_MODE_XAUI; ++ else ++ return CVMX_HELPER_INTERFACE_MODE_DISABLED; ++ case 7: ++ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(3)); ++ /* QLM is disabled when QLM SPD is 15. */ ++ if (qlm_cfg.s.qlm_spd == 15) { ++ return CVMX_HELPER_INTERFACE_MODE_DISABLED; ++ } else if (qlm_cfg.s.qlm_cfg != 0) { ++ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(1)); ++ if (qlm_cfg.s.qlm_cfg != 0) ++ return CVMX_HELPER_INTERFACE_MODE_DISABLED; ++ } ++ return CVMX_HELPER_INTERFACE_MODE_NPI; ++ case 8: ++ return CVMX_HELPER_INTERFACE_MODE_LOOP; ++ default: ++ return CVMX_HELPER_INTERFACE_MODE_DISABLED; ++ } ++} ++ ++/** ++ * @INTERNAL ++ * Return interface mode for an Octeon II ++ */ ++static cvmx_helper_interface_mode_t __cvmx_get_mode_octeon2(int interface) ++{ ++ union cvmx_gmxx_inf_mode mode; ++ ++ if (OCTEON_IS_MODEL(OCTEON_CN68XX)) ++ return __cvmx_get_mode_cn68xx(interface); ++ ++ if (interface == 2) ++ return CVMX_HELPER_INTERFACE_MODE_NPI; ++ ++ if (interface == 3) ++ return CVMX_HELPER_INTERFACE_MODE_LOOP; ++ ++ /* Only present in CN63XX & CN66XX Octeon model */ ++ if ((OCTEON_IS_MODEL(OCTEON_CN63XX) && ++ (interface == 4 || interface == 5)) || ++ (OCTEON_IS_MODEL(OCTEON_CN66XX) && ++ interface >= 4 && interface <= 7)) { ++ return CVMX_HELPER_INTERFACE_MODE_DISABLED; ++ } ++ ++ if (OCTEON_IS_MODEL(OCTEON_CN66XX)) { ++ union cvmx_mio_qlmx_cfg mio_qlm_cfg; ++ ++ /* QLM2 is SGMII0 and QLM1 is SGMII1 */ ++ if (interface == 0) ++ mio_qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(2)); ++ else if (interface == 1) ++ mio_qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(1)); ++ else ++ return CVMX_HELPER_INTERFACE_MODE_DISABLED; ++ ++ if (mio_qlm_cfg.s.qlm_spd == 15) ++ return CVMX_HELPER_INTERFACE_MODE_DISABLED; ++ ++ if (mio_qlm_cfg.s.qlm_cfg == 9) ++ return CVMX_HELPER_INTERFACE_MODE_SGMII; ++ else if (mio_qlm_cfg.s.qlm_cfg == 11) ++ return CVMX_HELPER_INTERFACE_MODE_XAUI; ++ else ++ return CVMX_HELPER_INTERFACE_MODE_DISABLED; ++ } else if (OCTEON_IS_MODEL(OCTEON_CN61XX)) { ++ union cvmx_mio_qlmx_cfg qlm_cfg; ++ ++ if (interface == 0) { ++ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(2)); ++ if (qlm_cfg.s.qlm_cfg == 2) ++ return CVMX_HELPER_INTERFACE_MODE_SGMII; ++ else if (qlm_cfg.s.qlm_cfg == 3) ++ return CVMX_HELPER_INTERFACE_MODE_XAUI; ++ else ++ return CVMX_HELPER_INTERFACE_MODE_DISABLED; ++ } else if (interface == 1) { ++ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0)); ++ if (qlm_cfg.s.qlm_cfg == 2) ++ return CVMX_HELPER_INTERFACE_MODE_SGMII; ++ else if (qlm_cfg.s.qlm_cfg == 3) ++ return CVMX_HELPER_INTERFACE_MODE_XAUI; ++ else ++ return CVMX_HELPER_INTERFACE_MODE_DISABLED; ++ } ++ } else if (OCTEON_IS_MODEL(OCTEON_CNF71XX)) { ++ if (interface == 0) { ++ union cvmx_mio_qlmx_cfg qlm_cfg; ++ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0)); ++ if (qlm_cfg.s.qlm_cfg == 2) ++ return CVMX_HELPER_INTERFACE_MODE_SGMII; ++ } ++ return CVMX_HELPER_INTERFACE_MODE_DISABLED; ++ } ++ ++ if (interface == 1 && OCTEON_IS_MODEL(OCTEON_CN63XX)) ++ return CVMX_HELPER_INTERFACE_MODE_DISABLED; ++ ++ mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); ++ ++ if (OCTEON_IS_MODEL(OCTEON_CN63XX)) { ++ switch (mode.cn63xx.mode) { ++ case 0: ++ return CVMX_HELPER_INTERFACE_MODE_SGMII; ++ case 1: ++ return CVMX_HELPER_INTERFACE_MODE_XAUI; ++ default: ++ return CVMX_HELPER_INTERFACE_MODE_DISABLED; ++ } ++ } else { ++ if (!mode.s.en) ++ return CVMX_HELPER_INTERFACE_MODE_DISABLED; ++ ++ if (mode.s.type) ++ return CVMX_HELPER_INTERFACE_MODE_GMII; ++ else ++ return CVMX_HELPER_INTERFACE_MODE_RGMII; ++ } ++} ++ ++/** + * Get the operating mode of an interface. Depending on the Octeon + * chip and configuration, this function returns an enumeration + * of the type of packet I/O supported by an interface. +@@ -118,6 +270,20 @@ EXPORT_SYMBOL_GPL(cvmx_helper_ports_on_interface); + cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface) + { + union cvmx_gmxx_inf_mode mode; ++ ++ if (interface < 0 || ++ interface >= cvmx_helper_get_number_of_interfaces()) ++ return CVMX_HELPER_INTERFACE_MODE_DISABLED; ++ ++ /* ++ * Octeon II models ++ */ ++ if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)) ++ return __cvmx_get_mode_octeon2(interface); ++ ++ /* ++ * Octeon and Octeon Plus models ++ */ + if (interface == 2) + return CVMX_HELPER_INTERFACE_MODE_NPI; + +-- +2.0.0 + diff --git a/debian/patches/series b/debian/patches/series index 4cd34c652..466b73216 100644 --- a/debian/patches/series +++ b/debian/patches/series @@ -98,3 +98,5 @@ features/mips/0010-MIPS-Loongson-Add-Loongson-3-Kconfig-options.patch features/mips/0011-MIPS-Loongson-3-Add-Loongson-3-SMP-support.patch features/mips/0012-MIPS-Loongson-3-Add-CPU-hotplug-support.patch features/mips/0013-MIPS-Loongson-Add-a-Loongson-3-default-config-file.patch +features/mips/MIPS-Octeon-Add-PCIe2-support-in-arch_setup_msi_irq.patch +features/mips/MIPS-octeon-Add-interface-mode-detection-for-Octeon-.patch