[x86] amd64_edac: Fix single-channel setups (Closes: #717473)
svn path=/dists/sid/linux/; revision=20570
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@ -56,6 +56,7 @@ linux (3.10.10-1) UNRELEASED; urgency=low
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* aufs: Update to aufs3.10-20130826
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* aufs: Update to aufs3.10-20130826
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* aufs: mvdown, don't let unprivileged users provoke a WARNING
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* aufs: mvdown, don't let unprivileged users provoke a WARNING
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* [x86] ACPI: Re-enable ACPI_HOTPLUG_MEMORY as built-in
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* [x86] ACPI: Re-enable ACPI_HOTPLUG_MEMORY as built-in
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* [x86] amd64_edac: Fix single-channel setups (Closes: #717473)
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[ Ian Campbell ]
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[ Ian Campbell ]
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* [armel]: Enable MVMDIO and USB_EHCI_HCD_ORION on Kirkwood and Orion
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* [armel]: Enable MVMDIO and USB_EHCI_HCD_ORION on Kirkwood and Orion
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@ -0,0 +1,46 @@
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From: Borislav Petkov <bp@suse.de>
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Date: Tue, 23 Jul 2013 20:01:23 +0200
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Subject: amd64_edac: Fix single-channel setups
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Origin: https://git.kernel.org/linus/f0a56c480196a98479760862468cc95879df3de0
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Bug-Debian: http://bugs.debian.org/717473
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It can happen that configurations are running in a single-channel mode
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even with a dual-channel memory controller, by, say, putting the DIMMs
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only on the one channel and leaving the other empty. This causes a
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problem in init_csrows which implicitly assumes that when the second
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channel is enabled, i.e. channel 1, the struct dimm hierarchy will be
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present. Which is not.
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So always allocate two channels unconditionally.
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This provides for the nice side effect that the data structures are
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initialized so some day, when memory hotplug is supported, it should
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just work out of the box when all of a sudden a second channel appears.
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Reported-and-tested-by: Roger Leigh <rleigh@debian.org>
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Signed-off-by: Borislav Petkov <bp@suse.de>
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---
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drivers/edac/amd64_edac.c | 9 ++++++++-
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1 file changed, 8 insertions(+), 1 deletion(-)
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diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
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index 8b6a034..8b3d901 100644
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--- a/drivers/edac/amd64_edac.c
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+++ b/drivers/edac/amd64_edac.c
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@@ -2470,8 +2470,15 @@ static int amd64_init_one_instance(struct pci_dev *F2)
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layers[0].size = pvt->csels[0].b_cnt;
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layers[0].is_virt_csrow = true;
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layers[1].type = EDAC_MC_LAYER_CHANNEL;
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- layers[1].size = pvt->channel_count;
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+
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+ /*
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+ * Always allocate two channels since we can have setups with DIMMs on
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+ * only one channel. Also, this simplifies handling later for the price
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+ * of a couple of KBs tops.
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+ */
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+ layers[1].size = 2;
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layers[1].is_virt_csrow = false;
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+
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mci = edac_mc_alloc(nid, ARRAY_SIZE(layers), layers, 0);
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if (!mci)
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goto err_siblings;
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@ -118,3 +118,4 @@ bugfix/arm/I2C-mv64xxx-fix-race-between-FSM-interrupt-and-proce.patch
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bugfix/arm/ARM-Fix-the-world-famous-typo-with-is_gate_vma.patch
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bugfix/arm/ARM-Fix-the-world-famous-typo-with-is_gate_vma.patch
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# ABI stability
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# ABI stability
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bugfix/x86/amd64_edac-Fix-single-channel-setups.patch
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