141 lines
4.6 KiB
Diff
141 lines
4.6 KiB
Diff
From: "Maciej W. Rozycki" <macro@imgtec.com>
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Date: Fri, 22 Jan 2016 05:20:26 +0000
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Subject: MIPS: math-emu: Correctly handle NOP emulation
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Origin: https://git.kernel.org/linus/e4553573b37c3f72533683cb5f3a1ad300b18d37
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Fix an issue introduced with commit 9ab4471c9f1b ("MIPS: math-emu:
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Correct delay-slot exception propagation") where the emulation of a NOP
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instruction signals the need to terminate the emulation loop. This in
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turn, if the PC has not changed from the entry to the loop, will cause
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the kernel to terminate the program with SIGILL.
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Consider this program:
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static double div(double d)
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{
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do
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d /= 2.0;
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while (d > .5);
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return d;
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}
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int main(int argc, char **argv)
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{
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return div(argc);
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}
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which gets compiled to the following binary code:
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00400490 <main>:
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400490: 44840000 mtc1 a0,$f0
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400494: 3c020040 lui v0,0x40
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400498: d44207f8 ldc1 $f2,2040(v0)
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40049c: 46800021 cvt.d.w $f0,$f0
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4004a0: 46220002 mul.d $f0,$f0,$f2
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4004a4: 4620103c c.lt.d $f2,$f0
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4004a8: 4501fffd bc1t 4004a0 <main+0x10>
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4004ac: 00000000 nop
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4004b0: 4620000d trunc.w.d $f0,$f0
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4004b4: 03e00008 jr ra
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4004b8: 44020000 mfc1 v0,$f0
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4004bc: 00000000 nop
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Where the FPU emulator is used, depending on the number of command-line
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arguments this code will either run to completion or terminate with
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SIGILL.
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If no arguments are specified, then BC1T will not be taken, NOP will not
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be emulated and code will complete successfully.
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If one argument is specified, then BC1T will be taken once and NOP will
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be emulated. At this point the entry PC value will be 0x400498 and the
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new PC value, set by `mips_dsemul' will be 0x4004a0, the target of BC1T.
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The emulation loop will terminate, but SIGILL will not be issued,
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because the PC has changed. The FPU emulator will be entered again and
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on the second execution BC1T will not be taken, NOP will not be emulated
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and code will complete successfully.
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If two or more arguments are specified, then the first execution of BC1T
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will proceed as above. Upon reentering the FPU emulator the emulation
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loop will continue to BC1T, at which point the branch will be taken and
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NOP emulated again. At this point however the entry PC value will be
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0x4004a0, the same as the target of BC1T. This will make the emulator
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conclude that execution has not advanced and therefore an unsupported
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FPU instruction has been encountered, and SIGILL will be sent to the
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process.
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Fix the problem by extending the internal API of `mips_dsemul', making
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it return -1 if no delay slot emulation frame has been made, the
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instruction has been handled and execution of the emulation loop needs
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to continue as if nothing happened. Remove code from `mips_dsemul' to
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reproduce steps made by the emulation loop at the conclusion of each
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iteration, as those will be reached normally now. Adjust call sites
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accordingly. Document the API.
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Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
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Cc: Aurelien Jarno <aurelien@aurel32.net>
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Cc: linux-mips@linux-mips.org
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Patchwork: https://patchwork.linux-mips.org/patch/12172/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/math-emu/cp1emu.c | 4 ++++
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arch/mips/math-emu/dsemul.c | 14 ++++++++------
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2 files changed, 12 insertions(+), 6 deletions(-)
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diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
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index 32f0e19..cdfd44f 100644
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--- a/arch/mips/math-emu/cp1emu.c
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+++ b/arch/mips/math-emu/cp1emu.c
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@@ -1266,6 +1266,8 @@ branch_common:
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*/
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sig = mips_dsemul(xcp, ir,
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contpc);
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+ if (sig < 0)
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+ break;
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if (sig)
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xcp->cp0_epc = bcpc;
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/*
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@@ -1319,6 +1321,8 @@ branch_common:
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* instruction in the dslot
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*/
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sig = mips_dsemul(xcp, ir, contpc);
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+ if (sig < 0)
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+ break;
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if (sig)
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xcp->cp0_epc = bcpc;
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/* SIGILL forces out of the emulation loop. */
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diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c
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index cbb36c1..70e4824 100644
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--- a/arch/mips/math-emu/dsemul.c
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+++ b/arch/mips/math-emu/dsemul.c
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@@ -31,18 +31,20 @@ struct emuframe {
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unsigned long epc;
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};
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+/*
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+ * Set up an emulation frame for instruction IR, from a delay slot of
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+ * a branch jumping to CPC. Return 0 if successful, -1 if no emulation
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+ * required, otherwise a signal number causing a frame setup failure.
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+ */
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int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
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{
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struct emuframe __user *fr;
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int err;
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+ /* NOP is easy */
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if ((get_isa16_mode(regs->cp0_epc) && ((ir >> 16) == MM_NOP16)) ||
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- (ir == 0)) {
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- /* NOP is easy */
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- regs->cp0_epc = cpc;
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- clear_delay_slot(regs);
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- return 0;
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- }
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+ (ir == 0))
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+ return -1;
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pr_debug("dsemul %lx %lx\n", regs->cp0_epc, cpc);
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--
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2.7.0.rc3
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