718 lines
24 KiB
Diff
718 lines
24 KiB
Diff
--- a/drivers/gpu/drm/i915/i915_debugfs.c
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+++ b/drivers/gpu/drm/i915/i915_debugfs.c
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@@ -162,7 +162,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
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struct drm_device *dev = node->minor->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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- if (!IS_IRONLAKE(dev)) {
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+ if (!HAS_PCH_SPLIT(dev)) {
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seq_printf(m, "Interrupt enable: %08x\n",
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I915_READ(IER));
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seq_printf(m, "Interrupt identity: %08x\n",
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--- a/drivers/gpu/drm/i915/i915_dma.c
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+++ b/drivers/gpu/drm/i915/i915_dma.c
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@@ -978,15 +978,21 @@ static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
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* Some of the preallocated space is taken by the GTT
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* and popup. GTT is 1K per MB of aperture size, and popup is 4K.
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*/
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- if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev))
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+ if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev))
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overhead = 4096;
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else
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overhead = (*aperture_size / 1024) + 4096;
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switch (tmp & INTEL_GMCH_GMS_MASK) {
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case INTEL_855_GMCH_GMS_DISABLED:
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- DRM_ERROR("video memory is disabled\n");
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- return -1;
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+ /* XXX: This is what my A1 silicon has. */
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+ if (IS_GEN6(dev)) {
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+ stolen = 64 * 1024 * 1024;
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+ } else {
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+ DRM_ERROR("video memory is disabled\n");
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+ return -1;
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+ }
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+ break;
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case INTEL_855_GMCH_GMS_STOLEN_1M:
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stolen = 1 * 1024 * 1024;
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break;
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@@ -1064,7 +1070,7 @@ static unsigned long i915_gtt_to_phys(struct drm_device *dev,
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int gtt_offset, gtt_size;
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if (IS_I965G(dev)) {
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- if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
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+ if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
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gtt_offset = 2*1024*1024;
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gtt_size = 2*1024*1024;
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} else {
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@@ -1445,7 +1451,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
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dev->driver->get_vblank_counter = i915_get_vblank_counter;
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dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
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- if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
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+ if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
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dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
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dev->driver->get_vblank_counter = gm45_get_vblank_counter;
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}
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--- a/drivers/gpu/drm/i915/i915_drv.h
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+++ b/drivers/gpu/drm/i915/i915_drv.h
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@@ -1026,7 +1026,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
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#define IS_845G(dev) ((dev)->pci_device == 0x2562)
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#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
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#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
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-#define IS_I8XX(dev) (INTEL_INFO(dev)->is_i8xx)
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+#define IS_GEN2(dev) (INTEL_INFO(dev)->is_i8xx)
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#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
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#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
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#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
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@@ -1045,8 +1045,29 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
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#define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx)
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#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
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+#define IS_GEN3(dev) (IS_I915G(dev) || \
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+ IS_I915GM(dev) || \
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+ IS_I945G(dev) || \
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+ IS_I945GM(dev) || \
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+ IS_G33(dev) || \
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+ IS_PINEVIEW(dev))
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+#define IS_GEN4(dev) ((dev)->pci_device == 0x2972 || \
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+ (dev)->pci_device == 0x2982 || \
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+ (dev)->pci_device == 0x2992 || \
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+ (dev)->pci_device == 0x29A2 || \
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+ (dev)->pci_device == 0x2A02 || \
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+ (dev)->pci_device == 0x2A12 || \
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+ (dev)->pci_device == 0x2E02 || \
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+ (dev)->pci_device == 0x2E12 || \
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+ (dev)->pci_device == 0x2E22 || \
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+ (dev)->pci_device == 0x2E32 || \
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+ (dev)->pci_device == 0x2A42 || \
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+ (dev)->pci_device == 0x2E42)
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+
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#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
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+#define IS_GEN6(dev) ((dev)->pci_device == 0x0102)
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+
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/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
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* rows, which changed the alignment requirements and fence programming.
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*/
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@@ -1067,6 +1088,9 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
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#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
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#define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
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+#define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \
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+ IS_GEN6(dev))
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+
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#define PRIMARY_RINGBUFFER_SIZE (128*1024)
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#endif
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--- a/drivers/gpu/drm/i915/i915_gem.c
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+++ b/drivers/gpu/drm/i915/i915_gem.c
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@@ -1819,7 +1819,7 @@ i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible)
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return -EIO;
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if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
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- if (IS_IRONLAKE(dev))
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+ if (HAS_PCH_SPLIT(dev))
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ier = I915_READ(DEIER) | I915_READ(GTIER);
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else
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ier = I915_READ(IER);
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@@ -2316,6 +2316,12 @@ static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
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pitch_val = obj_priv->stride / tile_width;
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pitch_val = ffs(pitch_val) - 1;
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+ if (obj_priv->tiling_mode == I915_TILING_Y &&
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+ HAS_128_BYTE_Y_TILING(dev))
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+ WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
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+ else
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+ WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
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+
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val = obj_priv->gtt_offset;
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if (obj_priv->tiling_mode == I915_TILING_Y)
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val |= 1 << I830_FENCE_TILING_Y_SHIFT;
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--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
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+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
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@@ -209,7 +209,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
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uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
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bool need_disable;
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- if (IS_IRONLAKE(dev)) {
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+ if (IS_IRONLAKE(dev) || IS_GEN6(dev)) {
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/* On Ironlake whatever DRAM config, GPU always do
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* same swizzling setup.
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*/
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@@ -357,21 +357,17 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
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* reg, so dont bother to check the size */
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if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
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return false;
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- } else if (IS_I9XX(dev)) {
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- uint32_t pitch_val = ffs(stride / tile_width) - 1;
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-
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- /* XXX: For Y tiling, FENCE_MAX_PITCH_VAL is actually 6 (8KB)
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- * instead of 4 (2KB) on 945s.
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- */
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- if (pitch_val > I915_FENCE_MAX_PITCH_VAL ||
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- size > (I830_FENCE_MAX_SIZE_VAL << 20))
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+ } else if (IS_GEN3(dev) || IS_GEN2(dev)) {
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+ if (stride > 8192)
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return false;
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- } else {
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- uint32_t pitch_val = ffs(stride / tile_width) - 1;
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- if (pitch_val > I830_FENCE_MAX_PITCH_VAL ||
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- size > (I830_FENCE_MAX_SIZE_VAL << 19))
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- return false;
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+ if (IS_GEN3(dev)) {
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+ if (size > I830_FENCE_MAX_SIZE_VAL << 20)
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+ return false;
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+ } else {
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+ if (size > I830_FENCE_MAX_SIZE_VAL << 19)
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+ return false;
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+ }
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}
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/* 965+ just needs multiples of tile width */
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--- a/drivers/gpu/drm/i915/i915_irq.c
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+++ b/drivers/gpu/drm/i915/i915_irq.c
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@@ -576,7 +576,7 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
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atomic_inc(&dev_priv->irq_received);
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- if (IS_IRONLAKE(dev))
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+ if (HAS_PCH_SPLIT(dev))
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return ironlake_irq_handler(dev);
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iir = I915_READ(IIR);
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@@ -737,7 +737,7 @@ void i915_user_irq_get(struct drm_device *dev)
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spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
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if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
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- if (IS_IRONLAKE(dev))
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+ if (HAS_PCH_SPLIT(dev))
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ironlake_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
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else
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i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
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@@ -753,7 +753,7 @@ void i915_user_irq_put(struct drm_device *dev)
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spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
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BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
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if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
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- if (IS_IRONLAKE(dev))
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+ if (HAS_PCH_SPLIT(dev))
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ironlake_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
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else
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i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
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@@ -861,7 +861,7 @@ int i915_enable_vblank(struct drm_device *dev, int pipe)
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return -EINVAL;
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spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
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- if (IS_IRONLAKE(dev))
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+ if (HAS_PCH_SPLIT(dev))
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ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
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DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
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else if (IS_I965G(dev))
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@@ -883,7 +883,7 @@ void i915_disable_vblank(struct drm_device *dev, int pipe)
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unsigned long irqflags;
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spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
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- if (IS_IRONLAKE(dev))
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+ if (HAS_PCH_SPLIT(dev))
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ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
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DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
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else
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@@ -897,7 +897,7 @@ void i915_enable_interrupt (struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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- if (!IS_IRONLAKE(dev))
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+ if (!HAS_PCH_SPLIT(dev))
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opregion_enable_asle(dev);
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dev_priv->irq_enabled = 1;
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}
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@@ -1076,7 +1076,7 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
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INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
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INIT_WORK(&dev_priv->error_work, i915_error_work_func);
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- if (IS_IRONLAKE(dev)) {
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+ if (HAS_PCH_SPLIT(dev)) {
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ironlake_irq_preinstall(dev);
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return;
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}
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@@ -1108,7 +1108,7 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
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dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
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- if (IS_IRONLAKE(dev))
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+ if (HAS_PCH_SPLIT(dev))
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return ironlake_irq_postinstall(dev);
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/* Unmask the interrupts that we always want on. */
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@@ -1196,7 +1196,7 @@ void i915_driver_irq_uninstall(struct drm_device * dev)
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dev_priv->vblank_pipe = 0;
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- if (IS_IRONLAKE(dev)) {
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+ if (HAS_PCH_SPLIT(dev)) {
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ironlake_irq_uninstall(dev);
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return;
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}
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--- a/drivers/gpu/drm/i915/i915_reg.h
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+++ b/drivers/gpu/drm/i915/i915_reg.h
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@@ -221,7 +221,7 @@
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#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
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#define I830_FENCE_PITCH_SHIFT 4
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#define I830_FENCE_REG_VALID (1<<0)
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-#define I915_FENCE_MAX_PITCH_VAL 0x10
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+#define I915_FENCE_MAX_PITCH_VAL 4
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#define I830_FENCE_MAX_PITCH_VAL 6
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#define I830_FENCE_MAX_SIZE_VAL (1<<8)
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--- a/drivers/gpu/drm/i915/intel_bios.c
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+++ b/drivers/gpu/drm/i915/intel_bios.c
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@@ -247,6 +247,7 @@ static void
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parse_general_features(struct drm_i915_private *dev_priv,
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struct bdb_header *bdb)
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{
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+ struct drm_device *dev = dev_priv->dev;
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struct bdb_general_features *general;
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/* Set sensible defaults in case we can't find the general block */
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@@ -263,7 +264,7 @@ parse_general_features(struct drm_i915_private *dev_priv,
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if (IS_I85X(dev_priv->dev))
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dev_priv->lvds_ssc_freq =
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general->ssc_freq ? 66 : 48;
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- else if (IS_IRONLAKE(dev_priv->dev))
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+ else if (IS_IRONLAKE(dev_priv->dev) || IS_GEN6(dev))
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dev_priv->lvds_ssc_freq =
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general->ssc_freq ? 100 : 120;
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else
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--- a/drivers/gpu/drm/i915/intel_crt.c
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+++ b/drivers/gpu/drm/i915/intel_crt.c
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@@ -39,7 +39,7 @@ static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 temp, reg;
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- if (IS_IRONLAKE(dev))
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+ if (HAS_PCH_SPLIT(dev))
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reg = PCH_ADPA;
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else
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reg = ADPA;
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@@ -113,7 +113,7 @@ static void intel_crt_mode_set(struct drm_encoder *encoder,
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else
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dpll_md_reg = DPLL_B_MD;
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- if (IS_IRONLAKE(dev))
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+ if (HAS_PCH_SPLIT(dev))
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adpa_reg = PCH_ADPA;
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else
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adpa_reg = ADPA;
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@@ -122,7 +122,7 @@ static void intel_crt_mode_set(struct drm_encoder *encoder,
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* Disable separate mode multiplier used when cloning SDVO to CRT
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* XXX this needs to be adjusted when we really are cloning
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*/
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- if (IS_I965G(dev) && !IS_IRONLAKE(dev)) {
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+ if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
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dpll_md = I915_READ(dpll_md_reg);
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I915_WRITE(dpll_md_reg,
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dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
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@@ -136,11 +136,11 @@ static void intel_crt_mode_set(struct drm_encoder *encoder,
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if (intel_crtc->pipe == 0) {
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adpa |= ADPA_PIPE_A_SELECT;
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- if (!IS_IRONLAKE(dev))
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+ if (!HAS_PCH_SPLIT(dev))
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I915_WRITE(BCLRPAT_A, 0);
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} else {
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adpa |= ADPA_PIPE_B_SELECT;
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- if (!IS_IRONLAKE(dev))
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+ if (!HAS_PCH_SPLIT(dev))
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I915_WRITE(BCLRPAT_B, 0);
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}
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@@ -202,7 +202,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
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u32 hotplug_en;
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int i, tries = 0;
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- if (IS_IRONLAKE(dev))
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+ if (HAS_PCH_SPLIT(dev))
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return intel_ironlake_crt_detect_hotplug(connector);
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/*
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@@ -524,7 +524,7 @@ void intel_crt_init(struct drm_device *dev)
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&intel_output->enc);
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/* Set up the DDC bus. */
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- if (IS_IRONLAKE(dev))
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+ if (HAS_PCH_SPLIT(dev))
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i2c_reg = PCH_GPIOA;
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else {
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i2c_reg = GPIOA;
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--- a/drivers/gpu/drm/i915/intel_display.c
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+++ b/drivers/gpu/drm/i915/intel_display.c
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@@ -232,7 +232,7 @@ struct intel_limit {
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#define G4X_P2_DISPLAY_PORT_FAST 10
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#define G4X_P2_DISPLAY_PORT_LIMIT 0
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-/* Ironlake */
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+/* Ironlake / Sandybridge */
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/* as we calculate clock using (register_value + 2) for
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N/M1/M2, so here the range value for them is (actual_value-2).
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*/
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@@ -690,7 +690,7 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
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struct drm_device *dev = crtc->dev;
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const intel_limit_t *limit;
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- if (IS_IRONLAKE(dev))
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+ if (HAS_PCH_SPLIT(dev))
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limit = intel_ironlake_limit(crtc);
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else if (IS_G4X(dev)) {
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limit = intel_g4x_limit(crtc);
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@@ -1366,7 +1366,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
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dspcntr &= ~DISPPLANE_TILED;
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}
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- if (IS_IRONLAKE(dev))
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+ if (HAS_PCH_SPLIT(dev))
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/* must disable */
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dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
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@@ -1427,7 +1427,7 @@ static void i915_disable_vga (struct drm_device *dev)
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u8 sr1;
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u32 vga_reg;
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- if (IS_IRONLAKE(dev))
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+ if (HAS_PCH_SPLIT(dev))
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vga_reg = CPU_VGACNTRL;
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else
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vga_reg = VGACNTRL;
|
|
@@ -2111,7 +2111,7 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
|
|
struct drm_display_mode *adjusted_mode)
|
|
{
|
|
struct drm_device *dev = crtc->dev;
|
|
- if (IS_IRONLAKE(dev)) {
|
|
+ if (HAS_PCH_SPLIT(dev)) {
|
|
/* FDI link clock is fixed at 2.7G */
|
|
if (mode->clock * 3 > 27000 * 4)
|
|
return MODE_CLOCK_HIGH;
|
|
@@ -2967,7 +2967,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
|
|
refclk / 1000);
|
|
} else if (IS_I9XX(dev)) {
|
|
refclk = 96000;
|
|
- if (IS_IRONLAKE(dev))
|
|
+ if (HAS_PCH_SPLIT(dev))
|
|
refclk = 120000; /* 120Mhz refclk */
|
|
} else {
|
|
refclk = 48000;
|
|
@@ -3025,7 +3025,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
|
|
}
|
|
|
|
/* FDI link */
|
|
- if (IS_IRONLAKE(dev)) {
|
|
+ if (HAS_PCH_SPLIT(dev)) {
|
|
int lane, link_bw, bpp;
|
|
/* eDP doesn't require FDI link, so just set DP M/N
|
|
according to current link config */
|
|
@@ -3102,7 +3102,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
|
|
* PCH B stepping, previous chipset stepping should be
|
|
* ignoring this setting.
|
|
*/
|
|
- if (IS_IRONLAKE(dev)) {
|
|
+ if (HAS_PCH_SPLIT(dev)) {
|
|
temp = I915_READ(PCH_DREF_CONTROL);
|
|
/* Always enable nonspread source */
|
|
temp &= ~DREF_NONSPREAD_SOURCE_MASK;
|
|
@@ -3149,7 +3149,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
|
|
reduced_clock.m2;
|
|
}
|
|
|
|
- if (!IS_IRONLAKE(dev))
|
|
+ if (!HAS_PCH_SPLIT(dev))
|
|
dpll = DPLL_VGA_MODE_DIS;
|
|
|
|
if (IS_I9XX(dev)) {
|
|
@@ -3162,7 +3162,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
|
|
sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
|
|
if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
|
|
dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
|
|
- else if (IS_IRONLAKE(dev))
|
|
+ else if (HAS_PCH_SPLIT(dev))
|
|
dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
|
|
}
|
|
if (is_dp)
|
|
@@ -3174,7 +3174,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
|
|
else {
|
|
dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
|
|
/* also FPA1 */
|
|
- if (IS_IRONLAKE(dev))
|
|
+ if (HAS_PCH_SPLIT(dev))
|
|
dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
|
|
if (IS_G4X(dev) && has_reduced_clock)
|
|
dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
|
|
@@ -3193,7 +3193,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
|
|
dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
|
|
break;
|
|
}
|
|
- if (IS_I965G(dev) && !IS_IRONLAKE(dev))
|
|
+ if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
|
|
dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
|
|
} else {
|
|
if (is_lvds) {
|
|
@@ -3227,7 +3227,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
|
|
|
|
/* Ironlake's plane is forced to pipe, bit 24 is to
|
|
enable color space conversion */
|
|
- if (!IS_IRONLAKE(dev)) {
|
|
+ if (!HAS_PCH_SPLIT(dev)) {
|
|
if (pipe == 0)
|
|
dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
|
|
else
|
|
@@ -3254,14 +3254,14 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
|
|
|
|
|
|
/* Disable the panel fitter if it was on our pipe */
|
|
- if (!IS_IRONLAKE(dev) && intel_panel_fitter_pipe(dev) == pipe)
|
|
+ if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
|
|
I915_WRITE(PFIT_CONTROL, 0);
|
|
|
|
DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
|
|
drm_mode_debug_printmodeline(mode);
|
|
|
|
/* assign to Ironlake registers */
|
|
- if (IS_IRONLAKE(dev)) {
|
|
+ if (HAS_PCH_SPLIT(dev)) {
|
|
fp_reg = pch_fp_reg;
|
|
dpll_reg = pch_dpll_reg;
|
|
}
|
|
@@ -3282,7 +3282,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
|
|
if (is_lvds) {
|
|
u32 lvds;
|
|
|
|
- if (IS_IRONLAKE(dev))
|
|
+ if (HAS_PCH_SPLIT(dev))
|
|
lvds_reg = PCH_LVDS;
|
|
|
|
lvds = I915_READ(lvds_reg);
|
|
@@ -3328,7 +3328,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
|
|
/* Wait for the clocks to stabilize. */
|
|
udelay(150);
|
|
|
|
- if (IS_I965G(dev) && !IS_IRONLAKE(dev)) {
|
|
+ if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
|
|
if (is_sdvo) {
|
|
sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
|
|
I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
|
|
@@ -3375,14 +3375,14 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
|
|
/* pipesrc and dspsize control the size that is scaled from, which should
|
|
* always be the user's requested size.
|
|
*/
|
|
- if (!IS_IRONLAKE(dev)) {
|
|
+ if (!HAS_PCH_SPLIT(dev)) {
|
|
I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
|
|
(mode->hdisplay - 1));
|
|
I915_WRITE(dsppos_reg, 0);
|
|
}
|
|
I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
|
|
|
|
- if (IS_IRONLAKE(dev)) {
|
|
+ if (HAS_PCH_SPLIT(dev)) {
|
|
I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
|
|
I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
|
|
I915_WRITE(link_m1_reg, m_n.link_m);
|
|
@@ -3403,7 +3403,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
|
|
|
|
intel_wait_for_vblank(dev);
|
|
|
|
- if (IS_IRONLAKE(dev)) {
|
|
+ if (HAS_PCH_SPLIT(dev)) {
|
|
/* enable address swizzle for tiling buffer */
|
|
temp = I915_READ(DISP_ARB_CTL);
|
|
I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
|
|
@@ -3438,7 +3438,7 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
|
|
return;
|
|
|
|
/* use legacy palette for Ironlake */
|
|
- if (IS_IRONLAKE(dev))
|
|
+ if (HAS_PCH_SPLIT(dev))
|
|
palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
|
|
LGC_PALETTE_B;
|
|
|
|
@@ -3922,7 +3922,7 @@ static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
|
|
int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
|
|
int dpll = I915_READ(dpll_reg);
|
|
|
|
- if (IS_IRONLAKE(dev))
|
|
+ if (HAS_PCH_SPLIT(dev))
|
|
return;
|
|
|
|
if (!dev_priv->lvds_downclock_avail)
|
|
@@ -3961,7 +3961,7 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
|
|
int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
|
|
int dpll = I915_READ(dpll_reg);
|
|
|
|
- if (IS_IRONLAKE(dev))
|
|
+ if (HAS_PCH_SPLIT(dev))
|
|
return;
|
|
|
|
if (!dev_priv->lvds_downclock_avail)
|
|
@@ -4382,7 +4382,7 @@ static void intel_setup_outputs(struct drm_device *dev)
|
|
if (IS_MOBILE(dev) && !IS_I830(dev))
|
|
intel_lvds_init(dev);
|
|
|
|
- if (IS_IRONLAKE(dev)) {
|
|
+ if (HAS_PCH_SPLIT(dev)) {
|
|
int found;
|
|
|
|
if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
|
|
@@ -4451,7 +4451,7 @@ static void intel_setup_outputs(struct drm_device *dev)
|
|
DRM_DEBUG_KMS("probing DP_D\n");
|
|
intel_dp_init(dev, DP_D);
|
|
}
|
|
- } else if (IS_I8XX(dev))
|
|
+ } else if (IS_GEN2(dev))
|
|
intel_dvo_init(dev);
|
|
|
|
if (SUPPORTS_TV(dev))
|
|
@@ -4599,7 +4599,7 @@ void intel_init_clock_gating(struct drm_device *dev)
|
|
* Disable clock gating reported to work incorrectly according to the
|
|
* specs, but enable as much else as we can.
|
|
*/
|
|
- if (IS_IRONLAKE(dev)) {
|
|
+ if (HAS_PCH_SPLIT(dev)) {
|
|
return;
|
|
} else if (IS_G4X(dev)) {
|
|
uint32_t dspclk_gate;
|
|
@@ -4672,7 +4672,7 @@ static void intel_init_display(struct drm_device *dev)
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
/* We always want a DPMS function */
|
|
- if (IS_IRONLAKE(dev))
|
|
+ if (HAS_PCH_SPLIT(dev))
|
|
dev_priv->display.dpms = ironlake_crtc_dpms;
|
|
else
|
|
dev_priv->display.dpms = i9xx_crtc_dpms;
|
|
@@ -4715,7 +4715,7 @@ static void intel_init_display(struct drm_device *dev)
|
|
i830_get_display_clock_speed;
|
|
|
|
/* For FIFO watermark updates */
|
|
- if (IS_IRONLAKE(dev))
|
|
+ if (HAS_PCH_SPLIT(dev))
|
|
dev_priv->display.update_wm = NULL;
|
|
else if (IS_G4X(dev))
|
|
dev_priv->display.update_wm = g4x_update_wm;
|
|
--- a/drivers/gpu/drm/i915/intel_lvds.c
|
|
+++ b/drivers/gpu/drm/i915/intel_lvds.c
|
|
@@ -661,7 +661,7 @@ static enum drm_connector_status intel_lvds_detect(struct drm_connector *connect
|
|
/* ACPI lid methods were generally unreliable in this generation, so
|
|
* don't even bother.
|
|
*/
|
|
- if (IS_I8XX(dev))
|
|
+ if (IS_GEN2(dev))
|
|
return connector_status_connected;
|
|
|
|
if (!dmi_check_system(bad_lid_status) && !acpi_lid_open())
|
|
--- a/drivers/gpu/drm/i915/intel_overlay.c
|
|
+++ b/drivers/gpu/drm/i915/intel_overlay.c
|
|
@@ -172,7 +172,7 @@ struct overlay_registers {
|
|
#define OFC_UPDATE 0x1
|
|
|
|
#define OVERLAY_NONPHYSICAL(dev) (IS_G33(dev) || IS_I965G(dev))
|
|
-#define OVERLAY_EXISTS(dev) (!IS_G4X(dev) && !IS_IRONLAKE(dev))
|
|
+#define OVERLAY_EXISTS(dev) (!IS_G4X(dev) && !IS_IRONLAKE(dev) && !IS_GEN6(dev))
|
|
|
|
|
|
static struct overlay_registers *intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
|
|
--- a/drivers/net/sfc/efx.c
|
|
+++ b/drivers/net/sfc/efx.c
|
|
@@ -1862,6 +1862,7 @@ out:
|
|
}
|
|
|
|
if (disabled) {
|
|
+ dev_close(efx->net_dev);
|
|
EFX_ERR(efx, "has been disabled\n");
|
|
efx->state = STATE_DISABLED;
|
|
} else {
|
|
@@ -1885,8 +1886,7 @@ static void efx_reset_work(struct work_struct *data)
|
|
}
|
|
|
|
rtnl_lock();
|
|
- if (efx_reset(efx, efx->reset_pending))
|
|
- dev_close(efx->net_dev);
|
|
+ (void)efx_reset(efx, efx->reset_pending);
|
|
rtnl_unlock();
|
|
}
|
|
|
|
--- a/drivers/net/sfc/falcon.c
|
|
+++ b/drivers/net/sfc/falcon.c
|
|
@@ -1317,7 +1317,9 @@ static int falcon_probe_nvconfig(struct efx_nic *efx)
|
|
|
|
EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad);
|
|
|
|
- falcon_probe_board(efx, board_rev);
|
|
+ rc = falcon_probe_board(efx, board_rev);
|
|
+ if (rc)
|
|
+ goto fail2;
|
|
|
|
kfree(nvconfig);
|
|
return 0;
|
|
--- a/drivers/net/sfc/falcon_boards.c
|
|
+++ b/drivers/net/sfc/falcon_boards.c
|
|
@@ -728,15 +728,7 @@ static const struct falcon_board_type board_types[] = {
|
|
},
|
|
};
|
|
|
|
-static const struct falcon_board_type falcon_dummy_board = {
|
|
- .init = efx_port_dummy_op_int,
|
|
- .init_phy = efx_port_dummy_op_void,
|
|
- .fini = efx_port_dummy_op_void,
|
|
- .set_id_led = efx_port_dummy_op_set_id_led,
|
|
- .monitor = efx_port_dummy_op_int,
|
|
-};
|
|
-
|
|
-void falcon_probe_board(struct efx_nic *efx, u16 revision_info)
|
|
+int falcon_probe_board(struct efx_nic *efx, u16 revision_info)
|
|
{
|
|
struct falcon_board *board = falcon_board(efx);
|
|
u8 type_id = FALCON_BOARD_TYPE(revision_info);
|
|
@@ -754,8 +746,9 @@ void falcon_probe_board(struct efx_nic *efx, u16 revision_info)
|
|
(efx->pci_dev->subsystem_vendor == EFX_VENDID_SFC)
|
|
? board->type->ref_model : board->type->gen_type,
|
|
'A' + board->major, board->minor);
|
|
+ return 0;
|
|
} else {
|
|
EFX_ERR(efx, "unknown board type %d\n", type_id);
|
|
- board->type = &falcon_dummy_board;
|
|
+ return -ENODEV;
|
|
}
|
|
}
|
|
--- a/drivers/net/sfc/nic.h
|
|
+++ b/drivers/net/sfc/nic.h
|
|
@@ -156,7 +156,7 @@ extern struct efx_nic_type siena_a0_nic_type;
|
|
**************************************************************************
|
|
*/
|
|
|
|
-extern void falcon_probe_board(struct efx_nic *efx, u16 revision_info);
|
|
+extern int falcon_probe_board(struct efx_nic *efx, u16 revision_info);
|
|
|
|
/* TX data path */
|
|
extern int efx_nic_probe_tx(struct efx_tx_queue *tx_queue);
|
|
--- a/drivers/net/sfc/siena.c
|
|
+++ b/drivers/net/sfc/siena.c
|
|
@@ -454,8 +454,17 @@ static int siena_try_update_nic_stats(struct efx_nic *efx)
|
|
|
|
static void siena_update_nic_stats(struct efx_nic *efx)
|
|
{
|
|
- while (siena_try_update_nic_stats(efx) == -EAGAIN)
|
|
- cpu_relax();
|
|
+ int retry;
|
|
+
|
|
+ /* If we're unlucky enough to read statistics wduring the DMA, wait
|
|
+ * up to 10ms for it to finish (typically takes <500us) */
|
|
+ for (retry = 0; retry < 100; ++retry) {
|
|
+ if (siena_try_update_nic_stats(efx) == 0)
|
|
+ return;
|
|
+ udelay(100);
|
|
+ }
|
|
+
|
|
+ /* Use the old values instead */
|
|
}
|
|
|
|
static void siena_start_nic_stats(struct efx_nic *efx)
|