58 lines
2.5 KiB
Diff
58 lines
2.5 KiB
Diff
From 4fdcfb8a09d75fbabf4454a60001224b89245c82 Mon Sep 17 00:00:00 2001
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From: Xiang Chen <chenxiang66@hisilicon.com>
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Date: Mon, 24 Sep 2018 23:06:34 +0800
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Subject: [PATCH 07/31] scsi: hisi_sas: Update v3 hw AIP_LIMIT and
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CFG_AGING_TIME register values
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Origin: https://git.kernel.org/linus/3bccfba8312762becfb05b35d698ba8cffd440f2
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Update registers as follows:
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- Default value of AIP timer is 1ms, and it is easy for some expanders to
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cause IO error. Change the value to max value 65ms to avoid IO error for
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those expanders.
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- A CQ completion will be reported by HW when 4 CQs have occurred or the
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aging timer expires, whichever happens first. Sor serial IO scenario, it
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will still wait 8us for every IO before it is reported. So in the
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situation, the performance is poor. So to improve it, change the limit
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time to the least value.
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For other scenario, it does little affect to the performance.
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Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
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Signed-off-by: John Garry <john.garry@huawei.com>
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Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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---
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drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 3 +++
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1 file changed, 3 insertions(+)
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diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
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index a0fc2d5de787..c3e0be90e19f 100644
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--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
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+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
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@@ -127,6 +127,7 @@
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#define PHY_CTRL_RESET_OFF 0
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#define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
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#define SL_CFG (PORT_BASE + 0x84)
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+#define AIP_LIMIT (PORT_BASE + 0x90)
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#define SL_CONTROL (PORT_BASE + 0x94)
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#define SL_CONTROL_NOTIFY_EN_OFF 0
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#define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
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@@ -431,6 +432,7 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
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(u32)((1ULL << hisi_hba->queue_count) - 1));
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hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
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hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
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+ hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
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hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
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hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
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hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
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@@ -495,6 +497,7 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
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hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32);
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/* used for 12G negotiate */
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hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
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+ hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff);
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}
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for (i = 0; i < hisi_hba->queue_count; i++) {
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--
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2.20.1
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