216 lines
6.1 KiB
Diff
216 lines
6.1 KiB
Diff
From: Andi Kleen <ak@linux.intel.com>
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Date: Thu, 26 Jan 2012 00:09:06 +0100
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Subject: crypto: Add support for x86 cpuid auto loading for x86 crypto
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drivers
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commit 3bd391f056df61e928de1680ff4a3e7e07e5b399 upstream.
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Add support for auto-loading of crypto drivers based on cpuid features.
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This enables auto-loading of the VIA and Intel specific drivers
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for AES, hashing and CRCs.
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Requires the earlier infrastructure patch to add x86 modinfo.
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I kept it all in a single patch for now.
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I dropped the printks when the driver cpuid doesn't match (imho
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drivers never should print anything in such a case)
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One drawback is that udev doesn't know if the drivers are used or not,
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so they will be unconditionally loaded at boot up. That's better
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than not loading them at all, like it often happens.
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Cc: Dave Jones <davej@redhat.com>
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Cc: Kay Sievers <kay.sievers@vrfy.org>
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Cc: Jen Axboe <axboe@kernel.dk>
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Cc: Herbert Xu <herbert@gondor.apana.org.au>
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Cc: Huang Ying <ying.huang@intel.com>
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Signed-off-by: Andi Kleen <ak@linux.intel.com>
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Signed-off-by: Thomas Renninger <trenn@suse.de>
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Acked-by: H. Peter Anvin <hpa@zytor.com>
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Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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---
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arch/x86/crypto/aesni-intel_glue.c | 12 +++++++++---
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arch/x86/crypto/crc32c-intel.c | 11 ++++++++---
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arch/x86/crypto/ghash-clmulni-intel_glue.c | 12 ++++++++----
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drivers/crypto/padlock-aes.c | 9 ++++++++-
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drivers/crypto/padlock-sha.c | 16 ++++++++--------
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5 files changed, 41 insertions(+), 19 deletions(-)
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diff --git a/arch/x86/crypto/aesni-intel_glue.c b/arch/x86/crypto/aesni-intel_glue.c
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index 545d0ce..b3350bd 100644
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--- a/arch/x86/crypto/aesni-intel_glue.c
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+++ b/arch/x86/crypto/aesni-intel_glue.c
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@@ -28,6 +28,7 @@
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#include <crypto/aes.h>
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#include <crypto/cryptd.h>
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#include <crypto/ctr.h>
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+#include <asm/cpu_device_id.h>
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#include <asm/i387.h>
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#include <asm/aes.h>
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#include <crypto/scatterwalk.h>
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@@ -1253,14 +1254,19 @@ static struct crypto_alg __rfc4106_alg = {
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};
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#endif
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+
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+static const struct x86_cpu_id aesni_cpu_id[] = {
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+ X86_FEATURE_MATCH(X86_FEATURE_AES),
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+ {}
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+};
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+MODULE_DEVICE_TABLE(x86cpu, aesni_cpu_id);
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+
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static int __init aesni_init(void)
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{
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int err;
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- if (!cpu_has_aes) {
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- printk(KERN_INFO "Intel AES-NI instructions are not detected.\n");
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+ if (!x86_match_cpu(aesni_cpu_id))
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return -ENODEV;
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- }
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if ((err = crypto_fpu_init()))
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goto fpu_err;
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diff --git a/arch/x86/crypto/crc32c-intel.c b/arch/x86/crypto/crc32c-intel.c
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index b9d0026..493f959 100644
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--- a/arch/x86/crypto/crc32c-intel.c
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+++ b/arch/x86/crypto/crc32c-intel.c
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@@ -31,6 +31,7 @@
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#include <crypto/internal/hash.h>
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#include <asm/cpufeature.h>
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+#include <asm/cpu_device_id.h>
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#define CHKSUM_BLOCK_SIZE 1
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#define CHKSUM_DIGEST_SIZE 4
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@@ -173,13 +174,17 @@ static struct shash_alg alg = {
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}
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};
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+static const struct x86_cpu_id crc32c_cpu_id[] = {
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+ X86_FEATURE_MATCH(X86_FEATURE_XMM4_2),
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+ {}
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+};
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+MODULE_DEVICE_TABLE(x86cpu, crc32c_cpu_id);
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static int __init crc32c_intel_mod_init(void)
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{
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- if (cpu_has_xmm4_2)
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- return crypto_register_shash(&alg);
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- else
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+ if (!x86_match_cpu(crc32c_cpu_id))
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return -ENODEV;
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+ return crypto_register_shash(&alg);
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}
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static void __exit crc32c_intel_mod_fini(void)
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diff --git a/arch/x86/crypto/ghash-clmulni-intel_glue.c b/arch/x86/crypto/ghash-clmulni-intel_glue.c
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index 976aa64..b4bf0a6 100644
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--- a/arch/x86/crypto/ghash-clmulni-intel_glue.c
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+++ b/arch/x86/crypto/ghash-clmulni-intel_glue.c
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@@ -20,6 +20,7 @@
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#include <crypto/gf128mul.h>
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#include <crypto/internal/hash.h>
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#include <asm/i387.h>
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+#include <asm/cpu_device_id.h>
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#define GHASH_BLOCK_SIZE 16
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#define GHASH_DIGEST_SIZE 16
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@@ -294,15 +295,18 @@ static struct ahash_alg ghash_async_alg = {
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},
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};
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+static const struct x86_cpu_id pcmul_cpu_id[] = {
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+ X86_FEATURE_MATCH(X86_FEATURE_PCLMULQDQ), /* Pickle-Mickle-Duck */
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+ {}
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+};
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+MODULE_DEVICE_TABLE(x86cpu, pcmul_cpu_id);
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+
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static int __init ghash_pclmulqdqni_mod_init(void)
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{
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int err;
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- if (!cpu_has_pclmulqdq) {
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- printk(KERN_INFO "Intel PCLMULQDQ-NI instructions are not"
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- " detected.\n");
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+ if (!x86_match_cpu(pcmul_cpu_id))
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return -ENODEV;
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- }
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err = crypto_register_shash(&ghash_alg);
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if (err)
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diff --git a/drivers/crypto/padlock-aes.c b/drivers/crypto/padlock-aes.c
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index 29b9469..37b2e94 100644
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--- a/drivers/crypto/padlock-aes.c
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+++ b/drivers/crypto/padlock-aes.c
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@@ -19,6 +19,7 @@
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#include <linux/percpu.h>
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#include <linux/smp.h>
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#include <linux/slab.h>
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+#include <asm/cpu_device_id.h>
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#include <asm/byteorder.h>
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#include <asm/processor.h>
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#include <asm/i387.h>
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@@ -503,12 +504,18 @@ static struct crypto_alg cbc_aes_alg = {
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}
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};
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+static struct x86_cpu_id padlock_cpu_id[] = {
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+ X86_FEATURE_MATCH(X86_FEATURE_XCRYPT),
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+ {}
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+};
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+MODULE_DEVICE_TABLE(x86cpu, padlock_cpu_id);
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+
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static int __init padlock_init(void)
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{
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int ret;
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struct cpuinfo_x86 *c = &cpu_data(0);
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- if (!cpu_has_xcrypt)
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+ if (!x86_match_cpu(padlock_cpu_id))
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return -ENODEV;
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if (!cpu_has_xcrypt_enabled) {
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diff --git a/drivers/crypto/padlock-sha.c b/drivers/crypto/padlock-sha.c
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index 06bdb4b..9266c0e 100644
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--- a/drivers/crypto/padlock-sha.c
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+++ b/drivers/crypto/padlock-sha.c
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@@ -22,6 +22,7 @@
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/scatterlist.h>
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+#include <asm/cpu_device_id.h>
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#include <asm/i387.h>
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struct padlock_sha_desc {
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@@ -526,6 +527,12 @@ static struct shash_alg sha256_alg_nano = {
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}
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};
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+static struct x86_cpu_id padlock_sha_ids[] = {
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+ X86_FEATURE_MATCH(X86_FEATURE_PHE),
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+ {}
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+};
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+MODULE_DEVICE_TABLE(x86cpu, padlock_sha_ids);
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+
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static int __init padlock_init(void)
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{
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int rc = -ENODEV;
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@@ -533,15 +540,8 @@ static int __init padlock_init(void)
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struct shash_alg *sha1;
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struct shash_alg *sha256;
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- if (!cpu_has_phe) {
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- printk(KERN_NOTICE PFX "VIA PadLock Hash Engine not detected.\n");
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- return -ENODEV;
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- }
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-
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- if (!cpu_has_phe_enabled) {
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- printk(KERN_NOTICE PFX "VIA PadLock detected, but not enabled. Hmm, strange...\n");
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+ if (!x86_match_cpu(padlock_sha_ids) || !cpu_has_phe_enabled)
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return -ENODEV;
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- }
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/* Register the newly added algorithm module if on *
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* VIA Nano processor, or else just do as before */
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