489 lines
15 KiB
Diff
489 lines
15 KiB
Diff
From 1386a9166d814e8e5e8668ada3c3e00f997349aa Mon Sep 17 00:00:00 2001
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Message-Id: <1386a9166d814e8e5e8668ada3c3e00f997349aa.1599166690.git.zanussi@kernel.org>
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In-Reply-To: <56457dc415803c8abc5acb513ada877a79596f05.1599166690.git.zanussi@kernel.org>
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References: <56457dc415803c8abc5acb513ada877a79596f05.1599166690.git.zanussi@kernel.org>
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From: Alexandre Belloni <alexandre.belloni@bootlin.com>
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Date: Thu, 13 Sep 2018 13:30:19 +0200
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Subject: [PATCH 002/333] clocksource/drivers: Add a new driver for the Atmel
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ARM TC blocks
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Origin: https://www.kernel.org/pub/linux/kernel/projects/rt/4.19/older/patches-4.19.142-rt63.tar.xz
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Add a driver for the Atmel Timer Counter Blocks. This driver provides a
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clocksource and two clockevent devices.
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One of the clockevent device is linked to the clocksource counter and so it
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will run at the same frequency. This will be used when there is only on TCB
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channel available for timers.
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The other clockevent device runs on a separate TCB channel when available.
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This driver uses regmap and syscon to be able to probe early in the boot
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and avoid having to switch on the TCB clocksource later. Using regmap also
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means that unused TCB channels may be used by other drivers (PWM for
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example). read/writel are still used to access channel specific registers
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to avoid the performance impact of regmap (mainly locking).
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Tested-by: Alexander Dahl <ada@thorsis.com>
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Tested-by: Andras Szemzo <szemzo.andras@gmail.com>
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Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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---
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drivers/clocksource/Kconfig | 8 +
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drivers/clocksource/Makefile | 3 +-
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drivers/clocksource/timer-atmel-tcb.c | 410 ++++++++++++++++++++++++++
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3 files changed, 420 insertions(+), 1 deletion(-)
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create mode 100644 drivers/clocksource/timer-atmel-tcb.c
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diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
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index 4d37f018d846..0ab22e7037f4 100644
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--- a/drivers/clocksource/Kconfig
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+++ b/drivers/clocksource/Kconfig
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@@ -415,6 +415,14 @@ config ATMEL_ST
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help
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Support for the Atmel ST timer.
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+config ATMEL_ARM_TCB_CLKSRC
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+ bool "Microchip ARM TC Block" if COMPILE_TEST
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+ select REGMAP_MMIO
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+ depends on GENERIC_CLOCKEVENTS
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+ help
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+ This enables build of clocksource and clockevent driver for
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+ the integrated Timer Counter Blocks in Microchip ARM SoCs.
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+
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config CLKSRC_EXYNOS_MCT
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bool "Exynos multi core timer driver" if COMPILE_TEST
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depends on ARM || ARM64
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diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
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index db51b2427e8a..0df9384a1230 100644
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--- a/drivers/clocksource/Makefile
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+++ b/drivers/clocksource/Makefile
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@@ -3,7 +3,8 @@ obj-$(CONFIG_TIMER_OF) += timer-of.o
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obj-$(CONFIG_TIMER_PROBE) += timer-probe.o
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obj-$(CONFIG_ATMEL_PIT) += timer-atmel-pit.o
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obj-$(CONFIG_ATMEL_ST) += timer-atmel-st.o
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-obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o
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+obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o
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+obj-$(CONFIG_ATMEL_ARM_TCB_CLKSRC) += timer-atmel-tcb.o
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obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
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obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
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obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += cs5535-clockevt.o
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diff --git a/drivers/clocksource/timer-atmel-tcb.c b/drivers/clocksource/timer-atmel-tcb.c
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new file mode 100644
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index 000000000000..21fbe430f91b
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--- /dev/null
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+++ b/drivers/clocksource/timer-atmel-tcb.c
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@@ -0,0 +1,410 @@
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+// SPDX-License-Identifier: GPL-2.0
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+#include <linux/clk.h>
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+#include <linux/clockchips.h>
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+#include <linux/clocksource.h>
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+#include <linux/interrupt.h>
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+#include <linux/kernel.h>
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+#include <linux/mfd/syscon.h>
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+#include <linux/of_address.h>
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+#include <linux/of_irq.h>
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+#include <linux/regmap.h>
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+#include <linux/sched_clock.h>
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+#include <soc/at91/atmel_tcb.h>
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+
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+struct atmel_tcb_clksrc {
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+ struct clocksource clksrc;
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+ struct clock_event_device clkevt;
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+ struct regmap *regmap;
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+ void __iomem *base;
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+ struct clk *clk[2];
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+ char name[20];
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+ int channels[2];
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+ int bits;
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+ int irq;
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+ struct {
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+ u32 cmr;
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+ u32 imr;
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+ u32 rc;
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+ bool clken;
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+ } cache[2];
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+ u32 bmr_cache;
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+ bool registered;
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+ bool clk_enabled;
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+};
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+
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+static struct atmel_tcb_clksrc tc;
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+
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+static struct clk *tcb_clk_get(struct device_node *node, int channel)
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+{
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+ struct clk *clk;
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+ char clk_name[] = "t0_clk";
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+
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+ clk_name[1] += channel;
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+ clk = of_clk_get_by_name(node->parent, clk_name);
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+ if (!IS_ERR(clk))
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+ return clk;
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+
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+ return of_clk_get_by_name(node->parent, "t0_clk");
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+}
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+
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+/*
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+ * Clocksource and clockevent using the same channel(s)
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+ */
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+static u64 tc_get_cycles(struct clocksource *cs)
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+{
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+ u32 lower, upper;
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+
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+ do {
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+ upper = readl_relaxed(tc.base + ATMEL_TC_CV(tc.channels[1]));
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+ lower = readl_relaxed(tc.base + ATMEL_TC_CV(tc.channels[0]));
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+ } while (upper != readl_relaxed(tc.base + ATMEL_TC_CV(tc.channels[1])));
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+
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+ return (upper << 16) | lower;
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+}
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+
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+static u64 tc_get_cycles32(struct clocksource *cs)
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+{
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+ return readl_relaxed(tc.base + ATMEL_TC_CV(tc.channels[0]));
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+}
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+
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+static u64 notrace tc_sched_clock_read(void)
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+{
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+ return tc_get_cycles(&tc.clksrc);
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+}
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+
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+static u64 notrace tc_sched_clock_read32(void)
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+{
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+ return tc_get_cycles32(&tc.clksrc);
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+}
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+
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+static int tcb_clkevt_next_event(unsigned long delta,
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+ struct clock_event_device *d)
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+{
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+ u32 old, next, cur;
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+
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+ old = readl(tc.base + ATMEL_TC_CV(tc.channels[0]));
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+ next = old + delta;
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+ writel(next, tc.base + ATMEL_TC_RC(tc.channels[0]));
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+ cur = readl(tc.base + ATMEL_TC_CV(tc.channels[0]));
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+
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+ /* check whether the delta elapsed while setting the register */
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+ if ((next < old && cur < old && cur > next) ||
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+ (next > old && (cur < old || cur > next))) {
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+ /*
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+ * Clear the CPCS bit in the status register to avoid
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+ * generating a spurious interrupt next time a valid
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+ * timer event is configured.
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+ */
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+ old = readl(tc.base + ATMEL_TC_SR(tc.channels[0]));
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+ return -ETIME;
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+ }
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+
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+ writel(ATMEL_TC_CPCS, tc.base + ATMEL_TC_IER(tc.channels[0]));
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+
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+ return 0;
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+}
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+
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+static irqreturn_t tc_clkevt_irq(int irq, void *handle)
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+{
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+ unsigned int sr;
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+
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+ sr = readl(tc.base + ATMEL_TC_SR(tc.channels[0]));
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+ if (sr & ATMEL_TC_CPCS) {
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+ tc.clkevt.event_handler(&tc.clkevt);
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+ return IRQ_HANDLED;
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+ }
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+
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+ return IRQ_NONE;
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+}
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+
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+static int tcb_clkevt_oneshot(struct clock_event_device *dev)
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+{
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+ if (clockevent_state_oneshot(dev))
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+ return 0;
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+
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+ /*
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+ * Because both clockevent devices may share the same IRQ, we don't want
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+ * the less likely one to stay requested
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+ */
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+ return request_irq(tc.irq, tc_clkevt_irq, IRQF_TIMER | IRQF_SHARED,
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+ tc.name, &tc);
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+}
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+
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+static int tcb_clkevt_shutdown(struct clock_event_device *dev)
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+{
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+ writel(0xff, tc.base + ATMEL_TC_IDR(tc.channels[0]));
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+ if (tc.bits == 16)
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+ writel(0xff, tc.base + ATMEL_TC_IDR(tc.channels[1]));
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+
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+ if (!clockevent_state_detached(dev))
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+ free_irq(tc.irq, &tc);
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+
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+ return 0;
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+}
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+
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+static void __init tcb_setup_dual_chan(struct atmel_tcb_clksrc *tc,
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+ int mck_divisor_idx)
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+{
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+ /* first channel: waveform mode, input mclk/8, clock TIOA on overflow */
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+ writel(mck_divisor_idx /* likely divide-by-8 */
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+ | ATMEL_TC_CMR_WAVE
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+ | ATMEL_TC_CMR_WAVESEL_UP /* free-run */
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+ | ATMEL_TC_CMR_ACPA(SET) /* TIOA rises at 0 */
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+ | ATMEL_TC_CMR_ACPC(CLEAR), /* (duty cycle 50%) */
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+ tc->base + ATMEL_TC_CMR(tc->channels[0]));
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+ writel(0x0000, tc->base + ATMEL_TC_RA(tc->channels[0]));
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+ writel(0x8000, tc->base + ATMEL_TC_RC(tc->channels[0]));
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+ writel(0xff, tc->base + ATMEL_TC_IDR(tc->channels[0])); /* no irqs */
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+ writel(ATMEL_TC_CCR_CLKEN, tc->base + ATMEL_TC_CCR(tc->channels[0]));
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+
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+ /* second channel: waveform mode, input TIOA */
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+ writel(ATMEL_TC_CMR_XC(tc->channels[1]) /* input: TIOA */
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+ | ATMEL_TC_CMR_WAVE
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+ | ATMEL_TC_CMR_WAVESEL_UP, /* free-run */
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+ tc->base + ATMEL_TC_CMR(tc->channels[1]));
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+ writel(0xff, tc->base + ATMEL_TC_IDR(tc->channels[1])); /* no irqs */
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+ writel(ATMEL_TC_CCR_CLKEN, tc->base + ATMEL_TC_CCR(tc->channels[1]));
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+
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+ /* chain both channel, we assume the previous channel */
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+ regmap_write(tc->regmap, ATMEL_TC_BMR,
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+ ATMEL_TC_BMR_TCXC(1 + tc->channels[1], tc->channels[1]));
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+ /* then reset all the timers */
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+ regmap_write(tc->regmap, ATMEL_TC_BCR, ATMEL_TC_BCR_SYNC);
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+}
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+
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+static void __init tcb_setup_single_chan(struct atmel_tcb_clksrc *tc,
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+ int mck_divisor_idx)
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+{
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+ /* channel 0: waveform mode, input mclk/8 */
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+ writel(mck_divisor_idx /* likely divide-by-8 */
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+ | ATMEL_TC_CMR_WAVE
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+ | ATMEL_TC_CMR_WAVESEL_UP, /* free-run */
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+ tc->base + ATMEL_TC_CMR(tc->channels[0]));
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+ writel(0xff, tc->base + ATMEL_TC_IDR(tc->channels[0])); /* no irqs */
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+ writel(ATMEL_TC_CCR_CLKEN, tc->base + ATMEL_TC_CCR(tc->channels[0]));
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+
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+ /* then reset all the timers */
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+ regmap_write(tc->regmap, ATMEL_TC_BCR, ATMEL_TC_BCR_SYNC);
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+}
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+
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+static void tc_clksrc_suspend(struct clocksource *cs)
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+{
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+ int i;
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+
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+ for (i = 0; i < 1 + (tc.bits == 16); i++) {
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+ tc.cache[i].cmr = readl(tc.base + ATMEL_TC_CMR(tc.channels[i]));
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+ tc.cache[i].imr = readl(tc.base + ATMEL_TC_IMR(tc.channels[i]));
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+ tc.cache[i].rc = readl(tc.base + ATMEL_TC_RC(tc.channels[i]));
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+ tc.cache[i].clken = !!(readl(tc.base +
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+ ATMEL_TC_SR(tc.channels[i])) &
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+ ATMEL_TC_CLKSTA);
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+ }
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+
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+ if (tc.bits == 16)
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+ regmap_read(tc.regmap, ATMEL_TC_BMR, &tc.bmr_cache);
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+}
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+
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+static void tc_clksrc_resume(struct clocksource *cs)
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+{
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+ int i;
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+
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+ for (i = 0; i < 1 + (tc.bits == 16); i++) {
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+ /* Restore registers for the channel, RA and RB are not used */
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+ writel(tc.cache[i].cmr, tc.base + ATMEL_TC_CMR(tc.channels[i]));
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+ writel(tc.cache[i].rc, tc.base + ATMEL_TC_RC(tc.channels[i]));
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+ writel(0, tc.base + ATMEL_TC_RA(tc.channels[i]));
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+ writel(0, tc.base + ATMEL_TC_RB(tc.channels[i]));
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+ /* Disable all the interrupts */
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+ writel(0xff, tc.base + ATMEL_TC_IDR(tc.channels[i]));
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+ /* Reenable interrupts that were enabled before suspending */
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+ writel(tc.cache[i].imr, tc.base + ATMEL_TC_IER(tc.channels[i]));
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+
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+ /* Start the clock if it was used */
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+ if (tc.cache[i].clken)
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+ writel(ATMEL_TC_CCR_CLKEN, tc.base +
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+ ATMEL_TC_CCR(tc.channels[i]));
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+ }
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+
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+ /* in case of dual channel, chain channels */
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+ if (tc.bits == 16)
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+ regmap_write(tc.regmap, ATMEL_TC_BMR, tc.bmr_cache);
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+ /* Finally, trigger all the channels*/
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+ regmap_write(tc.regmap, ATMEL_TC_BCR, ATMEL_TC_BCR_SYNC);
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+}
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+
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+static int __init tcb_clksrc_register(struct device_node *node,
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+ struct regmap *regmap, void __iomem *base,
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+ int channel, int channel1, int irq,
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+ int bits)
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+{
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+ u32 rate, divided_rate = 0;
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+ int best_divisor_idx = -1;
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+ int i, err = -1;
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+ u64 (*tc_sched_clock)(void);
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+
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+ tc.regmap = regmap;
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+ tc.base = base;
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+ tc.channels[0] = channel;
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+ tc.channels[1] = channel1;
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+ tc.irq = irq;
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+ tc.bits = bits;
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+
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+ tc.clk[0] = tcb_clk_get(node, tc.channels[0]);
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+ if (IS_ERR(tc.clk[0]))
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+ return PTR_ERR(tc.clk[0]);
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+ err = clk_prepare_enable(tc.clk[0]);
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+ if (err) {
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+ pr_debug("can't enable T0 clk\n");
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+ goto err_clk;
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+ }
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+
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+ /* How fast will we be counting? Pick something over 5 MHz. */
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+ rate = (u32)clk_get_rate(tc.clk[0]);
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+ for (i = 0; i < 5; i++) {
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+ unsigned int divisor = atmel_tc_divisors[i];
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+ unsigned int tmp;
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+
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+ if (!divisor)
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+ continue;
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+
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+ tmp = rate / divisor;
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+ pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
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+ if (best_divisor_idx > 0) {
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+ if (tmp < 5 * 1000 * 1000)
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+ continue;
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+ }
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+ divided_rate = tmp;
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+ best_divisor_idx = i;
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+ }
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+
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+ if (tc.bits == 32) {
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+ tc.clksrc.read = tc_get_cycles32;
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+ tcb_setup_single_chan(&tc, best_divisor_idx);
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+ tc_sched_clock = tc_sched_clock_read32;
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+ snprintf(tc.name, sizeof(tc.name), "%s:%d",
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+ kbasename(node->parent->full_name), tc.channels[0]);
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+ } else {
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+ tc.clk[1] = tcb_clk_get(node, tc.channels[1]);
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+ if (IS_ERR(tc.clk[1]))
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+ goto err_disable_t0;
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+
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+ err = clk_prepare_enable(tc.clk[1]);
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+ if (err) {
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+ pr_debug("can't enable T1 clk\n");
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+ goto err_clk1;
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+ }
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+ tc.clksrc.read = tc_get_cycles,
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+ tcb_setup_dual_chan(&tc, best_divisor_idx);
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+ tc_sched_clock = tc_sched_clock_read;
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+ snprintf(tc.name, sizeof(tc.name), "%s:%d,%d",
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+ kbasename(node->parent->full_name), tc.channels[0],
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+ tc.channels[1]);
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+ }
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+
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+ pr_debug("%s at %d.%03d MHz\n", tc.name,
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+ divided_rate / 1000000,
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+ ((divided_rate + 500000) % 1000000) / 1000);
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+
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+ tc.clksrc.name = tc.name;
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+ tc.clksrc.suspend = tc_clksrc_suspend;
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+ tc.clksrc.resume = tc_clksrc_resume;
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+ tc.clksrc.rating = 200;
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+ tc.clksrc.mask = CLOCKSOURCE_MASK(32);
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+ tc.clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
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+
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+ err = clocksource_register_hz(&tc.clksrc, divided_rate);
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+ if (err)
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+ goto err_disable_t1;
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+
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+ sched_clock_register(tc_sched_clock, 32, divided_rate);
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+
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+ tc.registered = true;
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+
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+ /* Set up and register clockevents */
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+ tc.clkevt.name = tc.name;
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+ tc.clkevt.cpumask = cpumask_of(0);
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+ tc.clkevt.set_next_event = tcb_clkevt_next_event;
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+ tc.clkevt.set_state_oneshot = tcb_clkevt_oneshot;
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+ tc.clkevt.set_state_shutdown = tcb_clkevt_shutdown;
|
|
+ tc.clkevt.features = CLOCK_EVT_FEAT_ONESHOT;
|
|
+ tc.clkevt.rating = 125;
|
|
+
|
|
+ clockevents_config_and_register(&tc.clkevt, divided_rate, 1,
|
|
+ BIT(tc.bits) - 1);
|
|
+
|
|
+ return 0;
|
|
+
|
|
+err_disable_t1:
|
|
+ if (tc.bits == 16)
|
|
+ clk_disable_unprepare(tc.clk[1]);
|
|
+
|
|
+err_clk1:
|
|
+ if (tc.bits == 16)
|
|
+ clk_put(tc.clk[1]);
|
|
+
|
|
+err_disable_t0:
|
|
+ clk_disable_unprepare(tc.clk[0]);
|
|
+
|
|
+err_clk:
|
|
+ clk_put(tc.clk[0]);
|
|
+
|
|
+ pr_err("%s: unable to register clocksource/clockevent\n",
|
|
+ tc.clksrc.name);
|
|
+
|
|
+ return err;
|
|
+}
|
|
+
|
|
+static int __init tcb_clksrc_init(struct device_node *node)
|
|
+{
|
|
+ const struct of_device_id *match;
|
|
+ struct regmap *regmap;
|
|
+ void __iomem *tcb_base;
|
|
+ u32 channel;
|
|
+ int irq, err, chan1 = -1;
|
|
+ unsigned bits;
|
|
+
|
|
+ if (tc.registered)
|
|
+ return -ENODEV;
|
|
+
|
|
+ /*
|
|
+ * The regmap has to be used to access registers that are shared
|
|
+ * between channels on the same TCB but we keep direct IO access for
|
|
+ * the counters to avoid the impact on performance
|
|
+ */
|
|
+ regmap = syscon_node_to_regmap(node->parent);
|
|
+ if (IS_ERR(regmap))
|
|
+ return PTR_ERR(regmap);
|
|
+
|
|
+ tcb_base = of_iomap(node->parent, 0);
|
|
+ if (!tcb_base) {
|
|
+ pr_err("%s +%d %s\n", __FILE__, __LINE__, __func__);
|
|
+ return -ENXIO;
|
|
+ }
|
|
+
|
|
+ match = of_match_node(atmel_tcb_dt_ids, node->parent);
|
|
+ bits = (uintptr_t)match->data;
|
|
+
|
|
+ err = of_property_read_u32_index(node, "reg", 0, &channel);
|
|
+ if (err)
|
|
+ return err;
|
|
+
|
|
+ irq = of_irq_get(node->parent, channel);
|
|
+ if (irq < 0) {
|
|
+ irq = of_irq_get(node->parent, 0);
|
|
+ if (irq < 0)
|
|
+ return irq;
|
|
+ }
|
|
+
|
|
+ if (bits == 16) {
|
|
+ of_property_read_u32_index(node, "reg", 1, &chan1);
|
|
+ if (chan1 == -1) {
|
|
+ pr_err("%s: clocksource needs two channels\n",
|
|
+ node->parent->full_name);
|
|
+ return -EINVAL;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ return tcb_clksrc_register(node, regmap, tcb_base, channel, chan1, irq,
|
|
+ bits);
|
|
+}
|
|
+TIMER_OF_DECLARE(atmel_tcb_clksrc, "atmel,tcb-timer", tcb_clksrc_init);
|
|
--
|
|
2.17.1
|
|
|