43 lines
1.9 KiB
Diff
43 lines
1.9 KiB
Diff
upstream commit 45db07382a5c78b0c43b3b0002b63757fb60e873
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Author: John David Anglin <dave.anglin@bell.net>
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Date: Sun Dec 14 10:49:11 2014 -0500
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parisc: fix out-of-register compiler error in ldcw inline assembler function
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The __ldcw macro has a problem when its argument needs to be reloaded from
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memory. The output memory operand and the input register operand both need to
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be reloaded using a register in class R1_REGS when generating 64-bit code.
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This fails because there's only a single register in the class. Instead, use a
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memory clobber. This also makes the __ldcw macro a compiler memory barrier.
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Signed-off-by: John David Anglin <dave.anglin@bell.net>
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Cc: <stable@vger.kernel.org> [3.13+]
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Signed-off-by: Helge Deller <deller@gmx.de>
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diff --git a/arch/parisc/include/asm/ldcw.h b/arch/parisc/include/asm/ldcw.h
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index d2d11b7..8121aa6 100644
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--- a/arch/parisc/include/asm/ldcw.h
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+++ b/arch/parisc/include/asm/ldcw.h
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@@ -33,11 +33,18 @@
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#endif /*!CONFIG_PA20*/
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-/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*. */
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+/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*.
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+ We don't explicitly expose that "*a" may be written as reload
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+ fails to find a register in class R1_REGS when "a" needs to be
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+ reloaded when generating 64-bit PIC code. Instead, we clobber
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+ memory to indicate to the compiler that the assembly code reads
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+ or writes to items other than those listed in the input and output
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+ operands. This may pessimize the code somewhat but __ldcw is
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+ usually used within code blocks surrounded by memory barriors. */
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#define __ldcw(a) ({ \
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unsigned __ret; \
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- __asm__ __volatile__(__LDCW " 0(%2),%0" \
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- : "=r" (__ret), "+m" (*(a)) : "r" (a)); \
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+ __asm__ __volatile__(__LDCW " 0(%1),%0" \
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+ : "=r" (__ret) : "r" (a) : "memory"); \
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__ret; \
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})
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