158 lines
5.7 KiB
Diff
158 lines
5.7 KiB
Diff
From caeef6247aa6f5250d14108b33cef5458ba6c58e Mon Sep 17 00:00:00 2001
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From: Yunsheng Lin <linyunsheng@huawei.com>
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Date: Tue, 18 Dec 2018 19:37:57 +0800
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Subject: [PATCH 20/31] net: hns3: getting tx and dv buffer size through
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firmware
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Origin: https://git.kernel.org/linus/368686be234daf365ef184a6ee1c4a6c18ede3b1
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This patch adds support of getting tx and dv buffer size through
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firmware, because different version of hardware requires different
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size of tx and dv buffer.
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This patch also add dv_buf_size to tc' private buffer size even if
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pfc is not enable for the tc.
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Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
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Signed-off-by: Peng Li <lipeng321@huawei.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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.../hisilicon/hns3/hns3pf/hclge_cmd.h | 5 ++-
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.../hisilicon/hns3/hns3pf/hclge_main.c | 41 ++++++++++++++-----
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.../hisilicon/hns3/hns3pf/hclge_main.h | 3 ++
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3 files changed, 38 insertions(+), 11 deletions(-)
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Index: linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
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===================================================================
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--- linux.orig/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
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+++ linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
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@@ -365,7 +365,9 @@ struct hclge_pf_res_cmd {
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#define HCLGE_PF_VEC_NUM_M GENMASK(7, 0)
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__le16 pf_intr_vector_number;
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__le16 pf_own_fun_number;
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- __le32 rsv[3];
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+ __le16 tx_buf_size;
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+ __le16 dv_buf_size;
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+ __le32 rsv[2];
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};
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#define HCLGE_CFG_OFFSET_S 0
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@@ -791,6 +793,7 @@ struct hclge_serdes_lb_cmd {
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#define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */
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#define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */
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#define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */
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+#define HCLGE_NON_DCB_ADDITIONAL_BUF 0x200 /* 512 byte */
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#define HCLGE_TYPE_CRQ 0
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#define HCLGE_TYPE_CSQ 1
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Index: linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
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===================================================================
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--- linux.orig/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
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+++ linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
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@@ -931,6 +931,18 @@ static int hclge_query_pf_resource(struc
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hdev->num_tqps = __le16_to_cpu(req->tqp_num);
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hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
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+ if (req->tx_buf_size)
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+ hdev->tx_buf_size =
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+ __le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S;
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+ else
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+ hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
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+
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+ if (req->dv_buf_size)
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+ hdev->dv_buf_size =
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+ __le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S;
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+ else
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+ hdev->dv_buf_size = HCLGE_DEFAULT_DV;
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+
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if (hnae3_dev_roce_supported(hdev)) {
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hdev->roce_base_msix_offset =
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hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
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@@ -1591,9 +1603,10 @@ static bool hclge_is_rx_buf_ok(struct h
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pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
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if (hnae3_dev_dcb_supported(hdev))
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- shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
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+ shared_buf_min = 2 * hdev->mps + hdev->dv_buf_size;
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else
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- shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
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+ shared_buf_min = hdev->mps + HCLGE_NON_DCB_ADDITIONAL_BUF
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+ + hdev->dv_buf_size;
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shared_buf_tc = pfc_enable_num * hdev->mps +
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(tc_num - pfc_enable_num) * hdev->mps / 2 +
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@@ -1606,8 +1619,15 @@ static bool hclge_is_rx_buf_ok(struct h
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shared_buf = rx_all - rx_priv;
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buf_alloc->s_buf.buf_size = shared_buf;
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- buf_alloc->s_buf.self.high = shared_buf;
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- buf_alloc->s_buf.self.low = 2 * hdev->mps;
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+ if (hnae3_dev_dcb_supported(hdev)) {
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+ buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size;
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+ buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
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+ - hdev->mps / 2;
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+ } else {
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+ buf_alloc->s_buf.self.high = hdev->mps +
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+ HCLGE_NON_DCB_ADDITIONAL_BUF;
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+ buf_alloc->s_buf.self.low = hdev->mps / 2;
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+ }
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for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
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if ((hdev->hw_tc_map & BIT(i)) &&
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@@ -1634,11 +1654,11 @@ static int hclge_tx_buffer_calc(struct h
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for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
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struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
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- if (total_size < HCLGE_DEFAULT_TX_BUF)
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+ if (total_size < hdev->tx_buf_size)
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return -ENOMEM;
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if (hdev->hw_tc_map & BIT(i))
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- priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
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+ priv->tx_buf_size = hdev->tx_buf_size;
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else
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priv->tx_buf_size = 0;
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@@ -1684,11 +1704,12 @@ static int hclge_rx_buffer_calc(struct h
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priv->wl.low = aligned_mps;
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priv->wl.high = priv->wl.low + aligned_mps;
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priv->buf_size = priv->wl.high +
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- HCLGE_DEFAULT_DV;
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+ hdev->dv_buf_size;
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} else {
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priv->wl.low = 0;
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priv->wl.high = 2 * aligned_mps;
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- priv->buf_size = priv->wl.high;
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+ priv->buf_size = priv->wl.high +
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+ hdev->dv_buf_size;
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}
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} else {
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priv->enable = 0;
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@@ -1720,11 +1741,11 @@ static int hclge_rx_buffer_calc(struct h
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if (hdev->tm_info.hw_pfc_map & BIT(i)) {
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priv->wl.low = 128;
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priv->wl.high = priv->wl.low + aligned_mps;
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- priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
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+ priv->buf_size = priv->wl.high + hdev->dv_buf_size;
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} else {
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priv->wl.low = 0;
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priv->wl.high = aligned_mps;
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- priv->buf_size = priv->wl.high;
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+ priv->buf_size = priv->wl.high + hdev->dv_buf_size;
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}
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}
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Index: linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
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===================================================================
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--- linux.orig/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
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+++ linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
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@@ -545,6 +545,9 @@ struct hclge_dev {
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u32 flag;
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u32 pkt_buf_size; /* Total pf buf size for tx/rx */
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+ u32 tx_buf_size; /* Tx buffer size for each TC */
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+ u32 dv_buf_size; /* Dv buffer size for each TC */
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+
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u32 mps; /* Max packet size */
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enum hclge_mta_dmac_sel_type mta_mac_sel_type;
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