301 lines
7.6 KiB
Diff
301 lines
7.6 KiB
Diff
From: Sylver Bruneau <sylver.bruneau@googlemail.com>
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Date: Fri, 23 May 2008 23:02:30 +0000 (+0200)
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Subject: [WATCHDOG] Orion: add hardware watchdog support
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X-Git-Url: http://git.marvell.com/?p=orion.git;a=commitdiff_plain;h=c64ce41834e774179b9769ae53eaede18e029943
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[WATCHDOG] Orion: add hardware watchdog support
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This patch allows the use of the hardware watchdog in the
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Marvell Orion series of ARM SoCs.
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Signed-off-by: Sylver Bruneau <sylver.bruneau@googlemail.com>
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Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
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---
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diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
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index ccb78f6..b0c3212 100644
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--- a/drivers/watchdog/Kconfig
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+++ b/drivers/watchdog/Kconfig
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@@ -217,6 +217,15 @@ config DAVINCI_WATCHDOG
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NOTE: once enabled, this timer cannot be disabled.
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Say N if you are unsure.
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+config ORION5X_WATCHDOG
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+ tristate "Orion5x watchdog"
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+ depends on ARCH_ORION5X
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+ help
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+ Say Y here if to include support for the watchdog timer
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+ in the Orion5x ARM SoCs.
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+ To compile this driver as a module, choose M here: the
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+ module will be called orion5x_wdt.
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+
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# ARM26 Architecture
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# AVR32 Architecture
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diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
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index 25b352b..2af7324 100644
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--- a/drivers/watchdog/Makefile
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+++ b/drivers/watchdog/Makefile
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@@ -39,6 +39,7 @@ obj-$(CONFIG_EP93XX_WATCHDOG) += ep93xx_wdt.o
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obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o
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obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o
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obj-$(CONFIG_DAVINCI_WATCHDOG) += davinci_wdt.o
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+obj-$(CONFIG_ORION5X_WATCHDOG) += orion5x_wdt.o
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# ARM26 Architecture
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diff --git a/drivers/watchdog/orion5x_wdt.c b/drivers/watchdog/orion5x_wdt.c
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new file mode 100644
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index 0000000..5cc1953
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--- /dev/null
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+++ b/drivers/watchdog/orion5x_wdt.c
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@@ -0,0 +1,232 @@
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+/*
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+ * drivers/watchdog/orion5x_wdt.c
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+ *
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+ * Watchdog driver for Orion5x processors
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+ *
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+ * Author: Sylver Bruneau <sylver.bruneau@googlemail.com>
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+ *
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+ * This file is licensed under the terms of the GNU General Public
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+ * License version 2. This program is licensed "as is" without any
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+ * warranty of any kind, whether express or implied.
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/moduleparam.h>
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+#include <linux/types.h>
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+#include <linux/kernel.h>
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+#include <linux/fs.h>
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+#include <linux/miscdevice.h>
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+#include <linux/watchdog.h>
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+#include <linux/init.h>
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+#include <linux/uaccess.h>
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+#include <linux/io.h>
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+
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+#include <asm/hardware.h>
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+
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+/*
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+ * Watchdog timer block registers.
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+ */
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+#define TIMER_CTRL (TIMER_VIRT_BASE + 0x0000)
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+#define WDT_EN 0x0010
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+#define WDT_VAL (TIMER_VIRT_BASE + 0x0024)
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+
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+#define WDT_MAX_DURATION (0xffffffff / ORION5X_TCLK)
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+#define WDT_IN_USE 0
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+#define WDT_OK_TO_CLOSE 1
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+
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+static int nowayout = WATCHDOG_NOWAYOUT;
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+static int heartbeat = WDT_MAX_DURATION; /* (seconds) */
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+static unsigned long wdt_status;
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+
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+static void wdt_enable(void)
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+{
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+ u32 reg;
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+
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+ /* Set watchdog duration */
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+ writel(ORION5X_TCLK * heartbeat, WDT_VAL);
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+
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+ /* Clear watchdog timer interrupt */
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+ reg = readl(BRIDGE_CAUSE);
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+ reg &= ~WDT_INT_REQ;
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+ writel(reg, BRIDGE_CAUSE);
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+
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+ /* Enable watchdog timer */
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+ reg = readl(TIMER_CTRL);
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+ reg |= WDT_EN;
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+ writel(reg, TIMER_CTRL);
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+
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+ /* Enable reset on watchdog */
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+ reg = readl(CPU_RESET_MASK);
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+ reg |= WDT_RESET;
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+ writel(reg, CPU_RESET_MASK);
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+}
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+
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+static void wdt_disable(void)
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+{
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+ u32 reg;
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+
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+ /* Disable reset on watchdog */
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+ reg = readl(CPU_RESET_MASK);
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+ reg &= ~WDT_RESET;
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+ writel(reg, CPU_RESET_MASK);
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+
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+ /* Disable watchdog timer */
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+ reg = readl(TIMER_CTRL);
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+ reg &= ~WDT_EN;
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+ writel(reg, TIMER_CTRL);
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+}
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+
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+static int orion5x_wdt_open(struct inode *inode, struct file *file)
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+{
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+ if (test_and_set_bit(WDT_IN_USE, &wdt_status))
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+ return -EBUSY;
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+ clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
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+ wdt_enable();
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+ return nonseekable_open(inode, file);
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+}
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+
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+static int orion5x_wdt_get_timeleft(int *time_left)
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+{
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+ *time_left = readl(WDT_VAL) / ORION5X_TCLK;
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+ return 0;
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+}
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+
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+static ssize_t orion5x_wdt_write(struct file *file, const char *data,
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+ size_t len, loff_t *ppos)
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+{
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+ if (len) {
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+ if (!nowayout) {
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+ size_t i;
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+
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+ clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
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+ for (i = 0; i != len; i++) {
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+ char c;
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+
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+ if (get_user(c, data + i))
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+ return -EFAULT;
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+ if (c == 'V')
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+ set_bit(WDT_OK_TO_CLOSE, &wdt_status);
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+ }
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+ }
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+ wdt_enable();
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+ }
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+ return len;
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+}
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+
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+static struct watchdog_info ident = {
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+ .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT |
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+ WDIOF_KEEPALIVEPING,
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+ .identity = "Orion5x Watchdog",
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+};
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+
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+
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+static int orion5x_wdt_ioctl(struct inode *inode, struct file *file,
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+ unsigned int cmd, unsigned long arg)
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+{
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+ int ret = -ENOTTY;
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+ int time;
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+
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+ switch (cmd) {
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+ case WDIOC_GETSUPPORT:
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+ ret = copy_to_user((struct watchdog_info *)arg, &ident,
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+ sizeof(ident)) ? -EFAULT : 0;
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+ break;
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+
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+ case WDIOC_GETSTATUS:
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+ ret = put_user(0, (int *)arg);
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+ break;
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+
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+ case WDIOC_SETTIMEOUT:
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+ ret = get_user(time, (int *)arg);
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+ if (ret)
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+ break;
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+
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+ if (time <= 0 || time > WDT_MAX_DURATION) {
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+ ret = -EINVAL;
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+ break;
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+ }
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+ heartbeat = time;
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+ wdt_enable();
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+ /* Fall through */
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+
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+ case WDIOC_GETTIMEOUT:
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+ ret = put_user(heartbeat, (int *)arg);
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+ break;
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+
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+ case WDIOC_KEEPALIVE:
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+ wdt_enable();
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+ ret = 0;
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+ break;
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+
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+ case WDIOC_GETTIMELEFT:
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+ if (orion5x_wdt_get_timeleft(&time)) {
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+ ret = -EINVAL;
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+ break;
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+ }
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+ ret = put_user(time, (int *)arg);
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+ break;
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+ }
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+ return ret;
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+}
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+
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+static int orion5x_wdt_release(struct inode *inode, struct file *file)
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+{
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+ if (test_bit(WDT_OK_TO_CLOSE, &wdt_status))
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+ wdt_disable();
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+ else
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+ printk(KERN_CRIT "WATCHDOG: Device closed unexpectedly - "
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+ "timer will not stop\n");
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+ clear_bit(WDT_IN_USE, &wdt_status);
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+ clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
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+
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+ return 0;
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+}
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+
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+
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+static const struct file_operations orion5x_wdt_fops = {
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+ .owner = THIS_MODULE,
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+ .llseek = no_llseek,
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+ .write = orion5x_wdt_write,
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+ .ioctl = orion5x_wdt_ioctl,
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+ .open = orion5x_wdt_open,
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+ .release = orion5x_wdt_release,
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+};
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+
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+static struct miscdevice orion5x_wdt_miscdev = {
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+ .minor = WATCHDOG_MINOR,
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+ .name = "watchdog",
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+ .fops = &orion5x_wdt_fops,
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+};
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+
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+static int __init orion5x_wdt_init(void)
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+{
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+ int ret;
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+
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+ ret = misc_register(&orion5x_wdt_miscdev);
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+ if (ret == 0)
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+ printk("Orion5x Watchdog Timer: heartbeat %d sec\n",
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+ heartbeat);
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+
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+ return ret;
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+}
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+
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+static void __exit orion5x_wdt_exit(void)
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+{
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+ misc_deregister(&orion5x_wdt_miscdev);
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+}
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+
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+module_init(orion5x_wdt_init);
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+module_exit(orion5x_wdt_exit);
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+
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+MODULE_AUTHOR("Sylver Bruneau <sylver.bruneau@googlemail.com>");
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+MODULE_DESCRIPTION("Orion5x Processor Watchdog");
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+
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+module_param(heartbeat, int, 0);
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+MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds (default is "
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+ __MODULE_STRING(WDT_MAX_DURATION) ")");
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+
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+module_param(nowayout, int, 0);
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+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
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+
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+MODULE_LICENSE("GPL");
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+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
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diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h
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index 10257f5..375da2e 100644
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--- a/include/asm-arm/arch-orion5x/orion5x.h~ 2008-07-26 00:33:55.000000000 +0000
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+++ b/include/asm-arm/arch-orion5x/orion5x.h 2008-07-26 00:33:58.000000000 +0000
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@@ -151,9 +151,11 @@
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#define CPU_CONF ORION5X_BRIDGE_REG(0x100)
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#define CPU_CTRL ORION5X_BRIDGE_REG(0x104)
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#define CPU_RESET_MASK ORION5X_BRIDGE_REG(0x108)
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+#define WDT_RESET 0x0002
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#define CPU_SOFT_RESET ORION5X_BRIDGE_REG(0x10c)
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#define POWER_MNG_CTRL_REG ORION5X_BRIDGE_REG(0x11C)
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#define BRIDGE_CAUSE ORION5X_BRIDGE_REG(0x110)
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+#define WDT_INT_REQ 0x0008
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#define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114)
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#define BRIDGE_INT_TIMER0 0x0002
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#define BRIDGE_INT_TIMER1 0x0004
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