673 lines
19 KiB
Diff
673 lines
19 KiB
Diff
From: Alexandre Belloni <alexandre.belloni@bootlin.com>
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Date: Wed, 18 Apr 2018 12:51:39 +0200
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Subject: [PATCH 2/6] clocksource/drivers: Add a new driver for the Atmel ARM
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TC blocks
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Origin: https://www.kernel.org/pub/linux/kernel/projects/rt/4.16/older/patches-4.16.8-rt3.tar.xz
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Add a driver for the Atmel Timer Counter Blocks. This driver provides a
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clocksource and two clockevent devices.
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One of the clockevent device is linked to the clocksource counter and so it
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will run at the same frequency. This will be used when there is only on TCB
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channel available for timers.
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The other clockevent device runs on a separate TCB channel when available.
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This driver uses regmap and syscon to be able to probe early in the boot
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and avoid having to switch on the TCB clocksource later. Using regmap also
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means that unused TCB channels may be used by other drivers (PWM for
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example). read/writel are still used to access channel specific registers
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to avoid the performance impact of regmap (mainly locking).
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Tested-by: Alexander Dahl <ada@thorsis.com>
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Tested-by: Andras Szemzo <szemzo.andras@gmail.com>
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Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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---
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drivers/clocksource/Kconfig | 8
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drivers/clocksource/Makefile | 3
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drivers/clocksource/timer-atmel-tcb.c | 608 ++++++++++++++++++++++++++++++++++
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3 files changed, 618 insertions(+), 1 deletion(-)
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create mode 100644 drivers/clocksource/timer-atmel-tcb.c
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--- a/drivers/clocksource/Kconfig
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+++ b/drivers/clocksource/Kconfig
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@@ -392,6 +392,14 @@ config ATMEL_ST
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help
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Support for the Atmel ST timer.
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+config ATMEL_ARM_TCB_CLKSRC
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+ bool "Microchip ARM TC Block" if COMPILE_TEST
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+ select REGMAP_MMIO
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+ depends on GENERIC_CLOCKEVENTS
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+ help
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+ This enables build of clocksource and clockevent driver for
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+ the integrated Timer Counter Blocks in Microchip ARM SoCs.
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+
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config CLKSRC_METAG_GENERIC
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def_bool y if METAG
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help
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--- a/drivers/clocksource/Makefile
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+++ b/drivers/clocksource/Makefile
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@@ -3,7 +3,8 @@ obj-$(CONFIG_TIMER_OF) += timer-of.o
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obj-$(CONFIG_TIMER_PROBE) += timer-probe.o
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obj-$(CONFIG_ATMEL_PIT) += timer-atmel-pit.o
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obj-$(CONFIG_ATMEL_ST) += timer-atmel-st.o
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-obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o
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+obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o
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+obj-$(CONFIG_ATMEL_ARM_TCB_CLKSRC) += timer-atmel-tcb.o
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obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
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obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
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obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += cs5535-clockevt.o
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--- /dev/null
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+++ b/drivers/clocksource/timer-atmel-tcb.c
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@@ -0,0 +1,608 @@
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+// SPDX-License-Identifier: GPL-2.0
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+#include <linux/clk.h>
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+#include <linux/clockchips.h>
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+#include <linux/clocksource.h>
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+#include <linux/interrupt.h>
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+#include <linux/kernel.h>
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+#include <linux/mfd/syscon.h>
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+#include <linux/of_address.h>
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+#include <linux/of_irq.h>
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+#include <linux/regmap.h>
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+#include <linux/sched_clock.h>
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+#include <soc/at91/atmel_tcb.h>
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+
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+static struct atmel_tcb_clksrc {
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+ struct clocksource clksrc;
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+ struct clock_event_device clkevt;
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+ struct regmap *regmap;
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+ void __iomem *base;
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+ struct clk *clk[2];
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+ char name[20];
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+ int channels[2];
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+ int bits;
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+ int irq;
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+ struct {
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+ u32 cmr;
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+ u32 imr;
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+ u32 rc;
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+ bool clken;
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+ } cache[2];
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+ u32 bmr_cache;
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+ bool registered;
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+} tc = {
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+ .clksrc = {
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+ .rating = 200,
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+ .mask = CLOCKSOURCE_MASK(32),
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+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
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+ },
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+ .clkevt = {
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+ .features = CLOCK_EVT_FEAT_ONESHOT,
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+ /* Should be lower than at91rm9200's system timer */
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+ .rating = 125,
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+ },
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+};
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+
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+static struct tc_clkevt_device {
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+ struct clock_event_device clkevt;
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+ struct regmap *regmap;
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+ void __iomem *base;
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+ struct clk *slow_clk;
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+ struct clk *clk;
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+ char name[20];
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+ int channel;
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+ int irq;
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+ struct {
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+ u32 cmr;
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+ u32 imr;
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+ u32 rc;
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+ bool clken;
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+ } cache;
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+ bool registered;
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+} tce = {
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+ .clkevt = {
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+ .features = CLOCK_EVT_FEAT_PERIODIC |
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+ CLOCK_EVT_FEAT_ONESHOT,
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+ /*
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+ * Should be lower than at91rm9200's system timer
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+ * but higher than tc.clkevt.rating
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+ */
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+ .rating = 140,
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+ },
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+};
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+
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+/*
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+ * Clockevent device using its own channel
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+ */
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+static int tc_clkevt2_shutdown(struct clock_event_device *d)
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+{
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+ writel(0xff, tce.base + ATMEL_TC_IDR(tce.channel));
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+ writel(ATMEL_TC_CCR_CLKDIS, tce.base + ATMEL_TC_CCR(tce.channel));
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+ if (!clockevent_state_detached(d))
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+ clk_disable(tce.clk);
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+
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+ return 0;
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+}
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+
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+/* For now, we always use the 32K clock ... this optimizes for NO_HZ,
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+ * because using one of the divided clocks would usually mean the
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+ * tick rate can never be less than several dozen Hz (vs 0.5 Hz).
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+ *
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+ * A divided clock could be good for high resolution timers, since
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+ * 30.5 usec resolution can seem "low".
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+ */
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+static int tc_clkevt2_set_oneshot(struct clock_event_device *d)
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+{
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+ if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
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+ tc_clkevt2_shutdown(d);
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+
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+ clk_enable(tce.clk);
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+
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+ /* slow clock, count up to RC, then irq and stop */
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+ writel(ATMEL_TC_CMR_TCLK(4) | ATMEL_TC_CMR_CPCSTOP |
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+ ATMEL_TC_CMR_WAVE | ATMEL_TC_CMR_WAVESEL_UPRC,
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+ tce.base + ATMEL_TC_CMR(tce.channel));
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+ writel(ATMEL_TC_CPCS, tce.base + ATMEL_TC_IER(tce.channel));
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+
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+ return 0;
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+}
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+
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+static int tc_clkevt2_set_periodic(struct clock_event_device *d)
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+{
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+ if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
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+ tc_clkevt2_shutdown(d);
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+
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+ /* By not making the gentime core emulate periodic mode on top
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+ * of oneshot, we get lower overhead and improved accuracy.
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+ */
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+ clk_enable(tce.clk);
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+
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+ /* slow clock, count up to RC, then irq and restart */
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+ writel(ATMEL_TC_CMR_TCLK(4) | ATMEL_TC_CMR_WAVE |
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+ ATMEL_TC_CMR_WAVESEL_UPRC,
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+ tce.base + ATMEL_TC_CMR(tce.channel));
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+ writel((32768 + HZ / 2) / HZ, tce.base + ATMEL_TC_RC(tce.channel));
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+
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+ /* Enable clock and interrupts on RC compare */
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+ writel(ATMEL_TC_CPCS, tce.base + ATMEL_TC_IER(tce.channel));
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+ writel(ATMEL_TC_CCR_CLKEN | ATMEL_TC_CCR_SWTRG,
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+ tce.base + ATMEL_TC_CCR(tce.channel));
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+
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+ return 0;
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+}
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+
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+static int tc_clkevt2_next_event(unsigned long delta,
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+ struct clock_event_device *d)
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+{
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+ writel(delta, tce.base + ATMEL_TC_RC(tce.channel));
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+ writel(ATMEL_TC_CCR_CLKEN | ATMEL_TC_CCR_SWTRG,
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+ tce.base + ATMEL_TC_CCR(tce.channel));
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+
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+ return 0;
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+}
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+
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+static irqreturn_t tc_clkevt2_irq(int irq, void *handle)
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+{
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+ unsigned int sr;
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+
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+ sr = readl(tce.base + ATMEL_TC_SR(tce.channel));
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+ if (sr & ATMEL_TC_CPCS) {
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+ tce.clkevt.event_handler(&tce.clkevt);
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+ return IRQ_HANDLED;
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+ }
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+
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+ return IRQ_NONE;
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+}
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+
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+static void tc_clkevt2_suspend(struct clock_event_device *d)
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+{
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+ tce.cache.cmr = readl(tce.base + ATMEL_TC_CMR(tce.channel));
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+ tce.cache.imr = readl(tce.base + ATMEL_TC_IMR(tce.channel));
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+ tce.cache.rc = readl(tce.base + ATMEL_TC_RC(tce.channel));
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+ tce.cache.clken = !!(readl(tce.base + ATMEL_TC_SR(tce.channel)) &
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+ ATMEL_TC_CLKSTA);
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+}
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+
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+static void tc_clkevt2_resume(struct clock_event_device *d)
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+{
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+ /* Restore registers for the channel, RA and RB are not used */
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+ writel(tce.cache.cmr, tc.base + ATMEL_TC_CMR(tce.channel));
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+ writel(tce.cache.rc, tc.base + ATMEL_TC_RC(tce.channel));
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+ writel(0, tc.base + ATMEL_TC_RA(tce.channel));
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+ writel(0, tc.base + ATMEL_TC_RB(tce.channel));
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+ /* Disable all the interrupts */
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+ writel(0xff, tc.base + ATMEL_TC_IDR(tce.channel));
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+ /* Reenable interrupts that were enabled before suspending */
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+ writel(tce.cache.imr, tc.base + ATMEL_TC_IER(tce.channel));
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+
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+ /* Start the clock if it was used */
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+ if (tce.cache.clken)
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+ writel(ATMEL_TC_CCR_CLKEN | ATMEL_TC_CCR_SWTRG,
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+ tc.base + ATMEL_TC_CCR(tce.channel));
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+}
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+
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+static int __init tc_clkevt_register(struct device_node *node,
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+ struct regmap *regmap, void __iomem *base,
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+ int channel, int irq, int bits)
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+{
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+ int ret;
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+
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+ tce.regmap = regmap;
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+ tce.base = base;
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+ tce.channel = channel;
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+ tce.irq = irq;
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+
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+ tce.slow_clk = of_clk_get_by_name(node->parent, "slow_clk");
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+ if (IS_ERR(tce.slow_clk))
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+ return PTR_ERR(tce.slow_clk);
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+
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+ ret = clk_prepare_enable(tce.slow_clk);
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+ if (ret)
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+ return ret;
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+
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+ tce.clk = tcb_clk_get(node, tce.channel);
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+ if (IS_ERR(tce.clk)) {
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+ ret = PTR_ERR(tce.clk);
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+ goto err_slow;
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+ }
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+
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+ snprintf(tce.name, sizeof(tce.name), "%s:%d",
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+ kbasename(node->parent->full_name), channel);
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+ tce.clkevt.cpumask = cpumask_of(0);
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+ tce.clkevt.name = tce.name;
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+ tce.clkevt.set_next_event = tc_clkevt2_next_event,
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+ tce.clkevt.set_state_shutdown = tc_clkevt2_shutdown,
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+ tce.clkevt.set_state_periodic = tc_clkevt2_set_periodic,
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+ tce.clkevt.set_state_oneshot = tc_clkevt2_set_oneshot,
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+ tce.clkevt.suspend = tc_clkevt2_suspend,
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+ tce.clkevt.resume = tc_clkevt2_resume,
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+
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+ /* try to enable clk to avoid future errors in mode change */
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+ ret = clk_prepare_enable(tce.clk);
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+ if (ret)
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+ goto err_slow;
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+ clk_disable(tce.clk);
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+
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+ clockevents_config_and_register(&tce.clkevt, 32768, 1, BIT(bits) - 1);
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+
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+ ret = request_irq(tce.irq, tc_clkevt2_irq, IRQF_TIMER | IRQF_SHARED,
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+ tce.clkevt.name, &tce);
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+ if (ret)
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+ goto err_clk;
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+
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+ tce.registered = true;
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+
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+ return 0;
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+
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+err_clk:
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+ clk_unprepare(tce.clk);
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+err_slow:
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+ clk_disable_unprepare(tce.slow_clk);
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+
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+ return ret;
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+}
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+
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+/*
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+ * Clocksource and clockevent using the same channel(s)
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+ */
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+static u64 tc_get_cycles(struct clocksource *cs)
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+{
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+ u32 lower, upper;
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+
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+ do {
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+ upper = readl_relaxed(tc.base + ATMEL_TC_CV(tc.channels[1]));
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+ lower = readl_relaxed(tc.base + ATMEL_TC_CV(tc.channels[0]));
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+ } while (upper != readl_relaxed(tc.base + ATMEL_TC_CV(tc.channels[1])));
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+
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+ return (upper << 16) | lower;
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+}
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+
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+static u64 tc_get_cycles32(struct clocksource *cs)
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+{
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+ return readl_relaxed(tc.base + ATMEL_TC_CV(tc.channels[0]));
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+}
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+
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+static u64 notrace tc_sched_clock_read(void)
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+{
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+ return tc_get_cycles(&tc.clksrc);
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+}
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+
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+static u64 notrace tc_sched_clock_read32(void)
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+{
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+ return tc_get_cycles32(&tc.clksrc);
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+}
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+
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+static int tcb_clkevt_next_event(unsigned long delta,
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+ struct clock_event_device *d)
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+{
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+ u32 old, next, cur;
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+
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+
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+ old = readl(tc.base + ATMEL_TC_CV(tc.channels[0]));
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+ next = old + delta;
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+ writel(next, tc.base + ATMEL_TC_RC(tc.channels[0]));
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+ cur = readl(tc.base + ATMEL_TC_CV(tc.channels[0]));
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+
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+ /* check whether the delta elapsed while setting the register */
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+ if ((next < old && cur < old && cur > next) ||
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+ (next > old && (cur < old || cur > next))) {
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+ /*
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+ * Clear the CPCS bit in the status register to avoid
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+ * generating a spurious interrupt next time a valid
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+ * timer event is configured.
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+ */
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+ old = readl(tc.base + ATMEL_TC_SR(tc.channels[0]));
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+ return -ETIME;
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+ }
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+
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+ writel(ATMEL_TC_CPCS, tc.base + ATMEL_TC_IER(tc.channels[0]));
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+
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+ return 0;
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+}
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+
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+static irqreturn_t tc_clkevt_irq(int irq, void *handle)
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+{
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+ unsigned int sr;
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+
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+ sr = readl(tc.base + ATMEL_TC_SR(tc.channels[0]));
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+ if (sr & ATMEL_TC_CPCS) {
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+ tc.clkevt.event_handler(&tc.clkevt);
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+ return IRQ_HANDLED;
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+ }
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+
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+ return IRQ_NONE;
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+}
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+
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+static int tcb_clkevt_oneshot(struct clock_event_device *dev)
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+{
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+ if (clockevent_state_oneshot(dev))
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+ return 0;
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+
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+ /*
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+ * Because both clockevent devices may share the same IRQ, we don't want
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+ * the less likely one to stay requested
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+ */
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+ return request_irq(tc.irq, tc_clkevt_irq, IRQF_TIMER | IRQF_SHARED,
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+ tc.name, &tc);
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+}
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+
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+static int tcb_clkevt_shutdown(struct clock_event_device *dev)
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+{
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+ writel(0xff, tc.base + ATMEL_TC_IDR(tc.channels[0]));
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+ if (tc.bits == 16)
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+ writel(0xff, tc.base + ATMEL_TC_IDR(tc.channels[1]));
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+
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+ if (!clockevent_state_detached(dev))
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+ free_irq(tc.irq, &tc);
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+
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+ return 0;
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+}
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+
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+static void __init tcb_setup_dual_chan(struct atmel_tcb_clksrc *tc,
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+ int mck_divisor_idx)
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+{
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+ /* first channel: waveform mode, input mclk/8, clock TIOA on overflow */
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+ writel(mck_divisor_idx /* likely divide-by-8 */
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+ | ATMEL_TC_CMR_WAVE
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+ | ATMEL_TC_CMR_WAVESEL_UP /* free-run */
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+ | ATMEL_TC_CMR_ACPA(SET) /* TIOA rises at 0 */
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+ | ATMEL_TC_CMR_ACPC(CLEAR), /* (duty cycle 50%) */
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+ tc->base + ATMEL_TC_CMR(tc->channels[0]));
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+ writel(0x0000, tc->base + ATMEL_TC_RA(tc->channels[0]));
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+ writel(0x8000, tc->base + ATMEL_TC_RC(tc->channels[0]));
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+ writel(0xff, tc->base + ATMEL_TC_IDR(tc->channels[0])); /* no irqs */
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+ writel(ATMEL_TC_CCR_CLKEN, tc->base + ATMEL_TC_CCR(tc->channels[0]));
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+
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+ /* second channel: waveform mode, input TIOA */
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+ writel(ATMEL_TC_CMR_XC(tc->channels[1]) /* input: TIOA */
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+ | ATMEL_TC_CMR_WAVE
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+ | ATMEL_TC_CMR_WAVESEL_UP, /* free-run */
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+ tc->base + ATMEL_TC_CMR(tc->channels[1]));
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+ writel(0xff, tc->base + ATMEL_TC_IDR(tc->channels[1])); /* no irqs */
|
|
+ writel(ATMEL_TC_CCR_CLKEN, tc->base + ATMEL_TC_CCR(tc->channels[1]));
|
|
+
|
|
+ /* chain both channel, we assume the previous channel */
|
|
+ regmap_write(tc->regmap, ATMEL_TC_BMR,
|
|
+ ATMEL_TC_BMR_TCXC(1 + tc->channels[1], tc->channels[1]));
|
|
+ /* then reset all the timers */
|
|
+ regmap_write(tc->regmap, ATMEL_TC_BCR, ATMEL_TC_BCR_SYNC);
|
|
+}
|
|
+
|
|
+static void __init tcb_setup_single_chan(struct atmel_tcb_clksrc *tc,
|
|
+ int mck_divisor_idx)
|
|
+{
|
|
+ /* channel 0: waveform mode, input mclk/8 */
|
|
+ writel(mck_divisor_idx /* likely divide-by-8 */
|
|
+ | ATMEL_TC_CMR_WAVE
|
|
+ | ATMEL_TC_CMR_WAVESEL_UP, /* free-run */
|
|
+ tc->base + ATMEL_TC_CMR(tc->channels[0]));
|
|
+ writel(0xff, tc->base + ATMEL_TC_IDR(tc->channels[0])); /* no irqs */
|
|
+ writel(ATMEL_TC_CCR_CLKEN, tc->base + ATMEL_TC_CCR(tc->channels[0]));
|
|
+
|
|
+ /* then reset all the timers */
|
|
+ regmap_write(tc->regmap, ATMEL_TC_BCR, ATMEL_TC_BCR_SYNC);
|
|
+}
|
|
+
|
|
+static void tc_clksrc_suspend(struct clocksource *cs)
|
|
+{
|
|
+ int i;
|
|
+
|
|
+ for (i = 0; i < 1 + (tc.bits == 16); i++) {
|
|
+ tc.cache[i].cmr = readl(tc.base + ATMEL_TC_CMR(tc.channels[i]));
|
|
+ tc.cache[i].imr = readl(tc.base + ATMEL_TC_IMR(tc.channels[i]));
|
|
+ tc.cache[i].rc = readl(tc.base + ATMEL_TC_RC(tc.channels[i]));
|
|
+ tc.cache[i].clken = !!(readl(tc.base +
|
|
+ ATMEL_TC_SR(tc.channels[i])) &
|
|
+ ATMEL_TC_CLKSTA);
|
|
+ }
|
|
+
|
|
+ if (tc.bits == 16)
|
|
+ regmap_read(tc.regmap, ATMEL_TC_BMR, &tc.bmr_cache);
|
|
+}
|
|
+
|
|
+static void tc_clksrc_resume(struct clocksource *cs)
|
|
+{
|
|
+ int i;
|
|
+
|
|
+ for (i = 0; i < 1 + (tc.bits == 16); i++) {
|
|
+ /* Restore registers for the channel, RA and RB are not used */
|
|
+ writel(tc.cache[i].cmr, tc.base + ATMEL_TC_CMR(tc.channels[i]));
|
|
+ writel(tc.cache[i].rc, tc.base + ATMEL_TC_RC(tc.channels[i]));
|
|
+ writel(0, tc.base + ATMEL_TC_RA(tc.channels[i]));
|
|
+ writel(0, tc.base + ATMEL_TC_RB(tc.channels[i]));
|
|
+ /* Disable all the interrupts */
|
|
+ writel(0xff, tc.base + ATMEL_TC_IDR(tc.channels[i]));
|
|
+ /* Reenable interrupts that were enabled before suspending */
|
|
+ writel(tc.cache[i].imr, tc.base + ATMEL_TC_IER(tc.channels[i]));
|
|
+
|
|
+ /* Start the clock if it was used */
|
|
+ if (tc.cache[i].clken)
|
|
+ writel(ATMEL_TC_CCR_CLKEN, tc.base +
|
|
+ ATMEL_TC_CCR(tc.channels[i]));
|
|
+ }
|
|
+
|
|
+ /* in case of dual channel, chain channels */
|
|
+ if (tc.bits == 16)
|
|
+ regmap_write(tc.regmap, ATMEL_TC_BMR, tc.bmr_cache);
|
|
+ /* Finally, trigger all the channels*/
|
|
+ regmap_write(tc.regmap, ATMEL_TC_BCR, ATMEL_TC_BCR_SYNC);
|
|
+}
|
|
+
|
|
+static int __init tcb_clksrc_register(struct device_node *node,
|
|
+ struct regmap *regmap, void __iomem *base,
|
|
+ int channel, int channel1, int irq,
|
|
+ int bits)
|
|
+{
|
|
+ u32 rate, divided_rate = 0;
|
|
+ int best_divisor_idx = -1;
|
|
+ int i, err = -1;
|
|
+ u64 (*tc_sched_clock)(void);
|
|
+
|
|
+ tc.regmap = regmap;
|
|
+ tc.base = base;
|
|
+ tc.channels[0] = channel;
|
|
+ tc.channels[1] = channel1;
|
|
+ tc.irq = irq;
|
|
+ tc.bits = bits;
|
|
+
|
|
+ tc.clk[0] = tcb_clk_get(node, tc.channels[0]);
|
|
+ if (IS_ERR(tc.clk[0]))
|
|
+ return PTR_ERR(tc.clk[0]);
|
|
+ err = clk_prepare_enable(tc.clk[0]);
|
|
+ if (err) {
|
|
+ pr_debug("can't enable T0 clk\n");
|
|
+ goto err_clk;
|
|
+ }
|
|
+
|
|
+ /* How fast will we be counting? Pick something over 5 MHz. */
|
|
+ rate = (u32)clk_get_rate(tc.clk[0]);
|
|
+ for (i = 0; i < 5; i++) {
|
|
+ unsigned int divisor = atmel_tc_divisors[i];
|
|
+ unsigned int tmp;
|
|
+
|
|
+ if (!divisor)
|
|
+ continue;
|
|
+
|
|
+ tmp = rate / divisor;
|
|
+ pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
|
|
+ if (best_divisor_idx > 0) {
|
|
+ if (tmp < 5 * 1000 * 1000)
|
|
+ continue;
|
|
+ }
|
|
+ divided_rate = tmp;
|
|
+ best_divisor_idx = i;
|
|
+ }
|
|
+
|
|
+ if (tc.bits == 32) {
|
|
+ tc.clksrc.read = tc_get_cycles32;
|
|
+ tcb_setup_single_chan(&tc, best_divisor_idx);
|
|
+ tc_sched_clock = tc_sched_clock_read32;
|
|
+ snprintf(tc.name, sizeof(tc.name), "%s:%d",
|
|
+ kbasename(node->parent->full_name), tc.channels[0]);
|
|
+ } else {
|
|
+ tc.clk[1] = tcb_clk_get(node, tc.channels[1]);
|
|
+ if (IS_ERR(tc.clk[1]))
|
|
+ goto err_disable_t0;
|
|
+
|
|
+ err = clk_prepare_enable(tc.clk[1]);
|
|
+ if (err) {
|
|
+ pr_debug("can't enable T1 clk\n");
|
|
+ goto err_clk1;
|
|
+ }
|
|
+ tc.clksrc.read = tc_get_cycles,
|
|
+ tcb_setup_dual_chan(&tc, best_divisor_idx);
|
|
+ tc_sched_clock = tc_sched_clock_read;
|
|
+ snprintf(tc.name, sizeof(tc.name), "%s:%d,%d",
|
|
+ kbasename(node->parent->full_name), tc.channels[0],
|
|
+ tc.channels[1]);
|
|
+ }
|
|
+
|
|
+ pr_debug("%s at %d.%03d MHz\n", tc.name,
|
|
+ divided_rate / 1000000,
|
|
+ ((divided_rate + 500000) % 1000000) / 1000);
|
|
+
|
|
+ tc.clksrc.name = tc.name;
|
|
+ tc.clksrc.suspend = tc_clksrc_suspend;
|
|
+ tc.clksrc.resume = tc_clksrc_resume;
|
|
+
|
|
+ err = clocksource_register_hz(&tc.clksrc, divided_rate);
|
|
+ if (err)
|
|
+ goto err_disable_t1;
|
|
+
|
|
+ sched_clock_register(tc_sched_clock, 32, divided_rate);
|
|
+
|
|
+ tc.registered = true;
|
|
+
|
|
+ /* Set up and register clockevents */
|
|
+ tc.clkevt.name = tc.name;
|
|
+ tc.clkevt.cpumask = cpumask_of(0);
|
|
+ tc.clkevt.set_next_event = tcb_clkevt_next_event;
|
|
+ tc.clkevt.set_state_oneshot = tcb_clkevt_oneshot;
|
|
+ tc.clkevt.set_state_shutdown = tcb_clkevt_shutdown;
|
|
+ clockevents_config_and_register(&tc.clkevt, divided_rate, 1,
|
|
+ BIT(tc.bits) - 1);
|
|
+
|
|
+ return 0;
|
|
+
|
|
+err_disable_t1:
|
|
+ if (tc.bits == 16)
|
|
+ clk_disable_unprepare(tc.clk[1]);
|
|
+
|
|
+err_clk1:
|
|
+ if (tc.bits == 16)
|
|
+ clk_put(tc.clk[1]);
|
|
+
|
|
+err_disable_t0:
|
|
+ clk_disable_unprepare(tc.clk[0]);
|
|
+
|
|
+err_clk:
|
|
+ clk_put(tc.clk[0]);
|
|
+
|
|
+ pr_err("%s: unable to register clocksource/clockevent\n",
|
|
+ tc.clksrc.name);
|
|
+
|
|
+ return err;
|
|
+}
|
|
+
|
|
+static int __init tcb_clksrc_init(struct device_node *node)
|
|
+{
|
|
+ const struct of_device_id *match;
|
|
+ const struct atmel_tcb_info *tcb_info;
|
|
+ struct regmap *regmap;
|
|
+ void __iomem *tcb_base;
|
|
+ u32 channel;
|
|
+ int bits, irq, err, chan1 = -1;
|
|
+
|
|
+ if (tc.registered && tce.registered)
|
|
+ return -ENODEV;
|
|
+
|
|
+ /*
|
|
+ * The regmap has to be used to access registers that are shared
|
|
+ * between channels on the same TCB but we keep direct IO access for
|
|
+ * the counters to avoid the impact on performance
|
|
+ */
|
|
+ regmap = syscon_node_to_regmap(node->parent);
|
|
+ if (IS_ERR(regmap))
|
|
+ return PTR_ERR(regmap);
|
|
+
|
|
+ tcb_base = of_iomap(node->parent, 0);
|
|
+ if (!tcb_base) {
|
|
+ pr_err("%s +%d %s\n", __FILE__, __LINE__, __func__);
|
|
+ return -ENXIO;
|
|
+ }
|
|
+
|
|
+ match = of_match_node(atmel_tcb_dt_ids, node->parent);
|
|
+ tcb_info = match->data;
|
|
+ bits = tcb_info->bits;
|
|
+
|
|
+ err = of_property_read_u32_index(node, "reg", 0, &channel);
|
|
+ if (err)
|
|
+ return err;
|
|
+
|
|
+ irq = tcb_irq_get(node, channel);
|
|
+ if (irq < 0)
|
|
+ return irq;
|
|
+
|
|
+ if (tc.registered)
|
|
+ return tc_clkevt_register(node, regmap, tcb_base, channel, irq,
|
|
+ bits);
|
|
+
|
|
+ if (bits == 16) {
|
|
+ of_property_read_u32_index(node, "reg", 1, &chan1);
|
|
+ if (chan1 == -1) {
|
|
+ if (tce.registered) {
|
|
+ pr_err("%s: clocksource needs two channels\n",
|
|
+ node->parent->full_name);
|
|
+ return -EINVAL;
|
|
+ } else {
|
|
+ return tc_clkevt_register(node, regmap,
|
|
+ tcb_base, channel,
|
|
+ irq, bits);
|
|
+ }
|
|
+ }
|
|
+ }
|
|
+
|
|
+ return tcb_clksrc_register(node, regmap, tcb_base, channel, chan1, irq,
|
|
+ bits);
|
|
+}
|
|
+CLOCKSOURCE_OF_DECLARE(atmel_tcb_clksrc, "atmel,tcb-timer",
|
|
+ tcb_clksrc_init);
|