48 lines
1.3 KiB
Diff
48 lines
1.3 KiB
Diff
From: Linus Torvalds <torvalds@g5.osdl.org>
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Date: Sat, 17 Sep 2005 22:41:04 +0000 (-0700)
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Subject: x86-64/smp: fix random SIGSEGV issues
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X-Git-Url: http://www.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=bc5e8fdfc622b03acf5ac974a1b8b26da6511c99
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x86-64/smp: fix random SIGSEGV issues
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They seem to have been due to AMD errata 63/122; the fix is to disable
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TLB flush filtering in SMP configurations.
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Confirmed to fix the problem by Andrew Walrond <andrew@walrond.org>
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[ Let's see if we'll have a better fix eventually, this is the Q&D
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"let's get this fixed and out there" version ]
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Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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---
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--- a/arch/x86_64/kernel/setup.c
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+++ b/arch/x86_64/kernel/setup.c
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@@ -793,11 +793,26 @@
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#endif
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}
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+#define HWCR 0xc0010015
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+
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static int __init init_amd(struct cpuinfo_x86 *c)
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{
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int r;
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int level;
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+#ifdef CONFIG_SMP
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+ unsigned long value;
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+
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+ // Disable TLB flush filter by setting HWCR.FFDIS:
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+ // bit 6 of msr C001_0015
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+ //
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+ // Errata 63 for SH-B3 steppings
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+ // Errata 122 for all(?) steppings
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+ rdmsrl(HWCR, value);
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+ value |= 1 << 6;
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+ wrmsrl(HWCR, value);
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+#endif
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+
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/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
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3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
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clear_bit(0*32+31, &c->x86_capability);
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