108 lines
3.6 KiB
Diff
108 lines
3.6 KiB
Diff
From: Paolo Bonzini <pbonzini@redhat.com>
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Date: Thu, 12 Jan 2017 15:02:32 +0100
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Subject: KVM: x86: fix emulation of "MOV SS, null selector"
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Origin: https://git.kernel.org/linus/33ab91103b3415e12457e3104f0e4517ce12d0f3
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This is CVE-2017-2583. On Intel this causes a failed vmentry because
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SS's type is neither 3 nor 7 (even though the manual says this check is
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only done for usable SS, and the dmesg splat says that SS is unusable!).
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On AMD it's worse: svm.c is confused and sets CPL to 0 in the vmcb.
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The fix fabricates a data segment descriptor when SS is set to a null
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selector, so that CPL and SS.DPL are set correctly in the VMCS/vmcb.
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Furthermore, only allow setting SS to a NULL selector if SS.RPL < 3;
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this in turn ensures CPL < 3 because RPL must be equal to CPL.
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Thanks to Andy Lutomirski and Willy Tarreau for help in analyzing
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the bug and deciphering the manuals.
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Reported-by: Xiaohan Zhang <zhangxiaohan1@huawei.com>
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Fixes: 79d5b4c3cd809c770d4bf9812635647016c56011
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Cc: stable@nongnu.org
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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---
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arch/x86/kvm/emulate.c | 48 ++++++++++++++++++++++++++++++++++++++----------
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1 file changed, 38 insertions(+), 10 deletions(-)
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diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
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index f36d0fa..cedbba0 100644
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--- a/arch/x86/kvm/emulate.c
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+++ b/arch/x86/kvm/emulate.c
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@@ -1585,7 +1585,6 @@ static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
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&ctxt->exception);
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}
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-/* Does not support long mode */
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static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
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u16 selector, int seg, u8 cpl,
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enum x86_transfer_type transfer,
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@@ -1622,20 +1621,34 @@ static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
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rpl = selector & 3;
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- /* NULL selector is not valid for TR, CS and SS (except for long mode) */
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- if ((seg == VCPU_SREG_CS
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- || (seg == VCPU_SREG_SS
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- && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
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- || seg == VCPU_SREG_TR)
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- && null_selector)
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- goto exception;
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-
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/* TR should be in GDT only */
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if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
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goto exception;
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- if (null_selector) /* for NULL selector skip all following checks */
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+ /* NULL selector is not valid for TR, CS and (except for long mode) SS */
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+ if (null_selector) {
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+ if (seg == VCPU_SREG_CS || seg == VCPU_SREG_TR)
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+ goto exception;
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+
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+ if (seg == VCPU_SREG_SS) {
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+ if (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl)
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+ goto exception;
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+
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+ /*
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+ * ctxt->ops->set_segment expects the CPL to be in
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+ * SS.DPL, so fake an expand-up 32-bit data segment.
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+ */
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+ seg_desc.type = 3;
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+ seg_desc.p = 1;
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+ seg_desc.s = 1;
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+ seg_desc.dpl = cpl;
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+ seg_desc.d = 1;
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+ seg_desc.g = 1;
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+ }
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+
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+ /* Skip all following checks */
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goto load;
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+ }
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ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
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if (ret != X86EMUL_CONTINUE)
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@@ -1751,6 +1764,21 @@ static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
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u16 selector, int seg)
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{
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u8 cpl = ctxt->ops->cpl(ctxt);
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+
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+ /*
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+ * None of MOV, POP and LSS can load a NULL selector in CPL=3, but
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+ * they can load it at CPL<3 (Intel's manual says only LSS can,
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+ * but it's wrong).
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+ *
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+ * However, the Intel manual says that putting IST=1/DPL=3 in
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+ * an interrupt gate will result in SS=3 (the AMD manual instead
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+ * says it doesn't), so allow SS=3 in __load_segment_descriptor
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+ * and only forbid it here.
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+ */
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+ if (seg == VCPU_SREG_SS && selector == 3 &&
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+ ctxt->mode == X86EMUL_MODE_PROT64)
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+ return emulate_exception(ctxt, GP_VECTOR, 0, true);
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+
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return __load_segment_descriptor(ctxt, selector, seg, cpl,
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X86_TRANSFER_NONE, NULL);
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}
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--
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2.1.4
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