603 lines
17 KiB
Diff
603 lines
17 KiB
Diff
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
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index 5ebde67..5401dab 100644
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--- a/drivers/net/bnx2.c
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+++ b/drivers/net/bnx2.c
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@@ -46,12 +46,12 @@
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#include <linux/crc32.h>
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#include <linux/prefetch.h>
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#include <linux/cache.h>
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-#include <linux/zlib.h>
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+#include <linux/firmware.h>
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#include <linux/log2.h>
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#include "bnx2.h"
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-#include "bnx2_fw.h"
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-#include "bnx2_fw2.h"
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+#include "bnx2_cpu.h"
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+#include "bnx2_fw_file.h"
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#define FW_BUF_SIZE 0x10000
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@@ -59,12 +59,20 @@
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#define PFX DRV_MODULE_NAME ": "
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#define DRV_MODULE_VERSION "1.9.3"
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#define DRV_MODULE_RELDATE "March 17, 2009"
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+#define FW_FILE_06 "bnx2-06-4.6.16.fw"
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+#define FW_FILE_09 "bnx2-09-4.6.15.fw"
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#define RUN_AT(x) (jiffies + (x))
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/* Time in jiffies before concluding the transmitter is hung. */
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#define TX_TIMEOUT (5*HZ)
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+#ifdef DEBUG
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+# define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
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+#else
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+# define DPRINTK(fmt, args...)
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+#endif
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+
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static char version[] __devinitdata =
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"Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
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@@ -72,6 +80,8 @@ MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
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MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
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MODULE_LICENSE("GPL");
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MODULE_VERSION(DRV_MODULE_VERSION);
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+MODULE_FIRMWARE(FW_FILE_06);
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+MODULE_FIRMWARE(FW_FILE_09);
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static int disable_msi = 0;
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@@ -3315,32 +3325,32 @@ bnx2_set_rx_mode(struct net_device *dev)
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spin_unlock_bh(&bp->phy_lock);
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}
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-static void
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-load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
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- u32 rv2p_proc)
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+static int
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+load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc, const struct bnx2_fw_file_section *fw_section)
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{
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- int i;
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+ int i, len, offset;
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+ u32 *data;
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u32 val;
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- if (rv2p_proc == RV2P_PROC2 && CHIP_NUM(bp) == CHIP_NUM_5709) {
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- val = le32_to_cpu(rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC]);
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- val &= ~XI_RV2P_PROC2_BD_PAGE_SIZE_MSK;
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- val |= XI_RV2P_PROC2_BD_PAGE_SIZE;
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- rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] = cpu_to_le32(val);
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- }
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+ len = be32_to_cpu(fw_section->len);
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+ offset = be32_to_cpu(fw_section->offset);
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+
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+ if (!len || !offset || len + offset > bp->firmware->size)
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+ return -EINVAL;
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+ DPRINTK("load rv2p firmware with length %u from file offset %u\n", len, offset);
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- for (i = 0; i < rv2p_code_len; i += 8) {
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- REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
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- rv2p_code++;
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- REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code));
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- rv2p_code++;
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+ data = (u32 *)(bp->firmware->data + offset);
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+
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+ for (i = 0; i < (len / 4); i += 2) {
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+ REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(data[i]));
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+ REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(data[i+1]));
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if (rv2p_proc == RV2P_PROC1) {
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- val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
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+ val = (i / 2) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
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REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
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}
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else {
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- val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
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+ val = (i / 2) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
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REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
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}
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}
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@@ -3352,14 +3362,18 @@ load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
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else {
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REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
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}
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+
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+ return 0;
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}
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static int
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-load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, struct fw_info *fw)
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+load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
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+ const struct bnx2_fw_file_entry *fw_entry)
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{
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+ u32 addr, len, file_offset;
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u32 offset;
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u32 val;
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- int rc;
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+ u32 *data;
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/* Halt the CPU. */
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val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
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@@ -3368,64 +3382,87 @@ load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, struct fw_info *fw)
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bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
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/* Load the Text area. */
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- offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
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- if (fw->gz_text) {
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+ addr = be32_to_cpu(fw_entry->text.addr);
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+ len = be32_to_cpu(fw_entry->text.len);
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+ file_offset = be32_to_cpu(fw_entry->text.offset);
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+ data = (u32 *)(bp->firmware->data + file_offset);
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+ DPRINTK("load text section to %x with length %u from file offset %x\n", addr, len, file_offset);
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+
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+ offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
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+ if (len) {
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int j;
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- rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
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- fw->gz_text_len);
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- if (rc < 0)
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- return rc;
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-
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- for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
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- bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j]));
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+ for (j = 0; j < (len / 4); j++, offset += 4) {
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+ bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
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}
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}
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/* Load the Data area. */
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- offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
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- if (fw->data) {
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+ addr = be32_to_cpu(fw_entry->data.addr);
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+ len = be32_to_cpu(fw_entry->data.len);
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+ file_offset = be32_to_cpu(fw_entry->data.offset);
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+ data = (u32 *)(bp->firmware->data + file_offset);
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+ DPRINTK("load data section to %x with length %u from file offset %x\n", addr, len, file_offset);
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+
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+ offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
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+ if (len) {
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int j;
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- for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
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- bnx2_reg_wr_ind(bp, offset, fw->data[j]);
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+ for (j = 0; j < (len / 4); j++, offset += 4) {
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+ bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
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}
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}
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/* Load the SBSS area. */
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- offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
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- if (fw->sbss_len) {
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+ addr = be32_to_cpu(fw_entry->sbss.addr);
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+ len = be32_to_cpu(fw_entry->sbss.len);
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+ DPRINTK("init sbss section on %x with length %u\n", addr, len);
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+
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+ offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
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+ if (len) {
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int j;
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- for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
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+ for (j = 0; j < (len / 4); j++, offset += 4) {
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bnx2_reg_wr_ind(bp, offset, 0);
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}
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}
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/* Load the BSS area. */
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- offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
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- if (fw->bss_len) {
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+ addr = be32_to_cpu(fw_entry->bss.addr);
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+ len = be32_to_cpu(fw_entry->bss.len);
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+ DPRINTK("init bss section on %x with length %u\n", addr, len);
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+
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+ offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
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+ if (len) {
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int j;
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- for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
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+ for (j = 0; j < (len / 4); j++, offset += 4) {
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bnx2_reg_wr_ind(bp, offset, 0);
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}
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}
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/* Load the Read-Only area. */
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- offset = cpu_reg->spad_base +
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- (fw->rodata_addr - cpu_reg->mips_view_base);
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- if (fw->rodata) {
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+ addr = be32_to_cpu(fw_entry->rodata.addr);
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+ len = be32_to_cpu(fw_entry->rodata.len);
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+ file_offset = be32_to_cpu(fw_entry->rodata.offset);
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+ data = (u32 *)(bp->firmware->data + file_offset);
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+ DPRINTK("load rodata section to %x with length %u from file offset %x\n", addr, len, file_offset);
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+
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+ offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
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+ if (len) {
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int j;
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- for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
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- bnx2_reg_wr_ind(bp, offset, fw->rodata[j]);
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+ for (j = 0; j < (len / 4); j++, offset += 4) {
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+ bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
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}
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}
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/* Clear the pre-fetch instruction. */
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bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
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- bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr);
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+
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+ val = be32_to_cpu(fw_entry->start_addr);
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+ DPRINTK("starting cpu on %x\n", val);
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+ bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
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/* Start the CPU. */
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val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
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@@ -3439,95 +3476,39 @@ load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, struct fw_info *fw)
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static int
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bnx2_init_cpus(struct bnx2 *bp)
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{
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- struct fw_info *fw;
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- int rc, rv2p_len;
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- void *text, *rv2p;
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-
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- /* Initialize the RV2P processor. */
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- text = vmalloc(FW_BUF_SIZE);
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- if (!text)
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- return -ENOMEM;
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- if (CHIP_NUM(bp) == CHIP_NUM_5709) {
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- rv2p = bnx2_xi_rv2p_proc1;
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- rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
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- } else {
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- rv2p = bnx2_rv2p_proc1;
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- rv2p_len = sizeof(bnx2_rv2p_proc1);
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- }
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- rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
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- if (rc < 0)
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- goto init_cpu_err;
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-
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- load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
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+ const struct bnx2_fw_file *fw = NULL;
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+ int rc;
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- if (CHIP_NUM(bp) == CHIP_NUM_5709) {
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- rv2p = bnx2_xi_rv2p_proc2;
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- rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
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- } else {
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- rv2p = bnx2_rv2p_proc2;
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- rv2p_len = sizeof(bnx2_rv2p_proc2);
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- }
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- rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
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- if (rc < 0)
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- goto init_cpu_err;
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+ fw = (struct bnx2_fw_file *)bp->firmware->data;
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- load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
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+ /* Initialize the RV2P processor. */
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+ load_rv2p_fw(bp, RV2P_PROC1, &fw->rv2p_proc1);
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+ load_rv2p_fw(bp, RV2P_PROC2, &fw->rv2p_proc2);
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/* Initialize the RX Processor. */
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- if (CHIP_NUM(bp) == CHIP_NUM_5709)
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- fw = &bnx2_rxp_fw_09;
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- else
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- fw = &bnx2_rxp_fw_06;
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-
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- fw->text = text;
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- rc = load_cpu_fw(bp, &cpu_reg_rxp, fw);
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+ rc = load_cpu_fw(bp, &cpu_reg_rxp, &fw->rxp);
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if (rc)
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goto init_cpu_err;
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/* Initialize the TX Processor. */
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- if (CHIP_NUM(bp) == CHIP_NUM_5709)
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- fw = &bnx2_txp_fw_09;
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- else
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- fw = &bnx2_txp_fw_06;
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-
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- fw->text = text;
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- rc = load_cpu_fw(bp, &cpu_reg_txp, fw);
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+ rc = load_cpu_fw(bp, &cpu_reg_txp, &fw->txp);
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if (rc)
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goto init_cpu_err;
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/* Initialize the TX Patch-up Processor. */
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- if (CHIP_NUM(bp) == CHIP_NUM_5709)
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- fw = &bnx2_tpat_fw_09;
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- else
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- fw = &bnx2_tpat_fw_06;
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-
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- fw->text = text;
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- rc = load_cpu_fw(bp, &cpu_reg_tpat, fw);
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+ rc = load_cpu_fw(bp, &cpu_reg_tpat, &fw->tpat);
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if (rc)
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goto init_cpu_err;
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/* Initialize the Completion Processor. */
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- if (CHIP_NUM(bp) == CHIP_NUM_5709)
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- fw = &bnx2_com_fw_09;
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- else
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- fw = &bnx2_com_fw_06;
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-
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- fw->text = text;
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- rc = load_cpu_fw(bp, &cpu_reg_com, fw);
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+ rc = load_cpu_fw(bp, &cpu_reg_com, &fw->com);
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if (rc)
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goto init_cpu_err;
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/* Initialize the Command Processor. */
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- if (CHIP_NUM(bp) == CHIP_NUM_5709)
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- fw = &bnx2_cp_fw_09;
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- else
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- fw = &bnx2_cp_fw_06;
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-
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- fw->text = text;
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- rc = load_cpu_fw(bp, &cpu_reg_cp, fw);
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+ rc = load_cpu_fw(bp, &cpu_reg_cp, &fw->cp);
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init_cpu_err:
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- vfree(text);
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return rc;
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}
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@@ -7656,6 +7638,7 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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struct bnx2 *bp;
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int rc;
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char str[40];
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+ const char *fw_file;
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if (version_printed++ == 0)
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printk(KERN_INFO "%s", version);
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@@ -7697,6 +7680,23 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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pci_set_drvdata(pdev, dev);
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+ if (CHIP_NUM(bp) == CHIP_NUM_5709)
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+ fw_file = FW_FILE_09;
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+ else
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+ fw_file = FW_FILE_06;
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+
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+ rc = request_firmware(&bp->firmware, fw_file, &pdev->dev);
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+ if (rc) {
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+ printk(KERN_ERR PFX "Can't load firmware file %s\n", fw_file);
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+ goto error;
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+ }
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+
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+ if (bp->firmware->size < sizeof(struct bnx2_fw_file)) {
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+ printk(KERN_ERR PFX "Firmware file too small\n");
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+ rc = -EINVAL;
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+ goto error;
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+ }
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+
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memcpy(dev->dev_addr, bp->mac_addr, 6);
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memcpy(dev->perm_addr, bp->mac_addr, 6);
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@@ -7714,13 +7714,7 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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if ((rc = register_netdev(dev))) {
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dev_err(&pdev->dev, "Cannot register net device\n");
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- if (bp->regview)
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- iounmap(bp->regview);
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- pci_release_regions(pdev);
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- pci_disable_device(pdev);
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- pci_set_drvdata(pdev, NULL);
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- free_netdev(dev);
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- return rc;
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+ goto error;
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}
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printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
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@@ -7734,6 +7728,15 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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bp->pdev->irq, print_mac(mac, dev->dev_addr));
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return 0;
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+
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+error:
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+ if (bp->regview)
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+ iounmap(bp->regview);
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+ pci_release_regions(pdev);
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+ pci_disable_device(pdev);
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+ pci_set_drvdata(pdev, NULL);
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+ free_netdev(dev);
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+ return rc;
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}
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static void __devexit
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@@ -7749,6 +7752,8 @@ bnx2_remove_one(struct pci_dev *pdev)
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if (bp->regview)
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iounmap(bp->regview);
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+ release_firmware(bp->firmware);
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+
|
|
free_netdev(dev);
|
|
pci_release_regions(pdev);
|
|
pci_disable_device(pdev);
|
|
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
|
|
index c3c579f..15e837e 100644
|
|
--- a/drivers/net/bnx2.h
|
|
+++ b/drivers/net/bnx2.h
|
|
@@ -6860,6 +6860,7 @@ struct bnx2 {
|
|
|
|
u32 idle_chk_status_idx;
|
|
|
|
+ const struct firmware *firmware;
|
|
};
|
|
|
|
#define REG_RD(bp, offset) \
|
|
@@ -6890,44 +6892,6 @@ struct cpu_reg {
|
|
u32 mips_view_base;
|
|
};
|
|
|
|
-struct fw_info {
|
|
- const u32 ver_major;
|
|
- const u32 ver_minor;
|
|
- const u32 ver_fix;
|
|
-
|
|
- const u32 start_addr;
|
|
-
|
|
- /* Text section. */
|
|
- const u32 text_addr;
|
|
- const u32 text_len;
|
|
- const u32 text_index;
|
|
- __le32 *text;
|
|
- u8 *gz_text;
|
|
- const u32 gz_text_len;
|
|
-
|
|
- /* Data section. */
|
|
- const u32 data_addr;
|
|
- const u32 data_len;
|
|
- const u32 data_index;
|
|
- const u32 *data;
|
|
-
|
|
- /* SBSS section. */
|
|
- const u32 sbss_addr;
|
|
- const u32 sbss_len;
|
|
- const u32 sbss_index;
|
|
-
|
|
- /* BSS section. */
|
|
- const u32 bss_addr;
|
|
- const u32 bss_len;
|
|
- const u32 bss_index;
|
|
-
|
|
- /* Read-only section. */
|
|
- const u32 rodata_addr;
|
|
- const u32 rodata_len;
|
|
- const u32 rodata_index;
|
|
- const u32 *rodata;
|
|
-};
|
|
-
|
|
#define RV2P_PROC1 0
|
|
#define RV2P_PROC2 1
|
|
|
|
diff --git a/drivers/net/bnx2_cpu.h b/drivers/net/bnx2_cpu.h
|
|
new file mode 100644
|
|
index 0000000..940eb91
|
|
--- /dev/null
|
|
+++ b/drivers/net/bnx2_cpu.h
|
|
@@ -0,0 +1,88 @@
|
|
+/* bnx2_fw.h: Broadcom NX2 network driver.
|
|
+ *
|
|
+ * Copyright (c) 2004, 2005, 2006, 2007 Broadcom Corporation
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify
|
|
+ * it under the terms of the GNU General Public License as published by
|
|
+ * the Free Software Foundation.
|
|
+ */
|
|
+
|
|
+/* Initialized Values for the Completion Processor. */
|
|
+static const struct cpu_reg cpu_reg_com = {
|
|
+ .mode = BNX2_COM_CPU_MODE,
|
|
+ .mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT,
|
|
+ .mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA,
|
|
+ .state = BNX2_COM_CPU_STATE,
|
|
+ .state_value_clear = 0xffffff,
|
|
+ .gpr0 = BNX2_COM_CPU_REG_FILE,
|
|
+ .evmask = BNX2_COM_CPU_EVENT_MASK,
|
|
+ .pc = BNX2_COM_CPU_PROGRAM_COUNTER,
|
|
+ .inst = BNX2_COM_CPU_INSTRUCTION,
|
|
+ .bp = BNX2_COM_CPU_HW_BREAKPOINT,
|
|
+ .spad_base = BNX2_COM_SCRATCH,
|
|
+ .mips_view_base = 0x8000000,
|
|
+};
|
|
+
|
|
+/* Initialized Values the Command Processor. */
|
|
+static const struct cpu_reg cpu_reg_cp = {
|
|
+ .mode = BNX2_CP_CPU_MODE,
|
|
+ .mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT,
|
|
+ .mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA,
|
|
+ .state = BNX2_CP_CPU_STATE,
|
|
+ .state_value_clear = 0xffffff,
|
|
+ .gpr0 = BNX2_CP_CPU_REG_FILE,
|
|
+ .evmask = BNX2_CP_CPU_EVENT_MASK,
|
|
+ .pc = BNX2_CP_CPU_PROGRAM_COUNTER,
|
|
+ .inst = BNX2_CP_CPU_INSTRUCTION,
|
|
+ .bp = BNX2_CP_CPU_HW_BREAKPOINT,
|
|
+ .spad_base = BNX2_CP_SCRATCH,
|
|
+ .mips_view_base = 0x8000000,
|
|
+};
|
|
+
|
|
+/* Initialized Values for the RX Processor. */
|
|
+static const struct cpu_reg cpu_reg_rxp = {
|
|
+ .mode = BNX2_RXP_CPU_MODE,
|
|
+ .mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT,
|
|
+ .mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA,
|
|
+ .state = BNX2_RXP_CPU_STATE,
|
|
+ .state_value_clear = 0xffffff,
|
|
+ .gpr0 = BNX2_RXP_CPU_REG_FILE,
|
|
+ .evmask = BNX2_RXP_CPU_EVENT_MASK,
|
|
+ .pc = BNX2_RXP_CPU_PROGRAM_COUNTER,
|
|
+ .inst = BNX2_RXP_CPU_INSTRUCTION,
|
|
+ .bp = BNX2_RXP_CPU_HW_BREAKPOINT,
|
|
+ .spad_base = BNX2_RXP_SCRATCH,
|
|
+ .mips_view_base = 0x8000000,
|
|
+};
|
|
+
|
|
+/* Initialized Values for the TX Patch-up Processor. */
|
|
+static const struct cpu_reg cpu_reg_tpat = {
|
|
+ .mode = BNX2_TPAT_CPU_MODE,
|
|
+ .mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT,
|
|
+ .mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA,
|
|
+ .state = BNX2_TPAT_CPU_STATE,
|
|
+ .state_value_clear = 0xffffff,
|
|
+ .gpr0 = BNX2_TPAT_CPU_REG_FILE,
|
|
+ .evmask = BNX2_TPAT_CPU_EVENT_MASK,
|
|
+ .pc = BNX2_TPAT_CPU_PROGRAM_COUNTER,
|
|
+ .inst = BNX2_TPAT_CPU_INSTRUCTION,
|
|
+ .bp = BNX2_TPAT_CPU_HW_BREAKPOINT,
|
|
+ .spad_base = BNX2_TPAT_SCRATCH,
|
|
+ .mips_view_base = 0x8000000,
|
|
+};
|
|
+
|
|
+/* Initialized Values for the TX Processor. */
|
|
+static const struct cpu_reg cpu_reg_txp = {
|
|
+ .mode = BNX2_TXP_CPU_MODE,
|
|
+ .mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT,
|
|
+ .mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA,
|
|
+ .state = BNX2_TXP_CPU_STATE,
|
|
+ .state_value_clear = 0xffffff,
|
|
+ .gpr0 = BNX2_TXP_CPU_REG_FILE,
|
|
+ .evmask = BNX2_TXP_CPU_EVENT_MASK,
|
|
+ .pc = BNX2_TXP_CPU_PROGRAM_COUNTER,
|
|
+ .inst = BNX2_TXP_CPU_INSTRUCTION,
|
|
+ .bp = BNX2_TXP_CPU_HW_BREAKPOINT,
|
|
+ .spad_base = BNX2_TXP_SCRATCH,
|
|
+ .mips_view_base = 0x8000000,
|
|
+};
|
|
diff --git a/drivers/net/bnx2_fw_file.h b/drivers/net/bnx2_fw_file.h
|
|
new file mode 100644
|
|
index 0000000..06c003c
|
|
--- /dev/null
|
|
+++ b/drivers/net/bnx2_fw_file.h
|
|
@@ -0,0 +1,25 @@
|
|
+struct bnx2_fw_file_section {
|
|
+ uint32_t addr;
|
|
+ uint32_t len;
|
|
+ uint32_t offset;
|
|
+};
|
|
+
|
|
+struct bnx2_fw_file_entry {
|
|
+ uint32_t start_addr;
|
|
+ struct bnx2_fw_file_section text;
|
|
+ struct bnx2_fw_file_section data;
|
|
+ struct bnx2_fw_file_section sbss;
|
|
+ struct bnx2_fw_file_section bss;
|
|
+ struct bnx2_fw_file_section rodata;
|
|
+};
|
|
+
|
|
+struct bnx2_fw_file {
|
|
+ struct bnx2_fw_file_entry com;
|
|
+ struct bnx2_fw_file_entry cp;
|
|
+ struct bnx2_fw_file_entry rxp;
|
|
+ struct bnx2_fw_file_entry tpat;
|
|
+ struct bnx2_fw_file_entry txp;
|
|
+ struct bnx2_fw_file_section rv2p_proc1;
|
|
+ struct bnx2_fw_file_section rv2p_proc2;
|
|
+};
|
|
+
|
|
--- a/drivers/net/Kconfig
|
|
+++ b/drivers/net/Kconfig
|
|
@@ -2327,3 +2327,3 @@ config BNX2
|
|
tristate "Broadcom NetXtremeII support"
|
|
- depends on BROKEN
|
|
+ select FW_LOADER
|
|
depends on PCI
|