718 lines
49 KiB
C
718 lines
49 KiB
C
/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
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File: octvc1_hw_api_swap.h
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Copyright (c) 2016 Octasic Inc. All rights reserved.
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Description:
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program;if not, write to the Free Software Foundation, Inc.,
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51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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Release: OCTSDR Software Development Kit OCTSDR_GSM-02.05.00-B780 (2016/01/14)
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\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
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#ifndef __OCTVC1_HW_API_SWAP_H__
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#define __OCTVC1_HW_API_SWAP_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** INCLUDE FILES *******************************/
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#include "../octvc1_swap_hdrs.h"
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#include "octvc1_hw_api.h"
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/********************************* MACROS **********************************/
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
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#define mOCTVC1_HW_PCB_INFO_SOURCE_ENUM_SWAP( pType ){ \
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*((tOCT_UINT32 *)pType) = mOCT_SWAP32_IF_LE( *((tOCT_UINT32 *)pType) ); }
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#else
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#define mOCTVC1_HW_PCB_INFO_SOURCE_ENUM_SWAP( pType )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
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#define mOCTVC1_HW_PCB_INFO_STATE_ENUM_SWAP( pType ){ \
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*((tOCT_UINT32 *)pType) = mOCT_SWAP32_IF_LE( *((tOCT_UINT32 *)pType) ); }
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#else
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#define mOCTVC1_HW_PCB_INFO_STATE_ENUM_SWAP( pType )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
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#define mOCTVC1_HW_CPU_CORE_MASK_SWAP( pType ){ \
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*((tOCT_UINT32 *)pType) = mOCT_SWAP32_IF_LE( *((tOCT_UINT32 *)pType) ); }
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#else
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#define mOCTVC1_HW_CPU_CORE_MASK_SWAP( pType )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
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#define mOCTVC1_HW_CPU_CORE_STATUS_ENUM_SWAP( pType ){ \
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*((tOCT_UINT32 *)pType) = mOCT_SWAP32_IF_LE( *((tOCT_UINT32 *)pType) ); }
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#else
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#define mOCTVC1_HW_CPU_CORE_STATUS_ENUM_SWAP( pType )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
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#define mOCTVC1_HW_CPU_CORE_FAILURE_MASK_SWAP( pType ){ \
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*((tOCT_UINT32 *)pType) = mOCT_SWAP32_IF_LE( *((tOCT_UINT32 *)pType) ); }
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#else
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#define mOCTVC1_HW_CPU_CORE_FAILURE_MASK_SWAP( pType )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
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#define mOCTVC1_HW_CPU_CORE_STATS_SWAP( _f_pParms ){ tOCTVC1_HW_CPU_CORE_STATS * pOCTVC1_HW_CPU_CORE_STATS = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_CPU_CORE_STATS)\
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{ mOCTVC1_HW_CPU_CORE_STATUS_ENUM_SWAP( &((tOCTVC1_HW_CPU_CORE_STATS *)pOCTVC1_HW_CPU_CORE_STATS)->ulCoreStatus ); } \
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((tOCTVC1_HW_CPU_CORE_STATS *)pOCTVC1_HW_CPU_CORE_STATS)->ulProgramCounter = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_CPU_CORE_STATS *)pOCTVC1_HW_CPU_CORE_STATS)->ulProgramCounter); \
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{ mOCTVC1_HW_CPU_CORE_FAILURE_MASK_SWAP( &((tOCTVC1_HW_CPU_CORE_STATS *)pOCTVC1_HW_CPU_CORE_STATS)->ulFailureMask ); } \
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((tOCTVC1_HW_CPU_CORE_STATS *)pOCTVC1_HW_CPU_CORE_STATS)->ulAccessViolationAddress = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_CPU_CORE_STATS *)pOCTVC1_HW_CPU_CORE_STATS)->ulAccessViolationAddress); \
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}
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#else
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#define mOCTVC1_HW_CPU_CORE_STATS_SWAP( pOCTVC1_HW_CPU_CORE_STATS )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
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#define mOCTVC1_HW_CPU_CORE_INFO_SWAP( _f_pParms ){ tOCTVC1_HW_CPU_CORE_INFO * pOCTVC1_HW_CPU_CORE_INFO = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_CPU_CORE_INFO)\
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((tOCTVC1_HW_CPU_CORE_INFO *)pOCTVC1_HW_CPU_CORE_INFO)->hProcess = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_CPU_CORE_INFO *)pOCTVC1_HW_CPU_CORE_INFO)->hProcess); \
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((tOCTVC1_HW_CPU_CORE_INFO *)pOCTVC1_HW_CPU_CORE_INFO)->ulPhysicalCoreId = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_CPU_CORE_INFO *)pOCTVC1_HW_CPU_CORE_INFO)->ulPhysicalCoreId); \
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{ mOCTVC1_PROCESS_TYPE_ENUM_SWAP( &((tOCTVC1_HW_CPU_CORE_INFO *)pOCTVC1_HW_CPU_CORE_INFO)->ulProcessImageType ); } \
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}
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#else
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#define mOCTVC1_HW_CPU_CORE_INFO_SWAP( pOCTVC1_HW_CPU_CORE_INFO )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
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#define mOCTVC1_HW_ETH_MODE_ENUM_SWAP( pType ){ \
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*((tOCT_UINT32 *)pType) = mOCT_SWAP32_IF_LE( *((tOCT_UINT32 *)pType) ); }
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#else
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#define mOCTVC1_HW_ETH_MODE_ENUM_SWAP( pType )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
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#define mOCTVC1_HW_ETH_LINK_SPEED_ENUM_SWAP( pType ){ \
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*((tOCT_UINT32 *)pType) = mOCT_SWAP32_IF_LE( *((tOCT_UINT32 *)pType) ); }
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#else
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#define mOCTVC1_HW_ETH_LINK_SPEED_ENUM_SWAP( pType )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
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#define mOCTVC1_HW_ETH_DUPLEX_MODE_ENUM_SWAP( pType ){ \
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*((tOCT_UINT32 *)pType) = mOCT_SWAP32_IF_LE( *((tOCT_UINT32 *)pType) ); }
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#else
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#define mOCTVC1_HW_ETH_DUPLEX_MODE_ENUM_SWAP( pType )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
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#define mOCTVC1_HW_ETH_PORT_CONFIG_SWAP( _f_pParms ){ tOCTVC1_HW_ETH_PORT_CONFIG * pOCTVC1_HW_ETH_PORT_CONFIG = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_ETH_PORT_CONFIG)\
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((tOCTVC1_HW_ETH_PORT_CONFIG *)pOCTVC1_HW_ETH_PORT_CONFIG)->ulPromiscuousModeFlag = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_CONFIG *)pOCTVC1_HW_ETH_PORT_CONFIG)->ulPromiscuousModeFlag); \
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((tOCTVC1_HW_ETH_PORT_CONFIG *)pOCTVC1_HW_ETH_PORT_CONFIG)->ulAcceptMulticastFlag = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_CONFIG *)pOCTVC1_HW_ETH_PORT_CONFIG)->ulAcceptMulticastFlag); \
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((tOCTVC1_HW_ETH_PORT_CONFIG *)pOCTVC1_HW_ETH_PORT_CONFIG)->ulAcceptJumboFrameFlag = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_CONFIG *)pOCTVC1_HW_ETH_PORT_CONFIG)->ulAcceptJumboFrameFlag); \
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((tOCTVC1_HW_ETH_PORT_CONFIG *)pOCTVC1_HW_ETH_PORT_CONFIG)->ulSgmiiAutoNegotationFlag = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_CONFIG *)pOCTVC1_HW_ETH_PORT_CONFIG)->ulSgmiiAutoNegotationFlag); \
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{ mOCTVC1_HW_ETH_LINK_SPEED_ENUM_SWAP( &((tOCTVC1_HW_ETH_PORT_CONFIG *)pOCTVC1_HW_ETH_PORT_CONFIG)->ulLinkSpeed ); } \
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{ mOCTVC1_HW_ETH_DUPLEX_MODE_ENUM_SWAP( &((tOCTVC1_HW_ETH_PORT_CONFIG *)pOCTVC1_HW_ETH_PORT_CONFIG)->ulDuplexMode ); } \
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}
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#else
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#define mOCTVC1_HW_ETH_PORT_CONFIG_SWAP( pOCTVC1_HW_ETH_PORT_CONFIG )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
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#define mOCTVC1_HW_ETH_PORT_TX_ERROR_STATS_SWAP( _f_pParms ){ tOCTVC1_HW_ETH_PORT_TX_ERROR_STATS * pOCTVC1_HW_ETH_PORT_TX_ERROR_STATS = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_ETH_PORT_TX_ERROR_STATS)\
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((tOCTVC1_HW_ETH_PORT_TX_ERROR_STATS *)pOCTVC1_HW_ETH_PORT_TX_ERROR_STATS)->ulTxUnderflowCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_TX_ERROR_STATS *)pOCTVC1_HW_ETH_PORT_TX_ERROR_STATS)->ulTxUnderflowCnt); \
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((tOCTVC1_HW_ETH_PORT_TX_ERROR_STATS *)pOCTVC1_HW_ETH_PORT_TX_ERROR_STATS)->ulTxLateCollisionCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_TX_ERROR_STATS *)pOCTVC1_HW_ETH_PORT_TX_ERROR_STATS)->ulTxLateCollisionCnt); \
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((tOCTVC1_HW_ETH_PORT_TX_ERROR_STATS *)pOCTVC1_HW_ETH_PORT_TX_ERROR_STATS)->ulTxExcessCollisionCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_TX_ERROR_STATS *)pOCTVC1_HW_ETH_PORT_TX_ERROR_STATS)->ulTxExcessCollisionCnt); \
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((tOCTVC1_HW_ETH_PORT_TX_ERROR_STATS *)pOCTVC1_HW_ETH_PORT_TX_ERROR_STATS)->ulTxExcessDeferralCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_TX_ERROR_STATS *)pOCTVC1_HW_ETH_PORT_TX_ERROR_STATS)->ulTxExcessDeferralCnt); \
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}
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#else
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#define mOCTVC1_HW_ETH_PORT_TX_ERROR_STATS_SWAP( pOCTVC1_HW_ETH_PORT_TX_ERROR_STATS )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
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#define mOCTVC1_HW_ETH_PORT_TX_STATS_SWAP( _f_pParms ){ tOCTVC1_HW_ETH_PORT_TX_STATS * pOCTVC1_HW_ETH_PORT_TX_STATS = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_ETH_PORT_TX_STATS)\
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((tOCTVC1_HW_ETH_PORT_TX_STATS *)pOCTVC1_HW_ETH_PORT_TX_STATS)->ulTxFrameCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_TX_STATS *)pOCTVC1_HW_ETH_PORT_TX_STATS)->ulTxFrameCnt); \
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((tOCTVC1_HW_ETH_PORT_TX_STATS *)pOCTVC1_HW_ETH_PORT_TX_STATS)->ulTxByteCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_TX_STATS *)pOCTVC1_HW_ETH_PORT_TX_STATS)->ulTxByteCnt); \
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((tOCTVC1_HW_ETH_PORT_TX_STATS *)pOCTVC1_HW_ETH_PORT_TX_STATS)->ulTxPauseFrameCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_TX_STATS *)pOCTVC1_HW_ETH_PORT_TX_STATS)->ulTxPauseFrameCnt); \
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((tOCTVC1_HW_ETH_PORT_TX_STATS *)pOCTVC1_HW_ETH_PORT_TX_STATS)->ulTxVlanFrameCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_TX_STATS *)pOCTVC1_HW_ETH_PORT_TX_STATS)->ulTxVlanFrameCnt); \
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((tOCTVC1_HW_ETH_PORT_TX_STATS *)pOCTVC1_HW_ETH_PORT_TX_STATS)->ulTxJumboFrameCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_TX_STATS *)pOCTVC1_HW_ETH_PORT_TX_STATS)->ulTxJumboFrameCnt); \
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{ mOCTVC1_HW_ETH_PORT_TX_ERROR_STATS_SWAP( &((tOCTVC1_HW_ETH_PORT_TX_STATS *)pOCTVC1_HW_ETH_PORT_TX_STATS)->TxErrorStat ); } \
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}
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#else
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#define mOCTVC1_HW_ETH_PORT_TX_STATS_SWAP( pOCTVC1_HW_ETH_PORT_TX_STATS )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
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#define mOCTVC1_HW_ETH_PORT_RX_ERROR_STATS_SWAP( _f_pParms ){ tOCTVC1_HW_ETH_PORT_RX_ERROR_STATS * pOCTVC1_HW_ETH_PORT_RX_ERROR_STATS = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_ETH_PORT_RX_ERROR_STATS)\
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((tOCTVC1_HW_ETH_PORT_RX_ERROR_STATS *)pOCTVC1_HW_ETH_PORT_RX_ERROR_STATS)->ulRxCrcErrorCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_RX_ERROR_STATS *)pOCTVC1_HW_ETH_PORT_RX_ERROR_STATS)->ulRxCrcErrorCnt); \
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((tOCTVC1_HW_ETH_PORT_RX_ERROR_STATS *)pOCTVC1_HW_ETH_PORT_RX_ERROR_STATS)->ulRxAlignmentErrorCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_RX_ERROR_STATS *)pOCTVC1_HW_ETH_PORT_RX_ERROR_STATS)->ulRxAlignmentErrorCnt); \
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((tOCTVC1_HW_ETH_PORT_RX_ERROR_STATS *)pOCTVC1_HW_ETH_PORT_RX_ERROR_STATS)->ulRxJabberErrorCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_RX_ERROR_STATS *)pOCTVC1_HW_ETH_PORT_RX_ERROR_STATS)->ulRxJabberErrorCnt); \
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((tOCTVC1_HW_ETH_PORT_RX_ERROR_STATS *)pOCTVC1_HW_ETH_PORT_RX_ERROR_STATS)->ulRxUndersizeCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_RX_ERROR_STATS *)pOCTVC1_HW_ETH_PORT_RX_ERROR_STATS)->ulRxUndersizeCnt); \
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((tOCTVC1_HW_ETH_PORT_RX_ERROR_STATS *)pOCTVC1_HW_ETH_PORT_RX_ERROR_STATS)->ulRxOversizeCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_RX_ERROR_STATS *)pOCTVC1_HW_ETH_PORT_RX_ERROR_STATS)->ulRxOversizeCnt); \
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((tOCTVC1_HW_ETH_PORT_RX_ERROR_STATS *)pOCTVC1_HW_ETH_PORT_RX_ERROR_STATS)->ulRxLengthCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_RX_ERROR_STATS *)pOCTVC1_HW_ETH_PORT_RX_ERROR_STATS)->ulRxLengthCnt); \
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((tOCTVC1_HW_ETH_PORT_RX_ERROR_STATS *)pOCTVC1_HW_ETH_PORT_RX_ERROR_STATS)->ulRxOutOfRangeCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_RX_ERROR_STATS *)pOCTVC1_HW_ETH_PORT_RX_ERROR_STATS)->ulRxOutOfRangeCnt); \
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((tOCTVC1_HW_ETH_PORT_RX_ERROR_STATS *)pOCTVC1_HW_ETH_PORT_RX_ERROR_STATS)->ulRxFifoOverflowCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_RX_ERROR_STATS *)pOCTVC1_HW_ETH_PORT_RX_ERROR_STATS)->ulRxFifoOverflowCnt); \
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((tOCTVC1_HW_ETH_PORT_RX_ERROR_STATS *)pOCTVC1_HW_ETH_PORT_RX_ERROR_STATS)->ulRxWatchdogCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_RX_ERROR_STATS *)pOCTVC1_HW_ETH_PORT_RX_ERROR_STATS)->ulRxWatchdogCnt); \
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}
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#else
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#define mOCTVC1_HW_ETH_PORT_RX_ERROR_STATS_SWAP( pOCTVC1_HW_ETH_PORT_RX_ERROR_STATS )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
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#define mOCTVC1_HW_ETH_PORT_RX_STATS_SWAP( _f_pParms ){ tOCTVC1_HW_ETH_PORT_RX_STATS * pOCTVC1_HW_ETH_PORT_RX_STATS = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_ETH_PORT_RX_STATS)\
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((tOCTVC1_HW_ETH_PORT_RX_STATS *)pOCTVC1_HW_ETH_PORT_RX_STATS)->ulRxFrameCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_RX_STATS *)pOCTVC1_HW_ETH_PORT_RX_STATS)->ulRxFrameCnt); \
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((tOCTVC1_HW_ETH_PORT_RX_STATS *)pOCTVC1_HW_ETH_PORT_RX_STATS)->ulRxByteCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_RX_STATS *)pOCTVC1_HW_ETH_PORT_RX_STATS)->ulRxByteCnt); \
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((tOCTVC1_HW_ETH_PORT_RX_STATS *)pOCTVC1_HW_ETH_PORT_RX_STATS)->ulRxJumboFrameCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_RX_STATS *)pOCTVC1_HW_ETH_PORT_RX_STATS)->ulRxJumboFrameCnt); \
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((tOCTVC1_HW_ETH_PORT_RX_STATS *)pOCTVC1_HW_ETH_PORT_RX_STATS)->ulRxPauseFrameCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_RX_STATS *)pOCTVC1_HW_ETH_PORT_RX_STATS)->ulRxPauseFrameCnt); \
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((tOCTVC1_HW_ETH_PORT_RX_STATS *)pOCTVC1_HW_ETH_PORT_RX_STATS)->ulRxVlanFrameCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_ETH_PORT_RX_STATS *)pOCTVC1_HW_ETH_PORT_RX_STATS)->ulRxVlanFrameCnt); \
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{ mOCTVC1_HW_ETH_PORT_RX_ERROR_STATS_SWAP( &((tOCTVC1_HW_ETH_PORT_RX_STATS *)pOCTVC1_HW_ETH_PORT_RX_STATS)->RxErrorStat ); } \
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}
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#else
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#define mOCTVC1_HW_ETH_PORT_RX_STATS_SWAP( pOCTVC1_HW_ETH_PORT_RX_STATS )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
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#define mOCTVC1_HW_RF_PORT_RX_STATS_SWAP( _f_pParms ){ tOCTVC1_HW_RF_PORT_RX_STATS * pOCTVC1_HW_RF_PORT_RX_STATS = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_RF_PORT_RX_STATS)\
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((tOCTVC1_HW_RF_PORT_RX_STATS *)pOCTVC1_HW_RF_PORT_RX_STATS)->ulRxByteCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_RF_PORT_RX_STATS *)pOCTVC1_HW_RF_PORT_RX_STATS)->ulRxByteCnt); \
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((tOCTVC1_HW_RF_PORT_RX_STATS *)pOCTVC1_HW_RF_PORT_RX_STATS)->ulRxOverflowCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_RF_PORT_RX_STATS *)pOCTVC1_HW_RF_PORT_RX_STATS)->ulRxOverflowCnt); \
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((tOCTVC1_HW_RF_PORT_RX_STATS *)pOCTVC1_HW_RF_PORT_RX_STATS)->ulRxAverageBytePerSecond = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_RF_PORT_RX_STATS *)pOCTVC1_HW_RF_PORT_RX_STATS)->ulRxAverageBytePerSecond); \
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((tOCTVC1_HW_RF_PORT_RX_STATS *)pOCTVC1_HW_RF_PORT_RX_STATS)->ulRxAveragePeriodUs = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_RF_PORT_RX_STATS *)pOCTVC1_HW_RF_PORT_RX_STATS)->ulRxAveragePeriodUs); \
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((tOCTVC1_HW_RF_PORT_RX_STATS *)pOCTVC1_HW_RF_PORT_RX_STATS)->ulFrequencyKhz = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_RF_PORT_RX_STATS *)pOCTVC1_HW_RF_PORT_RX_STATS)->ulFrequencyKhz); \
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}
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#else
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#define mOCTVC1_HW_RF_PORT_RX_STATS_SWAP( pOCTVC1_HW_RF_PORT_RX_STATS )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
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#define mOCTVC1_HW_RF_PORT_TX_STATS_SWAP( _f_pParms ){ tOCTVC1_HW_RF_PORT_TX_STATS * pOCTVC1_HW_RF_PORT_TX_STATS = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_RF_PORT_TX_STATS)\
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((tOCTVC1_HW_RF_PORT_TX_STATS *)pOCTVC1_HW_RF_PORT_TX_STATS)->ulTxByteCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_RF_PORT_TX_STATS *)pOCTVC1_HW_RF_PORT_TX_STATS)->ulTxByteCnt); \
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((tOCTVC1_HW_RF_PORT_TX_STATS *)pOCTVC1_HW_RF_PORT_TX_STATS)->ulTxUnderflowCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_RF_PORT_TX_STATS *)pOCTVC1_HW_RF_PORT_TX_STATS)->ulTxUnderflowCnt); \
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((tOCTVC1_HW_RF_PORT_TX_STATS *)pOCTVC1_HW_RF_PORT_TX_STATS)->ulTxAverageBytePerSecond = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_RF_PORT_TX_STATS *)pOCTVC1_HW_RF_PORT_TX_STATS)->ulTxAverageBytePerSecond); \
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((tOCTVC1_HW_RF_PORT_TX_STATS *)pOCTVC1_HW_RF_PORT_TX_STATS)->ulTxAveragePeriodUs = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_RF_PORT_TX_STATS *)pOCTVC1_HW_RF_PORT_TX_STATS)->ulTxAveragePeriodUs); \
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((tOCTVC1_HW_RF_PORT_TX_STATS *)pOCTVC1_HW_RF_PORT_TX_STATS)->ulFrequencyKhz = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_RF_PORT_TX_STATS *)pOCTVC1_HW_RF_PORT_TX_STATS)->ulFrequencyKhz); \
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}
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|
#else
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|
#define mOCTVC1_HW_RF_PORT_TX_STATS_SWAP( pOCTVC1_HW_RF_PORT_TX_STATS )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
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|
#define mOCTVC1_HW_CLOCK_SYNC_MGR_SOURCE_ENUM_SWAP( pType ){ \
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*((tOCT_UINT32 *)pType) = mOCT_SWAP32_IF_LE( *((tOCT_UINT32 *)pType) ); }
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#else
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#define mOCTVC1_HW_CLOCK_SYNC_MGR_SOURCE_ENUM_SWAP( pType )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
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|
#define mOCTVC1_HW_CLOCK_SYNC_MGR_SOURCE_SELECTION_ENUM_SWAP( pType ){ \
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*((tOCT_UINT32 *)pType) = mOCT_SWAP32_IF_LE( *((tOCT_UINT32 *)pType) ); }
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#else
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|
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#define mOCTVC1_HW_CLOCK_SYNC_MGR_SOURCE_SELECTION_ENUM_SWAP( pType )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_CLOCK_SYNC_MGR_SOURCE_STATE_ENUM_SWAP( pType ){ \
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|
*((tOCT_UINT32 *)pType) = mOCT_SWAP32_IF_LE( *((tOCT_UINT32 *)pType) ); }
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#else
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|
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#define mOCTVC1_HW_CLOCK_SYNC_MGR_SOURCE_STATE_ENUM_SWAP( pType )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_CLOCK_SYNC_MGR_STATE_ENUM_SWAP( pType ){ \
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|
*((tOCT_UINT32 *)pType) = mOCT_SWAP32_IF_LE( *((tOCT_UINT32 *)pType) ); }
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#else
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|
|
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#define mOCTVC1_HW_CLOCK_SYNC_MGR_STATE_ENUM_SWAP( pType )
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|
|
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_PCB_INFO_CMD_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_PCB_INFO_CMD * pOCTVC1_HW_MSG_PCB_INFO_CMD = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_PCB_INFO_CMD)\
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|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_PCB_INFO_CMD *)pOCTVC1_HW_MSG_PCB_INFO_CMD)->Header ); } \
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|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_PCB_INFO_CMD_SWAP( pOCTVC1_HW_MSG_PCB_INFO_CMD )
|
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_PCB_INFO_RSP_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_PCB_INFO_RSP * pOCTVC1_HW_MSG_PCB_INFO_RSP = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_PCB_INFO_RSP)\
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|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_PCB_INFO_RSP *)pOCTVC1_HW_MSG_PCB_INFO_RSP)->Header ); } \
|
|
((tOCTVC1_HW_MSG_PCB_INFO_RSP *)pOCTVC1_HW_MSG_PCB_INFO_RSP)->ulDeviceId = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_PCB_INFO_RSP *)pOCTVC1_HW_MSG_PCB_INFO_RSP)->ulDeviceId); \
|
|
{ mOCTVC1_HW_PCB_INFO_SOURCE_ENUM_SWAP( &((tOCTVC1_HW_MSG_PCB_INFO_RSP *)pOCTVC1_HW_MSG_PCB_INFO_RSP)->ulInfoSource ); } \
|
|
{ mOCTVC1_HW_PCB_INFO_STATE_ENUM_SWAP( &((tOCTVC1_HW_MSG_PCB_INFO_RSP *)pOCTVC1_HW_MSG_PCB_INFO_RSP)->ulInfoState ); } \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_PCB_INFO_RSP_SWAP( pOCTVC1_HW_MSG_PCB_INFO_RSP )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_CPU_CORE_STATS_CMD_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_CPU_CORE_STATS_CMD * pOCTVC1_HW_MSG_CPU_CORE_STATS_CMD = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_CPU_CORE_STATS_CMD)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_CPU_CORE_STATS_CMD *)pOCTVC1_HW_MSG_CPU_CORE_STATS_CMD)->Header ); } \
|
|
((tOCTVC1_HW_MSG_CPU_CORE_STATS_CMD *)pOCTVC1_HW_MSG_CPU_CORE_STATS_CMD)->ulCoreIndex = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_CPU_CORE_STATS_CMD *)pOCTVC1_HW_MSG_CPU_CORE_STATS_CMD)->ulCoreIndex); \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_CPU_CORE_STATS_CMD_SWAP( pOCTVC1_HW_MSG_CPU_CORE_STATS_CMD )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_CPU_CORE_STATS_RSP_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_CPU_CORE_STATS_RSP * pOCTVC1_HW_MSG_CPU_CORE_STATS_RSP = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_CPU_CORE_STATS_RSP)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_CPU_CORE_STATS_RSP *)pOCTVC1_HW_MSG_CPU_CORE_STATS_RSP)->Header ); } \
|
|
{ mOCTVC1_HW_CPU_CORE_STATS_SWAP( &((tOCTVC1_HW_MSG_CPU_CORE_STATS_RSP *)pOCTVC1_HW_MSG_CPU_CORE_STATS_RSP)->CoreStats ); } \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_CPU_CORE_STATS_RSP_SWAP( pOCTVC1_HW_MSG_CPU_CORE_STATS_RSP )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_CPU_CORE_INFO_CMD_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_CPU_CORE_INFO_CMD * pOCTVC1_HW_MSG_CPU_CORE_INFO_CMD = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_CPU_CORE_INFO_CMD)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_CPU_CORE_INFO_CMD *)pOCTVC1_HW_MSG_CPU_CORE_INFO_CMD)->Header ); } \
|
|
((tOCTVC1_HW_MSG_CPU_CORE_INFO_CMD *)pOCTVC1_HW_MSG_CPU_CORE_INFO_CMD)->ulCoreIndex = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_CPU_CORE_INFO_CMD *)pOCTVC1_HW_MSG_CPU_CORE_INFO_CMD)->ulCoreIndex); \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_CPU_CORE_INFO_CMD_SWAP( pOCTVC1_HW_MSG_CPU_CORE_INFO_CMD )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_CPU_CORE_INFO_RSP_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_CPU_CORE_INFO_RSP * pOCTVC1_HW_MSG_CPU_CORE_INFO_RSP = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_CPU_CORE_INFO_RSP)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_CPU_CORE_INFO_RSP *)pOCTVC1_HW_MSG_CPU_CORE_INFO_RSP)->Header ); } \
|
|
{ mOCTVC1_HW_CPU_CORE_INFO_SWAP( &((tOCTVC1_HW_MSG_CPU_CORE_INFO_RSP *)pOCTVC1_HW_MSG_CPU_CORE_INFO_RSP)->CoreInfo ); } \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_CPU_CORE_INFO_RSP_SWAP( pOCTVC1_HW_MSG_CPU_CORE_INFO_RSP )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_CPU_CORE_LIST_CMD_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_CPU_CORE_LIST_CMD * pOCTVC1_HW_MSG_CPU_CORE_LIST_CMD = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_CPU_CORE_LIST_CMD)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_CPU_CORE_LIST_CMD *)pOCTVC1_HW_MSG_CPU_CORE_LIST_CMD)->Header ); } \
|
|
{ mOCTVC1_CURSOR_INDEX_GET_SWAP( &((tOCTVC1_HW_MSG_CPU_CORE_LIST_CMD *)pOCTVC1_HW_MSG_CPU_CORE_LIST_CMD)->IndexGet ); } \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_CPU_CORE_LIST_CMD_SWAP( pOCTVC1_HW_MSG_CPU_CORE_LIST_CMD )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_CPU_CORE_LIST_RSP_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_CPU_CORE_LIST_RSP * pOCTVC1_HW_MSG_CPU_CORE_LIST_RSP = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_CPU_CORE_LIST_RSP)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_CPU_CORE_LIST_RSP *)pOCTVC1_HW_MSG_CPU_CORE_LIST_RSP)->Header ); } \
|
|
{ mOCTVC1_CURSOR_INDEX_GET_SWAP( &((tOCTVC1_HW_MSG_CPU_CORE_LIST_RSP *)pOCTVC1_HW_MSG_CPU_CORE_LIST_RSP)->IndexGet ); } \
|
|
{ mOCTVC1_LIST_INDEX_GET_SWAP( &((tOCTVC1_HW_MSG_CPU_CORE_LIST_RSP *)pOCTVC1_HW_MSG_CPU_CORE_LIST_RSP)->IndexList ); } \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_CPU_CORE_LIST_RSP_SWAP( pOCTVC1_HW_MSG_CPU_CORE_LIST_RSP )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_ETH_PORT_INFO_CMD_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_ETH_PORT_INFO_CMD * pOCTVC1_HW_MSG_ETH_PORT_INFO_CMD = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_ETH_PORT_INFO_CMD)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_ETH_PORT_INFO_CMD *)pOCTVC1_HW_MSG_ETH_PORT_INFO_CMD)->Header ); } \
|
|
((tOCTVC1_HW_MSG_ETH_PORT_INFO_CMD *)pOCTVC1_HW_MSG_ETH_PORT_INFO_CMD)->ulPortIndex = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_ETH_PORT_INFO_CMD *)pOCTVC1_HW_MSG_ETH_PORT_INFO_CMD)->ulPortIndex); \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_ETH_PORT_INFO_CMD_SWAP( pOCTVC1_HW_MSG_ETH_PORT_INFO_CMD )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_ETH_PORT_INFO_RSP_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_ETH_PORT_INFO_RSP * pOCTVC1_HW_MSG_ETH_PORT_INFO_RSP = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_ETH_PORT_INFO_RSP)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_ETH_PORT_INFO_RSP *)pOCTVC1_HW_MSG_ETH_PORT_INFO_RSP)->Header ); } \
|
|
((tOCTVC1_HW_MSG_ETH_PORT_INFO_RSP *)pOCTVC1_HW_MSG_ETH_PORT_INFO_RSP)->ulPortIndex = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_ETH_PORT_INFO_RSP *)pOCTVC1_HW_MSG_ETH_PORT_INFO_RSP)->ulPortIndex); \
|
|
((tOCTVC1_HW_MSG_ETH_PORT_INFO_RSP *)pOCTVC1_HW_MSG_ETH_PORT_INFO_RSP)->ulInterfaceId = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_ETH_PORT_INFO_RSP *)pOCTVC1_HW_MSG_ETH_PORT_INFO_RSP)->ulInterfaceId); \
|
|
{ mOCTVC1_HW_ETH_MODE_ENUM_SWAP( &((tOCTVC1_HW_MSG_ETH_PORT_INFO_RSP *)pOCTVC1_HW_MSG_ETH_PORT_INFO_RSP)->ulMode ); } \
|
|
((tOCTVC1_HW_MSG_ETH_PORT_INFO_RSP *)pOCTVC1_HW_MSG_ETH_PORT_INFO_RSP)->ulTxPktQueuesByteSize = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_ETH_PORT_INFO_RSP *)pOCTVC1_HW_MSG_ETH_PORT_INFO_RSP)->ulTxPktQueuesByteSize); \
|
|
((tOCTVC1_HW_MSG_ETH_PORT_INFO_RSP *)pOCTVC1_HW_MSG_ETH_PORT_INFO_RSP)->ulRxPktQueuesByteSize = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_ETH_PORT_INFO_RSP *)pOCTVC1_HW_MSG_ETH_PORT_INFO_RSP)->ulRxPktQueuesByteSize); \
|
|
((tOCTVC1_HW_MSG_ETH_PORT_INFO_RSP *)pOCTVC1_HW_MSG_ETH_PORT_INFO_RSP)->ulRestrictedApiFlag = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_ETH_PORT_INFO_RSP *)pOCTVC1_HW_MSG_ETH_PORT_INFO_RSP)->ulRestrictedApiFlag); \
|
|
((tOCTVC1_HW_MSG_ETH_PORT_INFO_RSP *)pOCTVC1_HW_MSG_ETH_PORT_INFO_RSP)->ulEnableFlag = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_ETH_PORT_INFO_RSP *)pOCTVC1_HW_MSG_ETH_PORT_INFO_RSP)->ulEnableFlag); \
|
|
{ mOCTVC1_HW_ETH_PORT_CONFIG_SWAP( &((tOCTVC1_HW_MSG_ETH_PORT_INFO_RSP *)pOCTVC1_HW_MSG_ETH_PORT_INFO_RSP)->Config ); } \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_ETH_PORT_INFO_RSP_SWAP( pOCTVC1_HW_MSG_ETH_PORT_INFO_RSP )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_ETH_PORT_LIST_CMD_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_ETH_PORT_LIST_CMD * pOCTVC1_HW_MSG_ETH_PORT_LIST_CMD = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_ETH_PORT_LIST_CMD)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_ETH_PORT_LIST_CMD *)pOCTVC1_HW_MSG_ETH_PORT_LIST_CMD)->Header ); } \
|
|
{ mOCTVC1_CURSOR_INDEX_GET_SWAP( &((tOCTVC1_HW_MSG_ETH_PORT_LIST_CMD *)pOCTVC1_HW_MSG_ETH_PORT_LIST_CMD)->IndexGet ); } \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_ETH_PORT_LIST_CMD_SWAP( pOCTVC1_HW_MSG_ETH_PORT_LIST_CMD )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_ETH_PORT_LIST_RSP_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_ETH_PORT_LIST_RSP * pOCTVC1_HW_MSG_ETH_PORT_LIST_RSP = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_ETH_PORT_LIST_RSP)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_ETH_PORT_LIST_RSP *)pOCTVC1_HW_MSG_ETH_PORT_LIST_RSP)->Header ); } \
|
|
{ mOCTVC1_CURSOR_INDEX_GET_SWAP( &((tOCTVC1_HW_MSG_ETH_PORT_LIST_RSP *)pOCTVC1_HW_MSG_ETH_PORT_LIST_RSP)->IndexGet ); } \
|
|
{ mOCTVC1_LIST_INDEX_GET_SWAP( &((tOCTVC1_HW_MSG_ETH_PORT_LIST_RSP *)pOCTVC1_HW_MSG_ETH_PORT_LIST_RSP)->IndexList ); } \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_ETH_PORT_LIST_RSP_SWAP( pOCTVC1_HW_MSG_ETH_PORT_LIST_RSP )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_ETH_PORT_STATS_CMD_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_ETH_PORT_STATS_CMD * pOCTVC1_HW_MSG_ETH_PORT_STATS_CMD = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_ETH_PORT_STATS_CMD)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_ETH_PORT_STATS_CMD *)pOCTVC1_HW_MSG_ETH_PORT_STATS_CMD)->Header ); } \
|
|
((tOCTVC1_HW_MSG_ETH_PORT_STATS_CMD *)pOCTVC1_HW_MSG_ETH_PORT_STATS_CMD)->ulPortIndex = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_ETH_PORT_STATS_CMD *)pOCTVC1_HW_MSG_ETH_PORT_STATS_CMD)->ulPortIndex); \
|
|
((tOCTVC1_HW_MSG_ETH_PORT_STATS_CMD *)pOCTVC1_HW_MSG_ETH_PORT_STATS_CMD)->ulResetStatsFlag = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_ETH_PORT_STATS_CMD *)pOCTVC1_HW_MSG_ETH_PORT_STATS_CMD)->ulResetStatsFlag); \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_ETH_PORT_STATS_CMD_SWAP( pOCTVC1_HW_MSG_ETH_PORT_STATS_CMD )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_ETH_PORT_STATS_RSP_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_ETH_PORT_STATS_RSP * pOCTVC1_HW_MSG_ETH_PORT_STATS_RSP = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_ETH_PORT_STATS_RSP)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_ETH_PORT_STATS_RSP *)pOCTVC1_HW_MSG_ETH_PORT_STATS_RSP)->Header ); } \
|
|
((tOCTVC1_HW_MSG_ETH_PORT_STATS_RSP *)pOCTVC1_HW_MSG_ETH_PORT_STATS_RSP)->ulPortIndex = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_ETH_PORT_STATS_RSP *)pOCTVC1_HW_MSG_ETH_PORT_STATS_RSP)->ulPortIndex); \
|
|
{ mOCTVC1_HW_ETH_PORT_RX_STATS_SWAP( &((tOCTVC1_HW_MSG_ETH_PORT_STATS_RSP *)pOCTVC1_HW_MSG_ETH_PORT_STATS_RSP)->RxStats ); } \
|
|
{ mOCTVC1_HW_ETH_PORT_TX_STATS_SWAP( &((tOCTVC1_HW_MSG_ETH_PORT_STATS_RSP *)pOCTVC1_HW_MSG_ETH_PORT_STATS_RSP)->TxStats ); } \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_ETH_PORT_STATS_RSP_SWAP( pOCTVC1_HW_MSG_ETH_PORT_STATS_RSP )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_ETH_PORT_MODIFY_CMD_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_ETH_PORT_MODIFY_CMD * pOCTVC1_HW_MSG_ETH_PORT_MODIFY_CMD = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_ETH_PORT_MODIFY_CMD)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_ETH_PORT_MODIFY_CMD *)pOCTVC1_HW_MSG_ETH_PORT_MODIFY_CMD)->Header ); } \
|
|
((tOCTVC1_HW_MSG_ETH_PORT_MODIFY_CMD *)pOCTVC1_HW_MSG_ETH_PORT_MODIFY_CMD)->ulPortIndex = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_ETH_PORT_MODIFY_CMD *)pOCTVC1_HW_MSG_ETH_PORT_MODIFY_CMD)->ulPortIndex); \
|
|
{ mOCTVC1_HW_ETH_PORT_CONFIG_SWAP( &((tOCTVC1_HW_MSG_ETH_PORT_MODIFY_CMD *)pOCTVC1_HW_MSG_ETH_PORT_MODIFY_CMD)->Config ); } \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_ETH_PORT_MODIFY_CMD_SWAP( pOCTVC1_HW_MSG_ETH_PORT_MODIFY_CMD )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_ETH_PORT_MODIFY_RSP_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_ETH_PORT_MODIFY_RSP * pOCTVC1_HW_MSG_ETH_PORT_MODIFY_RSP = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_ETH_PORT_MODIFY_RSP)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_ETH_PORT_MODIFY_RSP *)pOCTVC1_HW_MSG_ETH_PORT_MODIFY_RSP)->Header ); } \
|
|
((tOCTVC1_HW_MSG_ETH_PORT_MODIFY_RSP *)pOCTVC1_HW_MSG_ETH_PORT_MODIFY_RSP)->ulPortIndex = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_ETH_PORT_MODIFY_RSP *)pOCTVC1_HW_MSG_ETH_PORT_MODIFY_RSP)->ulPortIndex); \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_ETH_PORT_MODIFY_RSP_SWAP( pOCTVC1_HW_MSG_ETH_PORT_MODIFY_RSP )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
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|
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|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_RF_PORT_INFO_CMD_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_RF_PORT_INFO_CMD * pOCTVC1_HW_MSG_RF_PORT_INFO_CMD = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_RF_PORT_INFO_CMD)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_RF_PORT_INFO_CMD *)pOCTVC1_HW_MSG_RF_PORT_INFO_CMD)->Header ); } \
|
|
((tOCTVC1_HW_MSG_RF_PORT_INFO_CMD *)pOCTVC1_HW_MSG_RF_PORT_INFO_CMD)->ulPortIndex = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_RF_PORT_INFO_CMD *)pOCTVC1_HW_MSG_RF_PORT_INFO_CMD)->ulPortIndex); \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_RF_PORT_INFO_CMD_SWAP( pOCTVC1_HW_MSG_RF_PORT_INFO_CMD )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_RF_PORT_INFO_RSP_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_RF_PORT_INFO_RSP * pOCTVC1_HW_MSG_RF_PORT_INFO_RSP = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_RF_PORT_INFO_RSP)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_RF_PORT_INFO_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_RSP)->Header ); } \
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|
((tOCTVC1_HW_MSG_RF_PORT_INFO_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_RSP)->ulPortIndex = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_RF_PORT_INFO_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_RSP)->ulPortIndex); \
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|
((tOCTVC1_HW_MSG_RF_PORT_INFO_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_RSP)->ulInService = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_RF_PORT_INFO_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_RSP)->ulInService); \
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|
((tOCTVC1_HW_MSG_RF_PORT_INFO_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_RSP)->hOwner = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_RF_PORT_INFO_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_RSP)->hOwner); \
|
|
((tOCTVC1_HW_MSG_RF_PORT_INFO_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_RSP)->ulPortInterfaceId = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_RF_PORT_INFO_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_RSP)->ulPortInterfaceId); \
|
|
((tOCTVC1_HW_MSG_RF_PORT_INFO_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_RSP)->ulFrequencyMinKhz = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_RF_PORT_INFO_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_RSP)->ulFrequencyMinKhz); \
|
|
((tOCTVC1_HW_MSG_RF_PORT_INFO_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_RSP)->ulFrequencyMaxKhz = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_RF_PORT_INFO_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_RSP)->ulFrequencyMaxKhz); \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_RF_PORT_INFO_RSP_SWAP( pOCTVC1_HW_MSG_RF_PORT_INFO_RSP )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_RF_PORT_STATS_CMD_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_RF_PORT_STATS_CMD * pOCTVC1_HW_MSG_RF_PORT_STATS_CMD = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_RF_PORT_STATS_CMD)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_RF_PORT_STATS_CMD *)pOCTVC1_HW_MSG_RF_PORT_STATS_CMD)->Header ); } \
|
|
((tOCTVC1_HW_MSG_RF_PORT_STATS_CMD *)pOCTVC1_HW_MSG_RF_PORT_STATS_CMD)->ulPortIndex = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_RF_PORT_STATS_CMD *)pOCTVC1_HW_MSG_RF_PORT_STATS_CMD)->ulPortIndex); \
|
|
((tOCTVC1_HW_MSG_RF_PORT_STATS_CMD *)pOCTVC1_HW_MSG_RF_PORT_STATS_CMD)->ulResetStatsFlag = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_RF_PORT_STATS_CMD *)pOCTVC1_HW_MSG_RF_PORT_STATS_CMD)->ulResetStatsFlag); \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_RF_PORT_STATS_CMD_SWAP( pOCTVC1_HW_MSG_RF_PORT_STATS_CMD )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_RF_PORT_STATS_RSP_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_RF_PORT_STATS_RSP * pOCTVC1_HW_MSG_RF_PORT_STATS_RSP = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_RF_PORT_STATS_RSP)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_RF_PORT_STATS_RSP *)pOCTVC1_HW_MSG_RF_PORT_STATS_RSP)->Header ); } \
|
|
((tOCTVC1_HW_MSG_RF_PORT_STATS_RSP *)pOCTVC1_HW_MSG_RF_PORT_STATS_RSP)->ulPortIndex = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_RF_PORT_STATS_RSP *)pOCTVC1_HW_MSG_RF_PORT_STATS_RSP)->ulPortIndex); \
|
|
{ mOCTVC1_RADIO_STANDARD_ENUM_SWAP( &((tOCTVC1_HW_MSG_RF_PORT_STATS_RSP *)pOCTVC1_HW_MSG_RF_PORT_STATS_RSP)->ulRadioStandard ); } \
|
|
{ mOCTVC1_HW_RF_PORT_RX_STATS_SWAP( &((tOCTVC1_HW_MSG_RF_PORT_STATS_RSP *)pOCTVC1_HW_MSG_RF_PORT_STATS_RSP)->RxStats ); } \
|
|
{ mOCTVC1_HW_RF_PORT_TX_STATS_SWAP( &((tOCTVC1_HW_MSG_RF_PORT_STATS_RSP *)pOCTVC1_HW_MSG_RF_PORT_STATS_RSP)->TxStats ); } \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_RF_PORT_STATS_RSP_SWAP( pOCTVC1_HW_MSG_RF_PORT_STATS_RSP )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_RF_PORT_LIST_CMD_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_RF_PORT_LIST_CMD * pOCTVC1_HW_MSG_RF_PORT_LIST_CMD = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_RF_PORT_LIST_CMD)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_RF_PORT_LIST_CMD *)pOCTVC1_HW_MSG_RF_PORT_LIST_CMD)->Header ); } \
|
|
{ mOCTVC1_CURSOR_INDEX_GET_SWAP( &((tOCTVC1_HW_MSG_RF_PORT_LIST_CMD *)pOCTVC1_HW_MSG_RF_PORT_LIST_CMD)->IndexGet ); } \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_RF_PORT_LIST_CMD_SWAP( pOCTVC1_HW_MSG_RF_PORT_LIST_CMD )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_RF_PORT_LIST_RSP_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_RF_PORT_LIST_RSP * pOCTVC1_HW_MSG_RF_PORT_LIST_RSP = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_RF_PORT_LIST_RSP)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_RF_PORT_LIST_RSP *)pOCTVC1_HW_MSG_RF_PORT_LIST_RSP)->Header ); } \
|
|
{ mOCTVC1_CURSOR_INDEX_GET_SWAP( &((tOCTVC1_HW_MSG_RF_PORT_LIST_RSP *)pOCTVC1_HW_MSG_RF_PORT_LIST_RSP)->IndexGet ); } \
|
|
{ mOCTVC1_LIST_INDEX_GET_SWAP( &((tOCTVC1_HW_MSG_RF_PORT_LIST_RSP *)pOCTVC1_HW_MSG_RF_PORT_LIST_RSP)->IndexList ); } \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_RF_PORT_LIST_RSP_SWAP( pOCTVC1_HW_MSG_RF_PORT_LIST_RSP )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_RF_PORT_LIST_ANTENNA_CMD_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_RF_PORT_LIST_ANTENNA_CMD * pOCTVC1_HW_MSG_RF_PORT_LIST_ANTENNA_CMD = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_RF_PORT_LIST_ANTENNA_CMD)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_RF_PORT_LIST_ANTENNA_CMD *)pOCTVC1_HW_MSG_RF_PORT_LIST_ANTENNA_CMD)->Header ); } \
|
|
{ mOCTVC1_CURSOR_INDEX_GET_SUB_INDEX_SWAP( &((tOCTVC1_HW_MSG_RF_PORT_LIST_ANTENNA_CMD *)pOCTVC1_HW_MSG_RF_PORT_LIST_ANTENNA_CMD)->SubIndexGet ); } \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_RF_PORT_LIST_ANTENNA_CMD_SWAP( pOCTVC1_HW_MSG_RF_PORT_LIST_ANTENNA_CMD )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_RF_PORT_LIST_ANTENNA_RSP_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_RF_PORT_LIST_ANTENNA_RSP * pOCTVC1_HW_MSG_RF_PORT_LIST_ANTENNA_RSP = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_RF_PORT_LIST_ANTENNA_RSP)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_RF_PORT_LIST_ANTENNA_RSP *)pOCTVC1_HW_MSG_RF_PORT_LIST_ANTENNA_RSP)->Header ); } \
|
|
{ mOCTVC1_CURSOR_INDEX_GET_SUB_INDEX_SWAP( &((tOCTVC1_HW_MSG_RF_PORT_LIST_ANTENNA_RSP *)pOCTVC1_HW_MSG_RF_PORT_LIST_ANTENNA_RSP)->SubIndexGet ); } \
|
|
{ mOCTVC1_LIST_INDEX_GET_SUB_INDEX_SWAP( &((tOCTVC1_HW_MSG_RF_PORT_LIST_ANTENNA_RSP *)pOCTVC1_HW_MSG_RF_PORT_LIST_ANTENNA_RSP)->SubIndexList ); } \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_RF_PORT_LIST_ANTENNA_RSP_SWAP( pOCTVC1_HW_MSG_RF_PORT_LIST_ANTENNA_RSP )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_CMD_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_CMD * pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_CMD = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_CMD)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_CMD *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_CMD)->Header ); } \
|
|
((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_CMD *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_CMD)->ulPortIndex = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_CMD *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_CMD)->ulPortIndex); \
|
|
((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_CMD *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_CMD)->ulAntennaIndex = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_CMD *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_CMD)->ulAntennaIndex); \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_CMD_SWAP( pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_CMD )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_RSP_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_RSP * pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_RSP = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_RSP)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_RSP)->Header ); } \
|
|
((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_RSP)->ulPortIndex = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_RSP)->ulPortIndex); \
|
|
((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_RSP)->ulAntennaIndex = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_RSP)->ulAntennaIndex); \
|
|
((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_RSP)->ulEnableFlag = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_RSP)->ulEnableFlag); \
|
|
((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_RSP)->lRxGaindB = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_RSP)->lRxGaindB); \
|
|
{ mOCTVC1_RADIO_RX_GAIN_CTRL_MODE_ENUM_SWAP( &((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_RSP)->ulRxGainMode ); } \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_RSP_SWAP( pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_RX_CONFIG_RSP )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_CMD_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_CMD * pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_CMD = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_CMD)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_CMD *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_CMD)->Header ); } \
|
|
((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_CMD *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_CMD)->ulPortIndex = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_CMD *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_CMD)->ulPortIndex); \
|
|
((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_CMD *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_CMD)->ulAntennaIndex = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_CMD *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_CMD)->ulAntennaIndex); \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_CMD_SWAP( pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_CMD )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_RSP_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_RSP * pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_RSP = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_RSP)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_RSP)->Header ); } \
|
|
((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_RSP)->ulPortIndex = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_RSP)->ulPortIndex); \
|
|
((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_RSP)->ulAntennaIndex = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_RSP)->ulAntennaIndex); \
|
|
((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_RSP)->ulEnableFlag = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_RSP)->ulEnableFlag); \
|
|
((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_RSP)->lTxGaindB = \
|
|
mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_RSP *)pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_RSP)->lTxGaindB); \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_RSP_SWAP( pOCTVC1_HW_MSG_RF_PORT_INFO_ANTENNA_TX_CONFIG_RSP )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_CMD_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_CMD * pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_CMD = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_CMD)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_CMD *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_CMD)->Header ); } \
|
|
}
|
|
#else
|
|
#define mOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_CMD_SWAP( pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_CMD )
|
|
#endif /* _OCT_ENDIAN_TYPE_LE_ */
|
|
|
|
#if defined( _OCT_ENDIAN_TYPE_LE_ )
|
|
#define mOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_RSP_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_RSP * pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_RSP = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_RSP)\
|
|
{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_RSP *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_RSP)->Header ); } \
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{ mOCTVC1_HW_CLOCK_SYNC_MGR_SOURCE_ENUM_SWAP( &((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_RSP *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_RSP)->ulClkSourceRef ); } \
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{ mOCTVC1_HW_CLOCK_SYNC_MGR_SOURCE_SELECTION_ENUM_SWAP( &((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_RSP *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_RSP)->ulClkSourceSelection ); } \
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}
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#else
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#define mOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_RSP_SWAP( pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_RSP )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
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#define mOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_CMD_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_CMD * pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_CMD = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_CMD)\
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{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_CMD *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_CMD)->Header ); } \
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((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_CMD *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_CMD)->ulResetStatsFlag = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_CMD *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_CMD)->ulResetStatsFlag); \
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}
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#else
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#define mOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_CMD_SWAP( pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_CMD )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
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#define mOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP * pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP)\
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{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP)->Header ); } \
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{ mOCTVC1_HW_CLOCK_SYNC_MGR_STATE_ENUM_SWAP( &((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP)->ulState ); } \
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((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP)->lClockError = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP)->lClockError); \
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((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP)->lDroppedCycles = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP)->lDroppedCycles); \
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((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP)->ulPllFreqHz = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP)->ulPllFreqHz); \
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((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP)->ulPllFractionalFreqHz = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP)->ulPllFractionalFreqHz); \
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((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP)->ulSlipCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP)->ulSlipCnt); \
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((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP)->ulSyncLosseCnt = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP)->ulSyncLosseCnt); \
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{ mOCTVC1_HW_CLOCK_SYNC_MGR_SOURCE_STATE_ENUM_SWAP( &((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP)->ulSourceState ); } \
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((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP)->ulDacValue = \
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mOCT_SWAP32_IF_LE(((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP)->ulDacValue); \
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}
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#else
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#define mOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP_SWAP( pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_STATS_RSP )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
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#define mOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_SOURCE_CMD_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_SOURCE_CMD * pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_SOURCE_CMD = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_SOURCE_CMD)\
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{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_SOURCE_CMD *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_SOURCE_CMD)->Header ); } \
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}
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#else
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#define mOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_SOURCE_CMD_SWAP( pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_SOURCE_CMD )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
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#define mOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_SOURCE_RSP_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_SOURCE_RSP * pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_SOURCE_RSP = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_SOURCE_RSP)\
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{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_SOURCE_RSP *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_SOURCE_RSP)->Header ); } \
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{ mOCTVC1_HW_CLOCK_SYNC_MGR_SOURCE_ENUM_SWAP( &((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_SOURCE_RSP *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_SOURCE_RSP)->ulClkSourceRef ); } \
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{ mOCTVC1_HW_CLOCK_SYNC_MGR_SOURCE_STATE_ENUM_SWAP( &((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_SOURCE_RSP *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_SOURCE_RSP)->ulSourceState ); } \
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}
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#else
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#define mOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_SOURCE_RSP_SWAP( pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_INFO_SOURCE_RSP )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
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#define mOCTVC1_HW_MSG_CLOCK_SYNC_MGR_MODIFY_SOURCE_CMD_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_MODIFY_SOURCE_CMD * pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_MODIFY_SOURCE_CMD = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_MODIFY_SOURCE_CMD)\
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{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_MODIFY_SOURCE_CMD *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_MODIFY_SOURCE_CMD)->Header ); } \
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{ mOCTVC1_HW_CLOCK_SYNC_MGR_SOURCE_ENUM_SWAP( &((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_MODIFY_SOURCE_CMD *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_MODIFY_SOURCE_CMD)->ulClkSourceRef ); } \
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{ mOCTVC1_HW_CLOCK_SYNC_MGR_SOURCE_STATE_ENUM_SWAP( &((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_MODIFY_SOURCE_CMD *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_MODIFY_SOURCE_CMD)->ulSourceState ); } \
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}
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#else
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#define mOCTVC1_HW_MSG_CLOCK_SYNC_MGR_MODIFY_SOURCE_CMD_SWAP( pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_MODIFY_SOURCE_CMD )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#if defined( _OCT_ENDIAN_TYPE_LE_ )
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#define mOCTVC1_HW_MSG_CLOCK_SYNC_MGR_MODIFY_SOURCE_RSP_SWAP( _f_pParms ){ tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_MODIFY_SOURCE_RSP * pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_MODIFY_SOURCE_RSP = (_f_pParms); SWAP_UNUSED(pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_MODIFY_SOURCE_RSP)\
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{ mOCTVC1_MSG_HEADER_SWAP( &((tOCTVC1_HW_MSG_CLOCK_SYNC_MGR_MODIFY_SOURCE_RSP *)pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_MODIFY_SOURCE_RSP)->Header ); } \
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}
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#else
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|
#define mOCTVC1_HW_MSG_CLOCK_SYNC_MGR_MODIFY_SOURCE_RSP_SWAP( pOCTVC1_HW_MSG_CLOCK_SYNC_MGR_MODIFY_SOURCE_RSP )
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#endif /* _OCT_ENDIAN_TYPE_LE_ */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __OCTVC1_HW_API_SWAP_H__ */
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