Swapped system_stm32f0xx.c for the one that come with the Discovery firmware
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@ -6,14 +6,24 @@
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* @date 23-March-2012
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* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
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* This file contains the system clock configuration for STM32F0xx devices,
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* and is generated by the clock configuration tool
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* STM32F0xx_Clock_Configuration_V1.0.0.xls
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* and is customized for use with STM32F0-DISCOVERY Kit.
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* The STM32F0xx is configured to run at 48 MHz, following the three
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* configuration below:
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* - PLL_SOURCE_HSI (default): HSI (~8MHz) used to clock the PLL, and
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* the PLL is used as system clock source.
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* - PLL_SOURCE_HSE : HSE (8MHz) used to clock the PLL, and
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* the PLL is used as system clock source.
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* - PLL_SOURCE_HSE_BYPASS : HSE bypassed with an external clock
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* (8MHz, coming from ST-Link) used to clock
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* the PLL, and the PLL is used as system
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* clock source.
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*
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*
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* 1. This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
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* and Divider factors, AHB/APBx prescalers and Flash settings),
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* depending on the configuration made in the clock xls tool.
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* depending on the configuration selected (see above).
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* This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32f0xx.s" file.
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@ -39,31 +49,6 @@
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* through PLL, and you are using different crystal you have to adapt the HSE
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* value to your own configuration.
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*
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* 5. This file configures the system clock as follows:
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*=============================================================================
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* System Clock Configuration
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*=============================================================================
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* System Clock source | PLL(HSE)
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*-----------------------------------------------------------------------------
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* SYSCLK | 48000000 Hz
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*-----------------------------------------------------------------------------
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* HCLK | 48000000 Hz
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*-----------------------------------------------------------------------------
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* AHB Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB1 Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB2 Prescaler | 1
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*-----------------------------------------------------------------------------
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* HSE Frequency | 8000000 Hz
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*-----------------------------------------------------------------------------
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* PLL MUL | 6
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*-----------------------------------------------------------------------------
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* VDD | 3.3 V
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*-----------------------------------------------------------------------------
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* Flash Latency | 1 WS
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*-----------------------------------------------------------------------------
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*=============================================================================
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******************************************************************************
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* @attention
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*
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@ -113,6 +98,13 @@
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/** @addtogroup STM32F0xx_System_Private_Defines
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* @{
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*/
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/* Select the PLL clock source */
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#define PLL_SOURCE_HSI // HSI (~8MHz) used to clock the PLL, and the PLL is used as system clock source
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//#define PLL_SOURCE_HSE // HSE (8MHz) used to clock the PLL, and the PLL is used as system clock source
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//#define PLL_SOURCE_HSE_BYPASS // HSE bypassed with an external clock (8MHz, coming from ST-Link) used to clock
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// the PLL, and the PLL is used as system clock source
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/**
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* @}
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*/
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@ -281,8 +273,46 @@ static void SetSysClock(void)
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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/* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
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#if defined (PLL_SOURCE_HSI)
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/* At this stage the HSI is already enabled */
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/* Enable Prefetch Buffer and set Flash Latency */
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FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
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/* HCLK = SYSCLK */
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RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
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/* PCLK = HCLK */
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RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
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/* PLL configuration = (HSI/2) * 12 = ~48 MHz */
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
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RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL12);
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/* Enable PLL */
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RCC->CR |= RCC_CR_PLLON;
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/* Wait till PLL is ready */
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while((RCC->CR & RCC_CR_PLLRDY) == 0)
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{
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}
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/* Select PLL as system clock source */
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
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RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
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/* Wait till PLL is used as system clock source */
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while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
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{
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}
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#else
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#if defined (PLL_SOURCE_HSE)
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/* Enable HSE */
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RCC->CR |= ((uint32_t)RCC_CR_HSEON);
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#elif defined (PLL_SOURCE_HSE_BYPASS)
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/* HSE oscillator bypassed with external clock */
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RCC->CR |= (uint32_t)(RCC_CR_HSEON | RCC_CR_HSEBYP);
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#endif /* PLL_SOURCE_HSE */
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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@ -336,6 +366,7 @@ static void SetSysClock(void)
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{ /* If HSE fails to start-up, the application will have wrong clock
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configuration. User can add here some code to deal with this error */
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}
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#endif /* PLL_SOURCE_HSI */
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}
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/**
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