Major restructuring to match STM peripherals library; added auto flash programming via OpenOCD

This commit is contained in:
Mike Szczys 2012-06-16 13:47:01 -05:00
parent 6c17053b93
commit 61b6afcbcc
79 changed files with 11860 additions and 2654 deletions

5
lib/inc/stm32f0xx_conf.h → Device/stm32f0xx_conf.h Executable file → Normal file
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@ -1,6 +1,6 @@
/**
******************************************************************************
* @file IO_Toggle/stm32f0xx_conf.h
* @file stm32F0xx_conf.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
@ -31,7 +31,7 @@
/* Includes ------------------------------------------------------------------*/
/* Comment the line below to disable peripheral header file inclusion */
#include "stm32f0xx_adc.h"
/* #include "stm32f0xx_adc.h" */
#include "stm32f0xx_cec.h"
#include "stm32f0xx_crc.h"
#include "stm32f0xx_comp.h"
@ -58,7 +58,6 @@
/* Uncomment the line below to expanse the "assert_param" macro in the
Standard Peripheral Library drivers code */
/* #define USE_FULL_ASSERT 1 */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F0xx devices.
@ -61,7 +61,7 @@
* @{
*/
/* Uncomment the line below according to the target STM32F-0 device used in your
/* Uncomment the line below according to the target STM32F0 device used in your
application
*/
@ -71,8 +71,9 @@
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
- STM32F0xx devices are STM32F050xx microcontrollers where the Flash memory
density ranges between 32 and 64 Kbytes.
STM32F0xx devices are:
- STM32F050xx microcontrollers where the Flash memory density can go up to 32 Kbytes.
- STM32F051xx microcontrollers where the Flash memory density can go up to 64 Kbytes.
*/
#if !defined (STM32F0XX)
@ -138,11 +139,11 @@
#endif /* LSE_VALUE */
/**
* @brief STM32F0xx Standard Peripheral Library version number V1.0.0
* @brief STM32F0xx Standard Peripheral Library version number V1.0.1
*/
#define __STM32F0XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F0XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
#define __STM32F0XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0XX_STDPERIPH_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F0XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0XX_STDPERIPH_VERSION ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\
|(__STM32F0XX_STDPERIPH_VERSION_SUB1 << 16)\
@ -2176,266 +2177,263 @@ typedef struct
/* */
/******************************************************************************/
/******************** Bits definition for RTC_TR register *******************/
#define RTC_TR_PM ((uint32_t)0x00400000) /*!< */
#define RTC_TR_HT ((uint32_t)0x00300000) /*!< */
#define RTC_TR_HT_0 ((uint32_t)0x00100000) /*!< */
#define RTC_TR_HT_1 ((uint32_t)0x00200000) /*!< */
#define RTC_TR_HU ((uint32_t)0x000F0000) /*!< */
#define RTC_TR_HU_0 ((uint32_t)0x00010000) /*!< */
#define RTC_TR_HU_1 ((uint32_t)0x00020000) /*!< */
#define RTC_TR_HU_2 ((uint32_t)0x00040000) /*!< */
#define RTC_TR_HU_3 ((uint32_t)0x00080000) /*!< */
#define RTC_TR_MNT ((uint32_t)0x00007000) /*!< */
#define RTC_TR_MNT_0 ((uint32_t)0x00001000) /*!< */
#define RTC_TR_MNT_1 ((uint32_t)0x00002000) /*!< */
#define RTC_TR_MNT_2 ((uint32_t)0x00004000) /*!< */
#define RTC_TR_MNU ((uint32_t)0x00000F00) /*!< */
#define RTC_TR_MNU_0 ((uint32_t)0x00000100) /*!< */
#define RTC_TR_MNU_1 ((uint32_t)0x00000200) /*!< */
#define RTC_TR_MNU_2 ((uint32_t)0x00000400) /*!< */
#define RTC_TR_MNU_3 ((uint32_t)0x00000800) /*!< */
#define RTC_TR_ST ((uint32_t)0x00000070) /*!< */
#define RTC_TR_ST_0 ((uint32_t)0x00000010) /*!< */
#define RTC_TR_ST_1 ((uint32_t)0x00000020) /*!< */
#define RTC_TR_ST_2 ((uint32_t)0x00000040) /*!< */
#define RTC_TR_SU ((uint32_t)0x0000000F) /*!< */
#define RTC_TR_SU_0 ((uint32_t)0x00000001) /*!< */
#define RTC_TR_SU_1 ((uint32_t)0x00000002) /*!< */
#define RTC_TR_SU_2 ((uint32_t)0x00000004) /*!< */
#define RTC_TR_SU_3 ((uint32_t)0x00000008) /*!< */
#define RTC_TR_PM ((uint32_t)0x00400000)
#define RTC_TR_HT ((uint32_t)0x00300000)
#define RTC_TR_HT_0 ((uint32_t)0x00100000)
#define RTC_TR_HT_1 ((uint32_t)0x00200000)
#define RTC_TR_HU ((uint32_t)0x000F0000)
#define RTC_TR_HU_0 ((uint32_t)0x00010000)
#define RTC_TR_HU_1 ((uint32_t)0x00020000)
#define RTC_TR_HU_2 ((uint32_t)0x00040000)
#define RTC_TR_HU_3 ((uint32_t)0x00080000)
#define RTC_TR_MNT ((uint32_t)0x00007000)
#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
#define RTC_TR_MNU ((uint32_t)0x00000F00)
#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
#define RTC_TR_ST ((uint32_t)0x00000070)
#define RTC_TR_ST_0 ((uint32_t)0x00000010)
#define RTC_TR_ST_1 ((uint32_t)0x00000020)
#define RTC_TR_ST_2 ((uint32_t)0x00000040)
#define RTC_TR_SU ((uint32_t)0x0000000F)
#define RTC_TR_SU_0 ((uint32_t)0x00000001)
#define RTC_TR_SU_1 ((uint32_t)0x00000002)
#define RTC_TR_SU_2 ((uint32_t)0x00000004)
#define RTC_TR_SU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_DR register *******************/
#define RTC_DR_YT ((uint32_t)0x00F00000) /*!< */
#define RTC_DR_YT_0 ((uint32_t)0x00100000) /*!< */
#define RTC_DR_YT_1 ((uint32_t)0x00200000) /*!< */
#define RTC_DR_YT_2 ((uint32_t)0x00400000) /*!< */
#define RTC_DR_YT_3 ((uint32_t)0x00800000) /*!< */
#define RTC_DR_YU ((uint32_t)0x000F0000) /*!< */
#define RTC_DR_YU_0 ((uint32_t)0x00010000) /*!< */
#define RTC_DR_YU_1 ((uint32_t)0x00020000) /*!< */
#define RTC_DR_YU_2 ((uint32_t)0x00040000) /*!< */
#define RTC_DR_YU_3 ((uint32_t)0x00080000) /*!< */
#define RTC_DR_WDU ((uint32_t)0x0000E000) /*!< */
#define RTC_DR_WDU_0 ((uint32_t)0x00002000) /*!< */
#define RTC_DR_WDU_1 ((uint32_t)0x00004000) /*!< */
#define RTC_DR_WDU_2 ((uint32_t)0x00008000) /*!< */
#define RTC_DR_MT ((uint32_t)0x00001000) /*!< */
#define RTC_DR_MU ((uint32_t)0x00000F00) /*!< */
#define RTC_DR_MU_0 ((uint32_t)0x00000100) /*!< */
#define RTC_DR_MU_1 ((uint32_t)0x00000200) /*!< */
#define RTC_DR_MU_2 ((uint32_t)0x00000400) /*!< */
#define RTC_DR_MU_3 ((uint32_t)0x00000800) /*!< */
#define RTC_DR_DT ((uint32_t)0x00000030) /*!< */
#define RTC_DR_DT_0 ((uint32_t)0x00000010) /*!< */
#define RTC_DR_DT_1 ((uint32_t)0x00000020) /*!< */
#define RTC_DR_DU ((uint32_t)0x0000000F) /*!< */
#define RTC_DR_DU_0 ((uint32_t)0x00000001) /*!< */
#define RTC_DR_DU_1 ((uint32_t)0x00000002) /*!< */
#define RTC_DR_DU_2 ((uint32_t)0x00000004) /*!< */
#define RTC_DR_DU_3 ((uint32_t)0x00000008) /*!< */
#define RTC_DR_YT ((uint32_t)0x00F00000)
#define RTC_DR_YT_0 ((uint32_t)0x00100000)
#define RTC_DR_YT_1 ((uint32_t)0x00200000)
#define RTC_DR_YT_2 ((uint32_t)0x00400000)
#define RTC_DR_YT_3 ((uint32_t)0x00800000)
#define RTC_DR_YU ((uint32_t)0x000F0000)
#define RTC_DR_YU_0 ((uint32_t)0x00010000)
#define RTC_DR_YU_1 ((uint32_t)0x00020000)
#define RTC_DR_YU_2 ((uint32_t)0x00040000)
#define RTC_DR_YU_3 ((uint32_t)0x00080000)
#define RTC_DR_WDU ((uint32_t)0x0000E000)
#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
#define RTC_DR_MT ((uint32_t)0x00001000)
#define RTC_DR_MU ((uint32_t)0x00000F00)
#define RTC_DR_MU_0 ((uint32_t)0x00000100)
#define RTC_DR_MU_1 ((uint32_t)0x00000200)
#define RTC_DR_MU_2 ((uint32_t)0x00000400)
#define RTC_DR_MU_3 ((uint32_t)0x00000800)
#define RTC_DR_DT ((uint32_t)0x00000030)
#define RTC_DR_DT_0 ((uint32_t)0x00000010)
#define RTC_DR_DT_1 ((uint32_t)0x00000020)
#define RTC_DR_DU ((uint32_t)0x0000000F)
#define RTC_DR_DU_0 ((uint32_t)0x00000001)
#define RTC_DR_DU_1 ((uint32_t)0x00000002)
#define RTC_DR_DU_2 ((uint32_t)0x00000004)
#define RTC_DR_DU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_CR register *******************/
#define RTC_CR_COE ((uint32_t)0x00800000) /*!< */
#define RTC_CR_OSEL ((uint32_t)0x00600000) /*!< */
#define RTC_CR_OSEL_0 ((uint32_t)0x00200000) /*!< */
#define RTC_CR_OSEL_1 ((uint32_t)0x00400000) /*!< */
#define RTC_CR_POL ((uint32_t)0x00100000) /*!< */
#define RTC_CR_CALSEL ((uint32_t)0x00080000) /*!< */
#define RTC_CR_BCK ((uint32_t)0x00040000) /*!< */
#define RTC_CR_SUB1H ((uint32_t)0x00020000) /*!< */
#define RTC_CR_ADD1H ((uint32_t)0x00010000) /*!< */
#define RTC_CR_TSIE ((uint32_t)0x00008000) /*!< */
#define RTC_CR_ALRAIE ((uint32_t)0x00001000) /*!< */
#define RTC_CR_TSE ((uint32_t)0x00000800) /*!< */
#define RTC_CR_ALRAE ((uint32_t)0x00000100) /*!< */
#define RTC_CR_DCE ((uint32_t)0x00000080) /*!< */
#define RTC_CR_FMT ((uint32_t)0x00000040) /*!< */
#define RTC_CR_BYPSHAD ((uint32_t)0x00000020) /*!< */
#define RTC_CR_REFCKON ((uint32_t)0x00000010) /*!< */
#define RTC_CR_TSEDGE ((uint32_t)0x00000008) /*!< */
#define RTC_CR_COE ((uint32_t)0x00800000)
#define RTC_CR_OSEL ((uint32_t)0x00600000)
#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
#define RTC_CR_POL ((uint32_t)0x00100000)
#define RTC_CR_CALSEL ((uint32_t)0x00080000)
#define RTC_CR_BCK ((uint32_t)0x00040000)
#define RTC_CR_SUB1H ((uint32_t)0x00020000)
#define RTC_CR_ADD1H ((uint32_t)0x00010000)
#define RTC_CR_TSIE ((uint32_t)0x00008000)
#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
#define RTC_CR_TSE ((uint32_t)0x00000800)
#define RTC_CR_ALRAE ((uint32_t)0x00000100)
#define RTC_CR_DCE ((uint32_t)0x00000080)
#define RTC_CR_FMT ((uint32_t)0x00000040)
#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
#define RTC_CR_REFCKON ((uint32_t)0x00000010)
#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
/******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_RECALPF ((uint32_t)0x00010000) /*!< */
#define RTC_ISR_TAMP3F ((uint32_t)0x00008000) /*!< */
#define RTC_ISR_TAMP2F ((uint32_t)0x00004000) /*!< */
#define RTC_ISR_TAMP1F ((uint32_t)0x00002000) /*!< */
#define RTC_ISR_TSOVF ((uint32_t)0x00001000) /*!< */
#define RTC_ISR_TSF ((uint32_t)0x00000800) /*!< */
#define RTC_ISR_ALRAF ((uint32_t)0x00000100) /*!< */
#define RTC_ISR_INIT ((uint32_t)0x00000080) /*!< */
#define RTC_ISR_INITF ((uint32_t)0x00000040) /*!< */
#define RTC_ISR_RSF ((uint32_t)0x00000020) /*!< */
#define RTC_ISR_INITS ((uint32_t)0x00000010) /*!< */
#define RTC_ISR_SHPF ((uint32_t)0x00000008) /*!< */
#define RTC_ISR_ALRAWF ((uint32_t)0x00000001) /*!< */
#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
#define RTC_ISR_TSF ((uint32_t)0x00000800)
#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
#define RTC_ISR_INIT ((uint32_t)0x00000080)
#define RTC_ISR_INITF ((uint32_t)0x00000040)
#define RTC_ISR_RSF ((uint32_t)0x00000020)
#define RTC_ISR_INITS ((uint32_t)0x00000010)
#define RTC_ISR_SHPF ((uint32_t)0x00000008)
#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
/******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) /*!< */
#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) /*!< */
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
/******************** Bits definition for RTC_ALRMAR register ***************/
#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) /*!< */
#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) /*!< */
#define RTC_ALRMAR_DT ((uint32_t)0x30000000) /*!< */
#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) /*!< */
#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) /*!< */
#define RTC_ALRMAR_DU ((uint32_t)0x0F000000) /*!< */
#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) /*!< */
#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) /*!< */
#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) /*!< */
#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) /*!< */
#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) /*!< */
#define RTC_ALRMAR_PM ((uint32_t)0x00400000) /*!< */
#define RTC_ALRMAR_HT ((uint32_t)0x00300000) /*!< */
#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) /*!< */
#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) /*!< */
#define RTC_ALRMAR_HU ((uint32_t)0x000F0000) /*!< */
#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) /*!< */
#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) /*!< */
#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) /*!< */
#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) /*!< */
#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) /*!< */
#define RTC_ALRMAR_MNT ((uint32_t)0x00007000) /*!< */
#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) /*!< */
#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) /*!< */
#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) /*!< */
#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00) /*!< */
#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) /*!< */
#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) /*!< */
#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) /*!< */
#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) /*!< */
#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) /*!< */
#define RTC_ALRMAR_ST ((uint32_t)0x00000070) /*!< */
#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) /*!< */
#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) /*!< */
#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) /*!< */
#define RTC_ALRMAR_SU ((uint32_t)0x0000000F) /*!< */
#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) /*!< */
#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) /*!< */
#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) /*!< */
#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) /*!< */
#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_WPR register ******************/
#define RTC_WPR_KEY ((uint32_t)0x000000FF) /*!< */
#define RTC_WPR_KEY ((uint32_t)0x000000FF)
/******************** Bits definition for RTC_SSR register ******************/
#define RTC_SSR_SS ((uint32_t)0x0003FFFF) /*!< */
#define RTC_SSR_SS ((uint32_t)0x0003FFFF)
/******************** Bits definition for RTC_SHIFTR register ***************/
#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) /*!< */
#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) /*!< */
#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
/******************** Bits definition for RTC_TSTR register *****************/
#define RTC_TSTR_PM ((uint32_t)0x00400000) /*!< */
#define RTC_TSTR_HT ((uint32_t)0x00300000) /*!< */
#define RTC_TSTR_HT_0 ((uint32_t)0x00100000) /*!< */
#define RTC_TSTR_HT_1 ((uint32_t)0x00200000) /*!< */
#define RTC_TSTR_HU ((uint32_t)0x000F0000) /*!< */
#define RTC_TSTR_HU_0 ((uint32_t)0x00010000) /*!< */
#define RTC_TSTR_HU_1 ((uint32_t)0x00020000) /*!< */
#define RTC_TSTR_HU_2 ((uint32_t)0x00040000) /*!< */
#define RTC_TSTR_HU_3 ((uint32_t)0x00080000) /*!< */
#define RTC_TSTR_MNT ((uint32_t)0x00007000) /*!< */
#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000) /*!< */
#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000) /*!< */
#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000) /*!< */
#define RTC_TSTR_MNU ((uint32_t)0x00000F00) /*!< */
#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100) /*!< */
#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200) /*!< */
#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400) /*!< */
#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800) /*!< */
#define RTC_TSTR_ST ((uint32_t)0x00000070) /*!< */
#define RTC_TSTR_ST_0 ((uint32_t)0x00000010) /*!< */
#define RTC_TSTR_ST_1 ((uint32_t)0x00000020) /*!< */
#define RTC_TSTR_ST_2 ((uint32_t)0x00000040) /*!< */
#define RTC_TSTR_SU ((uint32_t)0x0000000F) /*!< */
#define RTC_TSTR_SU_0 ((uint32_t)0x00000001) /*!< */
#define RTC_TSTR_SU_1 ((uint32_t)0x00000002) /*!< */
#define RTC_TSTR_SU_2 ((uint32_t)0x00000004) /*!< */
#define RTC_TSTR_SU_3 ((uint32_t)0x00000008) /*!< */
#define RTC_TSTR_PM ((uint32_t)0x00400000)
#define RTC_TSTR_HT ((uint32_t)0x00300000)
#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
#define RTC_TSTR_HU ((uint32_t)0x000F0000)
#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
#define RTC_TSTR_MNT ((uint32_t)0x00007000)
#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
#define RTC_TSTR_ST ((uint32_t)0x00000070)
#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
#define RTC_TSTR_SU ((uint32_t)0x0000000F)
#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_TSDR register *****************/
#define RTC_TSDR_WDU ((uint32_t)0x0000E000) /*!< */
#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000) /*!< */
#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000) /*!< */
#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000) /*!< */
#define RTC_TSDR_MT ((uint32_t)0x00001000) /*!< */
#define RTC_TSDR_MU ((uint32_t)0x00000F00) /*!< */
#define RTC_TSDR_MU_0 ((uint32_t)0x00000100) /*!< */
#define RTC_TSDR_MU_1 ((uint32_t)0x00000200) /*!< */
#define RTC_TSDR_MU_2 ((uint32_t)0x00000400) /*!< */
#define RTC_TSDR_MU_3 ((uint32_t)0x00000800) /*!< */
#define RTC_TSDR_DT ((uint32_t)0x00000030) /*!< */
#define RTC_TSDR_DT_0 ((uint32_t)0x00000010) /*!< */
#define RTC_TSDR_DT_1 ((uint32_t)0x00000020) /*!< */
#define RTC_TSDR_DU ((uint32_t)0x0000000F) /*!< */
#define RTC_TSDR_DU_0 ((uint32_t)0x00000001) /*!< */
#define RTC_TSDR_DU_1 ((uint32_t)0x00000002) /*!< */
#define RTC_TSDR_DU_2 ((uint32_t)0x00000004) /*!< */
#define RTC_TSDR_DU_3 ((uint32_t)0x00000008) /*!< */
#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
#define RTC_TSDR_MT ((uint32_t)0x00001000)
#define RTC_TSDR_MU ((uint32_t)0x00000F00)
#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
#define RTC_TSDR_DT ((uint32_t)0x00000030)
#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
#define RTC_TSDR_DU ((uint32_t)0x0000000F)
#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_TSSSR register ****************/
#define RTC_TSSSR_SS ((uint32_t)0x0003FFFF)
/******************** Bits definition for RTC_CAL register *****************/
#define RTC_CAL_CALP ((uint32_t)0x00008000) /*!< */
#define RTC_CAL_CALW8 ((uint32_t)0x00004000) /*!< */
#define RTC_CAL_CALW16 ((uint32_t)0x00002000) /*!< */
#define RTC_CAL_CALM ((uint32_t)0x000001FF) /*!< */
#define RTC_CAL_CALM_0 ((uint32_t)0x00000001) /*!< */
#define RTC_CAL_CALM_1 ((uint32_t)0x00000002) /*!< */
#define RTC_CAL_CALM_2 ((uint32_t)0x00000004) /*!< */
#define RTC_CAL_CALM_3 ((uint32_t)0x00000008) /*!< */
#define RTC_CAL_CALM_4 ((uint32_t)0x00000010) /*!< */
#define RTC_CAL_CALM_5 ((uint32_t)0x00000020) /*!< */
#define RTC_CAL_CALM_6 ((uint32_t)0x00000040) /*!< */
#define RTC_CAL_CALM_7 ((uint32_t)0x00000080) /*!< */
#define RTC_CAL_CALM_8 ((uint32_t)0x00000100) /*!< */
#define RTC_CAL_CALP ((uint32_t)0x00008000)
#define RTC_CAL_CALW8 ((uint32_t)0x00004000)
#define RTC_CAL_CALW16 ((uint32_t)0x00002000)
#define RTC_CAL_CALM ((uint32_t)0x000001FF)
#define RTC_CAL_CALM_0 ((uint32_t)0x00000001)
#define RTC_CAL_CALM_1 ((uint32_t)0x00000002)
#define RTC_CAL_CALM_2 ((uint32_t)0x00000004)
#define RTC_CAL_CALM_3 ((uint32_t)0x00000008)
#define RTC_CAL_CALM_4 ((uint32_t)0x00000010)
#define RTC_CAL_CALM_5 ((uint32_t)0x00000020)
#define RTC_CAL_CALM_6 ((uint32_t)0x00000040)
#define RTC_CAL_CALM_7 ((uint32_t)0x00000080)
#define RTC_CAL_CALM_8 ((uint32_t)0x00000100)
/******************** Bits definition for RTC_TAFCR register ****************/
#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000) /*!< */
#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000) /*!< */
#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000) /*!< */
#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000) /*!< */
#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000) /*!< */
#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800) /*!< */
#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800) /*!< */
#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000) /*!< */
#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700) /*!< */
#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100) /*!< */
#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200) /*!< */
#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400) /*!< */
#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080) /*!< */
#define RTC_TAFCR_TAMP3EDGE ((uint32_t)0x00000040) /*!< */
#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020) /*!< */
#define RTC_TAFCR_TAMP2EDGE ((uint32_t)0x00000010) /*!< */
#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008) /*!< */
#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) /*!< */
#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) /*!< */
#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) /*!< */
#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
#define RTC_TAFCR_TAMP2EDGE ((uint32_t)0x00000010)
#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
/******************** Bits definition for RTC_ALRMASSR register *************/
#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000) /*!< */
#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000) /*!< */
#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000) /*!< */
#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000) /*!< */
#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000) /*!< */
#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF) /*!< */
#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
/******************** Bits definition for RTC_BKP0R register ****************/
#define RTC_BKP0R ((uint32_t)0xFFFFFFFF) /*!< */
#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP1R register ****************/
#define RTC_BKP1R ((uint32_t)0xFFFFFFFF) /*!< */
#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP2R register ****************/
#define RTC_BKP2R ((uint32_t)0xFFFFFFFF) /*!< */
#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP3R register ****************/
#define RTC_BKP3R ((uint32_t)0xFFFFFFFF) /*!< */
#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP4R register ****************/
#define RTC_BKP4R ((uint32_t)0xFFFFFFFF) /*!< */
#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
/******************************************************************************/
/* */

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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention

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<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
Notes for STM32F0xx CMSIS</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2012 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
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<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
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<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F0xx&nbsp;CMSIS
update History</a><o:p></o:p></span></li>
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<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F0xx CMSIS
update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1 / 20-April-2012</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add reference to STM32F050xx (Flash memory up to 32 Kbytes) and STM32F051xx (</span><span style="font-size: 10pt; font-family: Verdana;">Flash memory up to 64 Kbytes</span><span style="font-size: 10pt; font-family: Verdana;">) devices</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">RTC register bits definition: remove reference to Tamper3</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 23-March-2012</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">First official release&nbsp;for <span style="font-weight: bold; font-style: italic;">STM32F0xx devices</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All source files: license disclaimer text update and add link to the License file on ST Internet</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">change MCO bits value:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">change <span style="font-style: italic;">RCC_CFGR_MCO_HSI14</span> value from 0x03000000 to 0x01000000</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add <span style="font-style: italic;">RCC_CFGR_MCO_LSI</span> having value 0x02000000</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add <span style="font-style: italic;">RCC_CFGR_MCO_LSE</span> having value 0x03000000</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new bit <span style="font-style: italic;">RCC_CSR_V18PWRRSTF</span> having value 0x00800000</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">TIM_OR</span> bits definition values corrected</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename <span style="font-style: italic;">ADC_ISR_EOS</span> to <span style="font-style: italic;">ADC_ISR_EOSEQ</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename <span style="font-style: italic;">ADC_IER_EOSIE</span> to <span style="font-style: italic;">ADC_IER_EOSEQIE</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename <span style="font-style: italic;">ADC_CFGR1_AUTDLY</span> to <span style="font-style: italic;">ADC_CFGR1_WAIT</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename option bit <span style="font-style: italic;">FLASH_OBR_BOOT1</span> to <span style="font-style: italic;">FLASH_OBR_nBOOT1</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename <span style="font-style: italic;">FLASH_OBR_VDDA_ANALOG</span> to <span style="font-style: italic;">FLASH_OBR_VDDA_MONITOR</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add Flash and OB keys (removed from Flash driver)</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">system_stm32f0xx.c</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SetSysClock()</span> function: code optimized&nbsp;</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Miscellaneous&nbsp;formatting<br></span></li></ul></ul>
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0RC1 / 27-January-2012<o:p></o:p></span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square">
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Official version (V1.0.0) Release Candidate 1</span><span style="font-size: 10pt; font-family: Verdana;"></span></li>
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">All source
files: update disclaimer to add reference to the&nbsp;new license agreement</span></li>
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update all peripherals bits definitions<br>
</span></li>
</ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span><span style="font-weight: bold; font-style: italic;"></span></span>
<ul style="margin-top: 0in;" type="disc">
</ul>
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">package</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"> except in compliance with the License. You may obtain a copy of the License at:<br><br></span></p><div style="text-align: center;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a target="_blank" href="http://www.st.com/software_license_agreement_liberty_v2">http://www.st.com/software_license_agreement_liberty_v2</a></span><br><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"></span></div><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"><br>Unless
required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS, <br>WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See
the License for the specific language governing permissions and
limitations under the License.</span>
<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
<hr align="center" size="2" width="100%"></span></div>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">For
complete documentation on </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32<span style="color: black;">
Microcontrollers visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="font-size: 10pt; font-family: Verdana;"><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank"></a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
</td>
</tr>
</tbody>
</table>
<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
</td>
</tr>
</tbody>
</table>
</div>
<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
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/**
******************************************************************************
* @file startup_stm32f0xx.s
* @author MCD Application Team
* @version V1.0.1
* @date 20-April-2012
* @brief STM32F0xx Devices vector table for Atollic toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M0 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m0
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF108F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M0. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word 0
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_1_IRQHandler
.word EXTI2_3_IRQHandler
.word EXTI4_15_IRQHandler
.word TS_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_3_IRQHandler
.word DMA1_Channel4_5_IRQHandler
.word ADC1_COMP_IRQHandler
.word TIM1_BRK_UP_TRG_COM_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM6_DAC_IRQHandler
.word 0
.word TIM14_IRQHandler
.word TIM15_IRQHandler
.word TIM16_IRQHandler
.word TIM17_IRQHandler
.word I2C1_IRQHandler
.word I2C2_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word 0
.word CEC_IRQHandler
.word 0
.word BootRAM /* @0x108. This is for boot in RAM mode for
STM32F0xx devices. */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_1_IRQHandler
.thumb_set EXTI0_1_IRQHandler,Default_Handler
.weak EXTI2_3_IRQHandler
.thumb_set EXTI2_3_IRQHandler,Default_Handler
.weak EXTI4_15_IRQHandler
.thumb_set EXTI4_15_IRQHandler,Default_Handler
.weak TS_IRQHandler
.thumb_set TS_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_3_IRQHandler
.thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
.weak DMA1_Channel4_5_IRQHandler
.thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
.weak ADC1_COMP_IRQHandler
.thumb_set ADC1_COMP_IRQHandler,Default_Handler
.weak TIM1_BRK_UP_TRG_COM_IRQHandler
.thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM14_IRQHandler
.thumb_set TIM14_IRQHandler,Default_Handler
.weak TIM15_IRQHandler
.thumb_set TIM15_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_IRQHandler
.thumb_set I2C1_IRQHandler,Default_Handler
.weak I2C2_IRQHandler
.thumb_set I2C2_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
;* File Name : startup_stm32f0xx.s
;* Author : MCD Application Team
;* Version : V1.0.1
;* Date : 20-April-2012
;* Description : STM32F0xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM0 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; @attention
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD RTC_IRQHandler ; RTC through EXTI Line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
DCD TS_IRQHandler ; TS
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
DCD 0 ; Reserved
DCD TIM14_IRQHandler ; TIM14
DCD TIM15_IRQHandler ; TIM15
DCD TIM16_IRQHandler ; TIM16
DCD TIM17_IRQHandler ; TIM17
DCD I2C1_IRQHandler ; I2C1
DCD I2C2_IRQHandler ; I2C2
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD CEC_IRQHandler ; CEC
DCD 0 ; Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_1_IRQHandler [WEAK]
EXPORT EXTI2_3_IRQHandler [WEAK]
EXPORT EXTI4_15_IRQHandler [WEAK]
EXPORT TS_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_5_IRQHandler [WEAK]
EXPORT ADC1_COMP_IRQHandler [WEAK]
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM15_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_1_IRQHandler
EXTI2_3_IRQHandler
EXTI4_15_IRQHandler
TS_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_3_IRQHandler
DMA1_Channel4_5_IRQHandler
ADC1_COMP_IRQHandler
TIM1_BRK_UP_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM6_DAC_IRQHandler
TIM14_IRQHandler
TIM15_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_IRQHandler
I2C2_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
CEC_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

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@ -0,0 +1,292 @@
/**
******************************************************************************
* @file startup_stm32f0xx.s
* @author MCD Application Team
* @version V1.0.1
* @date 20-April-2012
* @brief STM32F0xx Devices vector table for RIDE7 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M0 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m0
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF108F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/*******************************************************************************
*
* The minimal vector table for a Cortex M0. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word 0
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_1_IRQHandler
.word EXTI2_3_IRQHandler
.word EXTI4_15_IRQHandler
.word TS_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_3_IRQHandler
.word DMA1_Channel4_5_IRQHandler
.word ADC1_COMP_IRQHandler
.word TIM1_BRK_UP_TRG_COM_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM6_DAC_IRQHandler
.word 0
.word TIM14_IRQHandler
.word TIM15_IRQHandler
.word TIM16_IRQHandler
.word TIM17_IRQHandler
.word I2C1_IRQHandler
.word I2C2_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word 0
.word CEC_IRQHandler
.word 0
.word BootRAM /* @0x108. This is for boot in RAM mode for
STM32F0xx devices. */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_1_IRQHandler
.thumb_set EXTI0_1_IRQHandler,Default_Handler
.weak EXTI2_3_IRQHandler
.thumb_set EXTI2_3_IRQHandler,Default_Handler
.weak EXTI4_15_IRQHandler
.thumb_set EXTI4_15_IRQHandler,Default_Handler
.weak TS_IRQHandler
.thumb_set TS_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_3_IRQHandler
.thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
.weak DMA1_Channel4_5_IRQHandler
.thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
.weak ADC1_COMP_IRQHandler
.thumb_set ADC1_COMP_IRQHandler,Default_Handler
.weak TIM1_BRK_UP_TRG_COM_IRQHandler
.thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM14_IRQHandler
.thumb_set TIM14_IRQHandler,Default_Handler
.weak TIM15_IRQHandler
.thumb_set TIM15_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_IRQHandler
.thumb_set I2C1_IRQHandler,Default_Handler
.weak I2C2_IRQHandler
.thumb_set I2C2_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@ -0,0 +1,330 @@
;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
;* File Name : startup_stm32f0xx.s
;* Author : MCD Application Team
;* Version : V1.0.1
;* Date : 20-April-2012
;* Description : STM32F0xx Devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M0 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
; @attention
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD RTC_IRQHandler ; RTC through EXTI Line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
DCD TS_IRQHandler ; TS
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
DCD 0 ; Reserved
DCD TIM14_IRQHandler ; TIM14
DCD TIM15_IRQHandler ; TIM15
DCD TIM16_IRQHandler ; TIM16
DCD TIM17_IRQHandler ; TIM17
DCD I2C1_IRQHandler ; I2C1
DCD I2C2_IRQHandler ; I2C2
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD CEC_IRQHandler ; CEC
DCD 0 ; Reserved
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_1_IRQHandler
B EXTI0_1_IRQHandler
PUBWEAK EXTI2_3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_3_IRQHandler
B EXTI2_3_IRQHandler
PUBWEAK EXTI4_15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_15_IRQHandler
B EXTI4_15_IRQHandler
PUBWEAK TS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TS_IRQHandler
B TS_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_3_IRQHandler
B DMA1_Channel2_3_IRQHandler
PUBWEAK DMA1_Channel4_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_5_IRQHandler
B DMA1_Channel4_5_IRQHandler
PUBWEAK ADC1_COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC1_COMP_IRQHandler
B ADC1_COMP_IRQHandler
PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_UP_TRG_COM_IRQHandler
B TIM1_BRK_UP_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM14_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM14_IRQHandler
B TIM14_IRQHandler
PUBWEAK TIM15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM15_IRQHandler
B TIM15_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK I2C1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_IRQHandler
B I2C1_IRQHandler
PUBWEAK I2C2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_IRQHandler
B I2C2_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK CEC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CEC_IRQHandler
B CEC_IRQHandler
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

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@ -0,0 +1,353 @@
/**
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V1.0.1
* @date 20-April-2012
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
* This file contains the system clock configuration for STM32F0xx devices,
* and is generated by the clock configuration tool
* STM32F0xx_Clock_Configuration_V1.0.0.xls
*
* 1. This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
* and Divider factors, AHB/APBx prescalers and Flash settings),
* depending on the configuration made in the clock xls tool.
* This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f0xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* 2. After each device reset the HSI (8 MHz Range) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
* configure the system clock before to branch to main program.
*
* 3. If the system clock source selected by user fails to startup, the SystemInit()
* function will do nothing and HSI still used as system clock source. User can
* add some code to deal with this issue inside the SetSysClock() function.
*
* 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
* in "stm32f0xx.h" file. When HSE is used as system clock source, directly or
* through PLL, and you are using different crystal you have to adapt the HSE
* value to your own configuration.
*
* 5. This file configures the system clock as follows:
*=============================================================================
* System Clock Configuration
*=============================================================================
* System Clock source | PLL(HSE)
*-----------------------------------------------------------------------------
* SYSCLK | 48000000 Hz
*-----------------------------------------------------------------------------
* HCLK | 48000000 Hz
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 1
*-----------------------------------------------------------------------------
* APB2 Prescaler | 1
*-----------------------------------------------------------------------------
* HSE Frequency | 8000000 Hz
*-----------------------------------------------------------------------------
* PLL MUL | 6
*-----------------------------------------------------------------------------
* VDD | 3.3 V
*-----------------------------------------------------------------------------
* Flash Latency | 1 WS
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f0xx_system
* @{
*/
/** @addtogroup STM32F0xx_System_Private_Includes
* @{
*/
#include "stm32f0xx.h"
/**
* @}
*/
/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F0xx_System_Private_Defines
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F0xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F0xx_System_Private_Variables
* @{
*/
uint32_t SystemCoreClock = 48000000;
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
*/
/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
* @{
*/
static void SetSysClock(void);
/**
* @}
*/
/** @addtogroup STM32F0xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system.
* Initialize the Embedded Flash Interface, the PLL and update the
* SystemCoreClock variable.
* @param None
* @retval None
*/
void SystemInit (void)
{
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
RCC->CFGR &= (uint32_t)0xF8FFB80C;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
RCC->CFGR &= (uint32_t)0xFFC0FFFF;
/* Reset PREDIV1[3:0] bits */
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
/* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
/* Reset HSI14 bit */
RCC->CR2 &= (uint32_t)0xFFFFFFFE;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
/* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
SetSysClock();
}
/**
* @brief Update SystemCoreClock according to Clock Register Values
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value
* 8 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
* @param None
* @retval None
*/
void SystemCoreClockUpdate (void)
{
uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor ----------------------*/
pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
pllmull = ( pllmull >> 18) + 2;
if (pllsource == 0x00)
{
/* HSI oscillator clock divided by 2 selected as PLL clock entry */
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
}
else
{
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
/* HSE oscillator clock selected as PREDIV1 clock entry */
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
}
break;
default: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK clock frequency ----------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
/**
* @brief Configures the System clock frequency, AHB/APBx prescalers and Flash
* settings.
* @note This function should be called only once the RCC clock configuration
* is reset to the default reset state (done in SystemInit() function).
* @param None
* @retval None
*/
static void SetSysClock(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Enable Prefetch Buffer and set Flash Latency */
FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
/* PLL configuration = HSE * 6 = 48 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6);
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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<?xml version="1.0" encoding="UTF-8"?>
<!--
@date: 29.07.2011
@note Copyright (C) 2011 ARM Limited. All rights reserved.
@par
ARM Limited (ARM) is supplying this software for use with Cortex-M
processor based microcontroller, but can be equally used for other
suitable processor architectures. This file can be freely distributed.
Modifications to this file shall be clearly marked.
@par
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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</xs:group>
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<xs:group ref="registerPropertiesGroup" minOccurs="0"/>
<xs:element name="peripherals">
<xs:complexType>
<xs:sequence>
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<xs:complexType>
<xs:sequence>
<xs:element name="name" type="xs:Name"/>
<xs:element name="version" type="xs:string" minOccurs="0"/>
<xs:element name="description" type="xs:string" minOccurs="0"/>
<xs:element name="groupName" type="xs:string" minOccurs="0"/>
<xs:element name="prependToName" type="xs:string" minOccurs="0"/>
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<xs:group ref="registerPropertiesGroup" minOccurs="0"/>
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<xs:element name="interrupt" type="interruptType" minOccurs="0" maxOccurs="unbounded"/>
<xs:element name="registers" minOccurs="0" maxOccurs="1">
<xs:complexType>
<xs:sequence>
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<xs:complexType>
<xs:sequence>
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<xs:element name="name" type="registerNameType"/> <!-- was xs:Name -->
<xs:element name="displayName" type="xs:string" minOccurs="0"/>
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<html>
<head>
<title>CMSIS Debug Support</title>
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<body>
<h1>CMSIS Debug Support</h1>
<p align="center">This file describes the CMSIS Debug support available with CMSIS (starting V1.30).</p>
<p align="center">Version: 1.02 - 25. July 2011</p>
<p class="TinyT">Information in this file, the accompany manuals, and software is<br>
Copyright © ARM Ltd.<br>All rights reserved.
</p>
<hr>
<p><span style="FONT-WEIGHT: bold">Revision History</span></p>
<ul>
<li>Version 1.00: Initial Release. </li>
<li>Version 1.01: Internal Review. </li>
<li>Version 1.02: Removed product specific information. </li>
</ul>
<hr>
<h2>Contents</h2>
<ol>
<li class="LI2"><a href="#About">About</a></li>
<li class="LI2"><a href="#ITM_DbgAcc">Cortex-M3 / Cortex-M4 ITM Debug Access</a></li>
<li class="LI2"><a href="#DbgIn_DbgOut">Debug IN / OUT functions</a></li>
<li class="LI2"><a href="#ITM_DbgSup">ITM Debug Support in Debugger</a></li>
</ol>
<p>&nbsp;</p>
<h2><a name="About"></a>About</h2>
<p>
CMSIS provides for Cortex-M3 / Cortex-M4 processor based microcontrollers debug support via the Instrumented Trace Macrocell (ITM).
This document describes the available CMSIS Debug functions and the used methods.
</p>
<p>&nbsp;</p>
<h2><a name="ITM_DbgAcc"></a>Cortex-M3 / Cortex-M4 ITM Debug Access</h2>
<p>
The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with
the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has
32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM
communication channels are used by CMSIS to output the following information:
</p>
<ul>
<li>ITM Channel 0: used for printf-style output via the debug interface.</li>
<li>ITM Channel 31: is reserved for RTOS kernel awareness debugging.</li>
</ul>
<p>&nbsp;</p>
<h2><a name="DbgIn_DbgOut"></a>Debug IN / OUT functions</h2>
<p>CMSIS provides following debug functions:</p>
<ul>
<li>ITM_SendChar (uses ITM channel 0)</li>
<li>ITM_ReceiveChar (uses global variable)</li>
<li>ITM_CheckChar (uses global variable)</li>
</ul>
<h3>ITM_SendChar</h3>
<p>
<strong>ITM_SendChar</strong> is used to transmit a character over ITM channel 0 from
the microcontroller system to the debug system. <br>
Only a 8 bit value is transmitted.
</p>
<pre>
static __INLINE uint32_t ITM_SendChar (uint32_t ch)
{
/* check if debugger connected and ITM channel enabled for tracing */
if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &amp;&amp;
(ITM-&gt;TCR & ITM_TCR_ITMENA) &amp;&amp;
(ITM-&gt;TER & (1UL &lt;&lt; 0)) )
{
while (ITM-&gt;PORT[0].u32 == 0);
ITM-&gt;PORT[0].u8 = (uint8_t)ch;
}
return (ch);
}</pre>
<h3>ITM_ReceiveChar</h3>
<p>
ITM communication channel is only capable for OUT direction. For IN direction
a global variable is used. A simple mechanism detects if a character is received.
The project to test need to be build with debug information.
</p>
<p>
The global variable <strong>ITM_RxBuffer</strong> is used to transmit a 8 bit value from debug system
to microcontroller system. <strong>ITM_RxBuffer</strong> is 32 bit wide to
ensure a proper handshake.
</p>
<pre>
extern volatile int32_t ITM_RxBuffer; /* variable to receive characters */
</pre>
<p>
A dedicated bit pattern is used to determine if <strong>ITM_RxBuffer</strong> is empty
or contains a valid value.
</p>
<pre>
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
</pre>
<p>
<strong>ITM_ReceiveChar</strong> is used to receive a 8 bit value from the debug system. The function is nonblocking.
It returns the received character or '-1' if no character was available.
</p>
<pre>
static __INLINE int32_t ITM_ReceiveChar (void) {
int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
return (ch);
}
</pre>
<h3>ITM_CheckChar</h3>
<p>
<strong>ITM_CheckChar</strong> is used to check if a character is received.
</p>
<pre>
static __INLINE int32_t ITM_CheckChar (void) {
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
return (0); /* no character available */
} else {
return (1); /* character available */
}
}</pre>
<p>&nbsp;</p>
<h2><a name="ITM_DbgSup"></a>ITM Debug Support in a Debugger</h2>
<p>
The Debugger shall offer a dedicated console window for printf style debug input and output using the CMSIS defined ITM methods described above.
</p>
<p>Direction: Microcontroller -&gt; Debugger:</p>
<ul>
<li>
at the beginning of a debug session the debugger shall enable ITM trace on channel 0 and continuously snoop for channel 0 data on the ITM trace
stream it receives from the Microcontroller's CoreSight ITM unit
</li>
<li>
data received via the ITM communication channel 0 is interpreted as charater and gets redirected into the dedicated <strong>Console Window</strong>
</li>
</ul>
<p>Direction: Debugger -&gt; Microcontroller:</p>
<ul>
<li>
at the beginning of a debug session the debugger shall seek for the presence of the global variable named <strong>ITM_RxBuffer</strong> in the debug
information of the application being loaded
</li>
<li>
strings entered into the <strong>Console Window</strong> are written by the debugger as a stream of char values via the variable <strong>ITM_RxBuffer</strong>.
</li>
<li>
the debugger writes the next character into the <strong>ITM_RxBuffer</strong> only once the value has been read and the <strong>ITM_RXBUFFER_EMPTY</strong> value being set.
(refer to: ITM_ReceiveChar()).
</ul>
</body>
</html>

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<html>
<head>
<title>CMSIS Version History</title>
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<h1>CMSIS Version History</h1>
<p align="center">This document describes the changes between the different CMSIS versions.</p>
<p align="center">Version: 2.10 - July 2011</p>
<p class="TinyT">Information in this file, the accompany manuals, and software is<br>
Copyright © ARM Ltd.<br>All rights reserved.
</p>
<hr>
<h2>Contents</h2>
<ol>
<li class="LI2"><a href="#Toolchain">Used Toolchains</a></li>
<li class="LI2"><a href="#6">Changes to version V2.00</a></li>
<li class="LI2"><a href="#5">Changes to version V1.30</a></li>
<li class="LI2"><a href="#4">Changes to version V1.20</a></li>
<li class="LI2"><a href="#2">Open Points</a></li>
<li class="LI2"><a href="#1">Limitations</a></li>
</ol>
<h2><a name="Toolchain"></a>Used Toolchains</h2>
<p>
Following toolchains have been used for test / verification:</i>.
</p>
<ul>
<li>ARM: MDK-ARM Version 4.21</li>
<li>GNU: Sourcery G++ Lite Edition for ARM 2010.09-51</li>
<li>IAR: IAR Embedded Workbench Kickstart Edition V6.10</li>
</ul>
<h2><a name="6"></a>Changes to version V2.00</h2>
<h3>Added CMSIS DSP Software Library support for Cortex-M0 based MCUs</h3>
<p>
The <strong>CMSIS DSP Software Library</strong> provides now also libraries and examples for Cortex-M0.
</p>
<p>
For more information refer to <i>CMSIS DSP Library documentation</i>.
</p>
<h3>Added big endian support for DSP library</h3>
<p>
The <strong>CMSIS DSP Software Library</strong> provides now also pre-build libraries
and projects for big endian devices.
</p>
<p>
For more information refer to <i>CMSIS DSP Library documentation</i>.
</p>
<h3>Simplified folder structure for CMSIS include files</h3>
<p>
All CMSIS core include files as well as the DSP-Library header files are located in
a single folder <strong>./CMSIS/Include</strong>.
</p>
<h3>Changed folder structure for Device Support packages</h3>
<p>
Device Support packages are expected to be in folder <strong>./Device</strong> located at the
same level as <strong>./CMSIS</strong>.
</p>
<p>The new Device folder contains the following subfolders:</p>
<ul>
<li><b>Device</b></li>
<ul>
<li>&lt;<b>Vendor</b>&gt;
<ul>
<li>&lt;<b>Device</b>&gt; | &lt;<b>Device Series</b>&gt;
<ul>
<li><b>Include</b><br>
&lt;device&gt;.h<br>
system_&lt;device&gt;.h<br>
</li>
<li><b>Source</b>
<ul>
<li><b>Templates</b><br>
system_&lt;device&gt;.c<br>
<ul>
<li>&lt;<b>Toolchain</b>&gt;<br>
startup_&lt;device&gt;.s<br>
</li>
<li>&lt;<b>Toolchain</b>&gt;</li>
<li>...</li>
</ul>
</li>
</ul>
</li>
</ul>
<li>&lt;<b>Device</b>&gt; | &lt;<b>Device Series</b>&gt;</li>
<li>...</li>
</ul>
</li>
<li>&lt;<b>Vendor</b>&gt;</li>
<li>...</li>
</ul>
</li>
</ul>
<p>Template files are application specific files and are required to be copied to the project prior to use!</p>
<h3>Removed CMSIS core source files</h3>
<p>
The CMSIS core source files <strong>core_cm0.c, core_cm3.c, core_cm4.c</strong>
containing helper functions for older ARM compiler versions got removed.
</p>
<p>
For the <b>ARM Compiler Toolchain </b>version <b>V4.0.677</b> or later is
required!</p>
<h2><a name="5"></a>Changes to version V1.30</h2>
<h3>Added CMSIS DSP Software Library</h3>
<p>
The <strong>CMSIS DSP Software Library</strong> is a suite of common signal processing functions targeted
to Cortex-M processor based microcontrollers. Even though the code has been specifically
optimized towards using the extended DSP instruction set of the Cortex-M4 processor,
the library can be compiled for any Cortex-M processor.
</p>
<p>
For more information see <i>CMSIS DSP Library documentation</i>.
</p>
<h3>Added CMSIS System View Description</h3>
<p>
The <strong>CMSIS System View Description</strong> answers the challenges of accurate, detailed and
timely device aware peripheral debugging support for Cortex Microcontroller based
devices by the software development tools vendor community.
</p>
<p>
Silicon vendors shall create and maintain a formalized description of the debug view
for all the peripherals contained in their Cortex Microcontroller based devices.
Tool vendors use such descriptions to establish device specific debug support in
their debugging tools.
</p>
<p>
A standardized System View Description shall provide a common approach to
capturing peripheral debug related information in a machine readable files.
</p>
<p>
For more information see <i>CMSIS System View Description</i>.
</p>
<h3>Added Cortex-M4 Core Support</h3>
<p>
Additional folder <strong>CM4</strong>, containing the Cortex-M4 core support files, has been added.
</p>
<ul>
<li>CM0</li>
<li>CM3</li>
<li>CM4
<ul>
<li>CoreSupport</li>
<li>DeviceSupport</li>
</ul>
</li>
</ul>
<h3>New naming for Core Support Files</h3>
<p>
The new Core Support Files are:
</p>
<ul>
<li>core_cm#.h (# = 0, 3, 4)</li>
<li>core_cmFunc.h (Cortex-M Core Register access functions)</li>
<li>core_cmInstr.h (Cortex-M Core instructions)</li>
<li>core_cm4_simd.h (Cortex-M4 SIMD instructions)</li>
</ul>
<h2><a name="4"></a>Changes to version V1.20</h2>
<h3>Removed CMSIS Middelware packages</h3>
<p>
CMSIS Middleware is removed and no longer focus of CMSIS.
</p>
<h3>SystemFrequency renamed to SystemCoreClock</h3>
<p>
The variable name <strong>SystemCoreClock</strong> is more precise than <strong>SystemFrequency</strong>
because the variable holds the clock value at which the core is running.
</p>
<h3>Changed startup concept</h3>
<p>
The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit
from main) has the weakness that it does not work for controllers which need a already
configuerd clock system to configure the external memory controller.
</p>
<h5>Changed startup concept</h5>
<ul>
<li>
SystemInit() is called from startup file before <strong>premain</strong>.
</li>
<li>
<strong>SystemInit()</strong> configures the clock system and also configures
an existing external memory controller.
</li>
<li>
<strong>SystemInit()</strong> must not use global variables.
</li>
<li>
<strong>SystemCoreClock</strong> is initialized with a correct predefined value.
</li>
<li>
Additional function <strong>void SystemCoreClockUpdate (void)</strong> is provided.<br>
<strong>SystemCoreClockUpdate()</strong> updates the variable <strong>SystemCoreClock</strong>
and must be called whenever the core clock is changed.<br>
<strong>SystemCoreClockUpdate()</strong> evaluates the clock register settings and calculates
the current core clock.
</li>
</ul>
<h3>Advanced Debug Functions</h3>
<p>
ITM communication channel is only capable for OUT direction. To allow also communication for
IN direction a simple concept is provided.
</p>
<ul>
<li>
Global variable <strong>volatile int ITM_RxBuffer</strong> used for IN data.
</li>
<li>
Function <strong>int ITM_CheckChar (void)</strong> checks if a new character is available.
</li>
<li>
Function <strong>int ITM_ReceiveChar (void)</strong> retrieves the new character.
</li>
</ul>
<p>
For detailed explanation see file <strong>CMSIS debug support.htm</strong>.
</p>
<h3>Core Register Bit Definitions</h3>
<p>
Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the
defines correspond with the Cortex-M Technical Reference Manual.
</p>
<p>
e.g. SysTick structure with bit definitions
</p>
<pre>
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */</pre>
<h3>DoxyGen Tags</h3>
<p>
DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation
using DoxyGen.
</p>
<h3>Folder Structure</h3>
<p>
The folder structure is changed to differentiate the single support packages.
</p>
<ul>
<li>CM0</li>
<li>CM3
<ul>
<li>CoreSupport</li>
<li>DeviceSupport</li>
<ul>
<li>Vendor
<ul>
<li>Device
<ul>
<li>Startup
<ul>
<li>Toolchain</li>
<li>Toolchain</li>
<li>...</li>
</ul>
</li>
</ul>
</li>
<li>Device</li>
<li>...</li>
</ul>
</li>
<li>Vendor</li>
<li>...</li>
</ul>
</li>
<li>Example <i>(optional)</i>
<ul>
<li>Toolchain
<ul>
<li>Device</li>
<li>Device</li>
<li>...</li>
</ul>
</li>
<li>Toolchain</li>
<li>...</li>
</ul>
</li>
</ul>
</li>
<li>Documentation</li>
</ul>
<h2><a name="2"></a>Open Points</h2>
<p>
Following points need to be clarified and solved:
</p>
<ul>
<li>
<p>
Equivalent C and Assembler startup files.
</p>
<p>
Is there a need for having C startup files although assembler startup files are
very efficient and do not need to be changed?
<p/>
</li>
<li>
<p>
Placing of HEAP in external RAM.
</p>
<p>
It must be possible to place HEAP in external RAM if the device supports an
external memory controller.
</p>
</li>
<li>
<p>
Placing of STACK /HEAP.
</p>
<p>
STACK should always be placed at the end of internal RAM.
</p>
<p>
If HEAP is placed in internal RAM than it should be placed after RW ZI section.
</p>
</li>
</ul>
<h2><a name="1"></a>Limitations</h2>
<p>
The following limitations are not covered with the current CMSIS version:
</p>
<ul>
<li>
No <strong>C startup files</strong> are available.
</li>
</ul>

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* -------------------------------------------------------------------
* Copyright (C) 2011 ARM Limited. All rights reserved.
*
* Date: 25 July 2011
* Revision: V2.10
*
* Project: Cortex Microcontroller Software Interface Standard (CMSIS)
* Title: Release Note for CMSIS
*
* -------------------------------------------------------------------
NOTE - Open the index.html file to access CMSIS documentation
The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all
Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects
and reduces time-to-market for new embedded applications.
CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf").
Any user of the software package is bound to the terms and conditions of the end user license agreement.
You will find the following sub-directories:
Documentation - Contains CMSIS documentation.
DSP_Lib - MDK project files, Examples and source files etc.. to build the
CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.
Include - CMSIS Core Support and CMSIS DSP Include Files.
Lib - CMSIS DSP Binaries
---

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<h1>CMSIS Release Notes</h1>
<p align="center">Release Notes for CMSIS V2.00</p>
<p align="center">November 2010</p>
<p class="TinyT">Information in this file, the accompany manuals, and software is<br>
Copyright © ARM Ltd.<br>All rights reserved.
<p align="center"><img src="Documentation/CMSIS_Logo_Final.jpg" height="78" width="197">
</p>
<hr>
<h2>Contents</h2>
<ul>
<li class="LI2"><a href="Documentation/CMSIS_History.htm">CMSIS Version History</a>
lists the changes between the different CMSIS versions.
</li>
<li class="LI2"><a href="Documentation/CMSIS_Core.htm">CMSIS Core Support</a>
contains a general description for CMSIS.
</li>
<li class="LI2"><a href="Documentation/DSP_Lib/html/index.html">CMSIS DSP Software Library</a>
describes the CMSIS DSP software library.
</li>
<li class="LI2"><a href="Documentation/CMSIS_System_View_Description.htm">CMSIS System View Description</a>
describes the CMSIS System View Description.
</li>
<li class="LI2"><a href="Documentation/CMSIS_CM4_SIMD.htm">CMSIS Support for Cortex-M4 SIMD Instructions</a>
lists the Cortex-M4 instructions supported by CMSIS.
</li>
<li class="LI2"><a href="Documentation/CMSIS_DebugSupport.htm">CMSIS Debug Support</a>
describes the available CMSIS Debug functions and the used methods.
</li>
<li class="LI2"><a href="CMSIS END USER LICENCE AGREEMENT.pdf">License</a></li>
</ul>
</body>
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@ -3,12 +3,13 @@ AR=arm-none-eabi-ar
###########################################
vpath %.c src src/peripherals
vpath %.c STM32F0xx_StdPeriph_Driver/src
CFLAGS = -g -O2 -Wall
CFLAGS += -mlittle-endian -mthumb -mcpu=cortex-m0 -march=armv6s-m
CFLAGS += -ffreestanding -nostdlib
CFLAGS += -Iinc -Iinc/core -Iinc/peripherals
CFLAGS += -I../Device -ICMSIS/Include -ICMSIS/Device/ST/STM32F0xx/Include -ISTM32F0xx_StdPeriph_Driver/inc
SRCS = stm32f0xx_adc.c stm32f0xx_cec.c stm32f0xx_comp.c stm32f0xx_crc.c \
stm32f0xx_dac.c stm32f0xx_dbgmcu.c stm32f0xx_dma.c stm32f0xx_exti.c \

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<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
Notes for<o:p></o:p> </span><span style="font-size: 20pt; color: rgb(51, 102, 255); font-family: Verdana;">STM32F0xx Standard Peripherals Library Drivers</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span><br>
<span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
© 2012 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt;"><img style="border: 0px solid ; width: 86px; height: 65px;" alt="" id="_x0000_i1025" src="../../_htmresc/logo.bmp"></span></p>
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<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
<ol style="margin-top: 0cm;" start="1" type="1">
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F0xx Standard Peripherals Library Drivers update history</a><o:p></o:p></span></li>
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
</ol>
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F0xx Standard Peripherals Library Drivers update history</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1 / 20-April-2012</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All drivers, function's header: update </span><span style="font-size: 10pt; font-family: Verdana;">comments&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">and Doxygen&nbsp;tags&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">formatting</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx_pwr.c</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">PWR_PVDLevelConfig()</span>
function: remove value of the voltage threshold corresponding to each
PVD detection level, user should refer to the electrical
characteristics of the STM32F0xx device&nbsp;datasheet to have the correct
value</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx_usart.c/.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">USART_Init() </span>function: update baudrate computation to be in line with the formula described in the Reference Manual (RM0091)</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">USART_AutoBaudRateNewRequest()</span> function removed<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx_i2c.c</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">I2C_GetITStatus() </span>function: add test to check if the interrupt source is enabled or not</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 23-March-2012</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">First official release&nbsp;for <span style="font-weight: bold; font-style: italic;">STM32F0xx devices</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All source files: license disclaimer text update and add link to the License file on ST Internet</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx_comp.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">&nbsp;Correct values of <span style="font-style: italic;">COMP_Mode</span> parameter</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx_rcc.c/.h</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new reset flag <span style="font-style: italic;">V18PWRRSTF</span> in the RCC CSR&nbsp;register</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new <span style="font-style: italic;">MCO clock sources (LSI and LSE)</span> and change value of <span style="font-style: italic;">RCC_MCOSource_HSI14&nbsp;</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx_flash.c/.h</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new function <span style="font-style: italic;">FLASH_OB_SRAMParityConfig(</span>) to manage the SRAM parity enable option bit</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Flash and OB keys&nbsp;moved to <span style="font-style: italic;">stm32f0xx.h</span> file</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx_tim.c/.h</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add additional input for <span style="font-style: italic;">TIM14 clock&nbsp;</span> (HSE divided by 32 and MCO)&nbsp;</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Miscellaneous</span><span style="font-size: 10pt; font-family: Verdana;">&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">enhancement</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx_adc.c/.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Miscellaneous</span><span style="font-size: 10pt; font-family: Verdana;">&nbsp;update to be in line with bits naming&nbsp;in the Reference Manual (update done also in&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx.h file)</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx_i2c.c/.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Miscellaneous</span><span style="font-size: 10pt; font-family: Verdana;">&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">enhancement</span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul></ul>
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0RC1 / 27-January-2012</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="list-style-type: square;">
<li><span style="font-size: 10pt; font-family: Verdana;">Official version (V1.0.0) Release Candidate 1</span></li>
</ul>
<span style="font-size: 10pt; font-family: Verdana;"></span><br><span style="font-size: 10pt; font-family: Verdana;"></span><ul style="margin-top: 0cm;" type="square"></ul>
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">package</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"> except in compliance with the License. You may obtain a copy of the License at:<br><br></span></p><div style="text-align: center;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a target="_blank" href="http://www.st.com/software_license_agreement_liberty_v2">http://www.st.com/software_license_agreement_liberty_v2</a></span><br><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"></span></div><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"><br>Unless
required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS, <br>WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See
the License for the specific language governing permissions and
limitations under the License.</span><div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
<hr align="center" size="2" width="100%"></span></div>
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complete documentation on </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32<span style="color: black;">
Microcontrollers visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="font-size: 10pt; font-family: Verdana;"><a target="_blank" href="http://www.st.com/internet/mcu/family/141.jsp"><u><span style="color: blue;"></span></u></a></span><span style="color: black;"><o:p></o:p></span></p>
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_adc.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file contains all the functions prototypes for the ADC firmware
* library
******************************************************************************
@ -181,7 +181,7 @@ typedef struct
* @}
*/
/** @defgroup ADC_Scan_Direction
/** @defgroup ADC_DMA_Mode
* @{
*/

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_cec.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file contains all the functions prototypes for the CEC firmware
* library.
******************************************************************************

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_comp.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file contains all the functions prototypes for the COMP firmware
* library.
******************************************************************************

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_crc.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file contains all the functions prototypes for the CRC firmware
* library.
******************************************************************************

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_dac.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file contains all the functions prototypes for the DAC firmware
* library.
******************************************************************************

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_dbgmcu.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file contains all the functions prototypes for the DBGMCU firmware
* library.
******************************************************************************

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_dma.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file contains all the functions prototypes for the DMA firmware
* library.
******************************************************************************

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_exti.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file contains all the functions prototypes for the EXTI
* firmware library
******************************************************************************

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_flash.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file contains all the functions prototypes for the FLASH
* firmware library.
******************************************************************************

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_gpio.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file contains all the functions prototypes for the GPIO
* firmware library.
******************************************************************************

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_i2c.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file contains all the functions prototypes for the I2C firmware
* library
******************************************************************************

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_iwdg.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file contains all the functions prototypes for the IWDG
* firmware library.
******************************************************************************

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_misc.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file contains all the functions prototypes for the miscellaneous
* firmware library functions (add-on to CMSIS functions).
******************************************************************************

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_pwr.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file contains all the functions prototypes for the PWR firmware
* library.
******************************************************************************

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_rcc.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file contains all the functions prototypes for the RCC
* firmware library.
******************************************************************************

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_rtc.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file contains all the functions prototypes for the RTC firmware
* library.
******************************************************************************
@ -555,8 +555,6 @@ typedef struct
input tamper 1 */
#define RTC_Tamper_2 RTC_TAFCR_TAMP2E /*!< Tamper detection enable for
input tamper 2 */
#define RTC_Tamper_3 RTC_TAFCR_TAMP3E /*!< Tamper detection enable for
input tamper 3 */
#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
@ -629,7 +627,6 @@ typedef struct
* @{
*/
#define RTC_FLAG_RECALPF ((uint32_t)0x00010000)
#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000)
#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000)
#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)
@ -640,13 +637,12 @@ typedef struct
#define RTC_FLAG_INITS ((uint32_t)0x00000010)
#define RTC_FLAG_SHPF ((uint32_t)0x00000008)
#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RECALPF) || ((FLAG) == RTC_FLAG_TAMP3F) || \
#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RECALPF) || ((FLAG) == RTC_FLAG_SHPF) || \
((FLAG) == RTC_FLAG_TAMP2F) || ((FLAG) == RTC_FLAG_TAMP1F) || \
((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_INITS) || \
((FLAG) == RTC_FLAG_SHPF))
#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF06DF) == (uint32_t)RESET))
((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_INITS))
#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF86DF) == (uint32_t)RESET))
/**
* @}
@ -660,13 +656,12 @@ typedef struct
#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
#define RTC_IT_TAMP1 ((uint32_t)0x00020000)
#define RTC_IT_TAMP2 ((uint32_t)0x00040000)
#define RTC_IT_TAMP3 ((uint32_t)0x00080000)
#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF6FFB) == (uint32_t)RESET))
#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_ALRA) || \
((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_TAMP2) || \
((IT) == RTC_IT_TAMP3))
#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF16FFF) == (uint32_t)RESET))
((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_TAMP2))
#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF96FFF) == (uint32_t)RESET))
/**
* @}

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_spi.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file contains all the functions prototypes for the SPI
* firmware library.
******************************************************************************

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_syscfg.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file contains all the functions prototypes for the SYSCFG firmware
* library.
******************************************************************************

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_tim.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file contains all the functions prototypes for the TIM
* firmware library.
******************************************************************************

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_usart.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file contains all the functions prototypes for the USART
* firmware library.
******************************************************************************
@ -129,8 +129,8 @@ typedef struct
*/
#define USART_StopBits_1 ((uint32_t)0x00000000)
#define USART_StopBits_2 ((uint32_t)USART_CR2_STOP_1)
#define USART_StopBits_1_5 ((uint32_t)USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define USART_StopBits_2 USART_CR2_STOP_1
#define USART_StopBits_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
((STOPBITS) == USART_StopBits_2) || \
((STOPBITS) == USART_StopBits_1_5))
@ -143,8 +143,8 @@ typedef struct
*/
#define USART_Parity_No ((uint32_t)0x00000000)
#define USART_Parity_Even ((uint32_t)USART_CR1_PCE)
#define USART_Parity_Odd ((uint32_t)USART_CR1_PCE | USART_CR1_PS)
#define USART_Parity_Even USART_CR1_PCE
#define USART_Parity_Odd (USART_CR1_PCE | USART_CR1_PS)
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
((PARITY) == USART_Parity_Even) || \
((PARITY) == USART_Parity_Odd))
@ -169,9 +169,9 @@ typedef struct
*/
#define USART_HardwareFlowControl_None ((uint32_t)0x00000000)
#define USART_HardwareFlowControl_RTS ((uint32_t)USART_CR3_RTSE)
#define USART_HardwareFlowControl_CTS ((uint32_t)USART_CR3_CTSE)
#define USART_HardwareFlowControl_RTS_CTS ((uint32_t)USART_CR3_RTSE | USART_CR3_CTSE)
#define USART_HardwareFlowControl_RTS USART_CR3_RTSE
#define USART_HardwareFlowControl_CTS USART_CR3_CTSE
#define USART_HardwareFlowControl_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
(((CONTROL) == USART_HardwareFlowControl_None) || \
((CONTROL) == USART_HardwareFlowControl_RTS) || \
@ -283,8 +283,8 @@ typedef struct
*/
#define USART_WakeUpSource_AddressMatch ((uint32_t)0x00000000)
#define USART_WakeUpSource_StartBit ((uint32_t)USART_CR3_WUS_1)
#define USART_WakeUpSource_RXNE ((uint32_t)USART_CR3_WUS_0 | USART_CR3_WUS_1)
#define USART_WakeUpSource_StartBit USART_CR3_WUS_1
#define USART_WakeUpSource_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)
#define IS_USART_STOPMODE_WAKEUPSOURCE(SOURCE) (((SOURCE) == USART_WakeUpSource_AddressMatch) || \
((SOURCE) == USART_WakeUpSource_StartBit) || \
((SOURCE) == USART_WakeUpSource_RXNE))
@ -528,7 +528,6 @@ void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_Wake
/* AutoBaudRate functions *****************************************************/
void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate);
void USART_AutoBaudRateNewRequest(USART_TypeDef* USARTx);
/* Data transfers functions ***************************************************/
void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_wwdg.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file contains all the functions prototypes for the WWDG
* firmware library.
******************************************************************************

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_adc.c
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
* + Initialization and Configuration
@ -304,12 +304,10 @@ void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState Ne
* consumption when the ADC is not converting.
* @param ADCx: where x can be 1 to select the ADC1 peripheral.
* @note The ADC can be powered down:
* - During the Auto delay phase
* => The ADC is powered on again at the end of the delay (until the
* previous data is read from the ADC data register).
* - During the ADC is waiting for a trigger event
* => The ADC is powered up at the next trigger event (when the
* conversion is started).
* - During the Auto delay phase: The ADC is powered on again at the end
* of the delay (until the previous data is read from the ADC data register).
* - During the ADC is waiting for a trigger event: The ADC is powered up
* at the next trigger event (when the conversion is started).
* @param NewState: new state of the ADCx power Off.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -337,9 +335,8 @@ void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
* @note When the CPU clock is not fast enough to manage the data rate, a
* Hardware delay can be introduced between ADC conversions to reduce
* this data rate.
* @note The Hardware delay is inserted after :
* - after each conversions and until the previous data is read from the
* ADC data register
* @note The Hardware delay is inserted after each conversions and until the
* previous data is read from the ADC data register
* @note This is a way to automatically adapt the speed of the ADC to the speed
* of the system which will read the data.
* @note Any hardware triggers wich occur while a conversion is on going or
@ -676,8 +673,7 @@ void ADC_VbatCmd(FunctionalState NewState)
* @arg ADC_Channel_16: ADC Channel16 selected
* @arg ADC_Channel_17: ADC Channel17 selected
* @arg ADC_Channel_18: ADC Channel18 selected
* @param ADC_SampleTime: The sample time value to be set for the selected
* channel.
* @param ADC_SampleTime: The sample time value to be set for the selected channel.
* This parameter can be one of the following values:
* @arg ADC_SampleTime_1_5Cycles: Sample time equal to 1.5 cycles
* @arg ADC_SampleTime_7_5Cycles: Sample time equal to 7.5 cycles

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_cec.c
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the Consumer Electronics Control (CEC) peripheral:
* + Initialization and Configuration
@ -325,7 +325,7 @@ void CEC_StartOfMessage(void)
/**
* @brief Transmits message with an EOM bit.
* @param None.
* @param None
* @retval None
*/
void CEC_EndOfMessage(void)

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_comp.c
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the comparators (COMP1 and COMP2) peripheral:
* + Comparators configuration
@ -157,7 +157,6 @@ void COMP_DeInit(void)
* @arg COMP_Selection_COMP2: COMP2 selected
* @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains
* the configuration information for the specified COMP peripheral.
*
* @retval None
*/
void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct)
@ -218,8 +217,7 @@ void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct)
* @param NewState: new state of the COMP peripheral.
* This parameter can be: ENABLE or DISABLE.
* @note When enabled, the comparator compares the non inverting input with
* the inverting input and the comparison result is available
* on comparator output.
* the inverting input and the comparison result is available on comparator output.
* @note When disabled, the comparator doesn't perform comparison and the
* output level is low.
* @retval None
@ -272,15 +270,15 @@ void COMP_SwitchCmd(FunctionalState NewState)
/**
* @brief Return the output level (high or low) of the selected comparator.
* @note The output level depends on the selected polarity.
* If the polarity is not inverted:
* @note -Comparator output is low when the non-inverting input is at a lower
* @note If the polarity is not inverted:
* - Comparator output is low when the non-inverting input is at a lower
* voltage than the inverting input
* @note -Comparator output is high when the non-inverting input is at a higher
* - Comparator output is high when the non-inverting input is at a higher
* voltage than the inverting input
* @note If the polarity is inverted:
* @note -Comparator output is high when the non-inverting input is at a lower
* - Comparator output is high when the non-inverting input is at a lower
* voltage than the inverting input
* @note -Comparator output is low when the non-inverting input is at a higher
* - Comparator output is low when the non-inverting input is at a higher
* voltage than the inverting input
* @param COMP_Selection: the selected comparator.
* This parameter can be one of the following values:
@ -328,9 +326,9 @@ uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection)
/**
* @brief Enables or disables the window mode.
* In window mode, COMP1 and COMP2 non inverting inputs are connected
* @note In window mode, COMP1 and COMP2 non inverting inputs are connected
* together and only COMP1 non inverting input (PA1) can be used.
* param NewState: new state of the window mode.
* @param NewState: new state of the window mode.
* This parameter can be :
* @arg ENABLE: COMP1 and COMP2 non inverting inputs are connected together.
* @arg DISABLE: OMP1 and COMP2 non inverting inputs are disconnected.

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_crc.c
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file provides firmware functions to manage the following
* functionalities of CRC computation unit peripheral:
* + Configuration of the CRC computation unit

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_dbgmcu.c
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the Debug MCU (DBGMCU) peripheral:
* + Device and Revision ID management

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_dma.c
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the Direct Memory Access controller (DMA):
* + Initialization and Configuration
@ -472,8 +472,7 @@ void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, Functiona
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
*
* @note
* The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags
* @note The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags
* relative to the same channel is set (Transfer Complete, Half-transfer
* Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or
* DMAy_FLAG_TEx).
@ -528,8 +527,7 @@ FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
*
* @note
* Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags
* @note Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags
* relative to the same channel (Transfer Complete, Half-transfer Complete and
* Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
*
@ -569,8 +567,7 @@ void DMA_ClearFlag(uint32_t DMA_FLAG)
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
*
* @note
* The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other
* @note The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other
* interrupts relative to the same channel is set (Transfer Complete,
* Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx,
* DMAy_IT_HTx or DMAy_IT_TEx).
@ -624,8 +621,7 @@ ITStatus DMA_GetITStatus(uint32_t DMA_IT)
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
*
* @note
* Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other
* @note Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other
* interrupts relative to the same channel (Transfer Complete, Half-transfer
* Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and
* DMAy_IT_TEx).

View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_exti.c
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the EXTI peripheral:
* + Initialization and Configuration
@ -117,11 +117,6 @@ void EXTI_DeInit(void)
/**
* @brief Initializes the EXTI peripheral according to the specified
* parameters in the EXTI_InitStruct.
* EXTI_Line specifies the EXTI line (EXTI0....EXTI27).
* EXTI_Mode specifies which EXTI line is used as interrupt or an event.
* EXTI_Trigger selects the trigger. When the trigger occurs, interrupt
* pending bit will be set.
* EXTI_LineCmd controls (Enable/Disable) the EXTI line.
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure that
* contains the configuration information for the EXTI peripheral.
* @retval None
@ -194,7 +189,7 @@ void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
* @brief Generates a Software interrupt on selected EXTI line.
* @param EXTI_Line: specifies the EXTI line on which the software interrupt
* will be generated.
* This parameter can be any combination of EXTI_Linex where x can be (0..19)
* This parameter can be any combination of EXTI_Linex where x can be (0..27).
* @retval None
*/
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
@ -224,8 +219,7 @@ void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
/**
* @brief Checks whether the specified EXTI line flag is set or not.
* @param EXTI_Line: specifies the EXTI line flag to check.
* This parameter can be:
* EXTI_Linex: External interrupt line x where x(0..19).
* This parameter can be EXTI_Linex where x can be (0..27).
* @retval The new state of EXTI_Line (SET or RESET).
*/
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
@ -248,7 +242,7 @@ FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
/**
* @brief Clears the EXTI's line pending flags.
* @param EXTI_Line: specifies the EXTI lines flags to clear.
* This parameter can be any combination of EXTI_Linex where x can be (0..19)
* This parameter can be any combination of EXTI_Linex where x can be (0..27).
* @retval None
*/
void EXTI_ClearFlag(uint32_t EXTI_Line)
@ -262,8 +256,7 @@ void EXTI_ClearFlag(uint32_t EXTI_Line)
/**
* @brief Checks whether the specified EXTI line is asserted or not.
* @param EXTI_Line: specifies the EXTI line to check.
* This parameter can be:
* EXTI_Linex: External interrupt line x where x(0..19).
* This parameter can be EXTI_Linex where x can be (0..27).
* @retval The new state of EXTI_Line (SET or RESET).
*/
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
@ -289,7 +282,7 @@ ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
/**
* @brief Clears the EXTI's line pending bits.
* @param EXTI_Line: specifies the EXTI lines to clear.
* This parameter can be any combination of EXTI_Linex where x can be (0..19).
* This parameter can be any combination of EXTI_Linex where x can be (0..27).
* @retval None
*/
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)

View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_flash.c
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the FLASH peripheral:
* - FLASH Interface configuration
@ -252,10 +252,9 @@ void FLASH_Lock(void)
/**
* @brief Erases a specified page in program memory.
* @note To correctly run this function, the FLASH_Unlock() function
* must be called before.
* Call the FLASH_Lock() to disable the flash memory access
* (recommended to protect the FLASH memory against possible unwanted operation)
* @note To correctly run this function, the FLASH_Unlock() function must be called before.
* @note Call the FLASH_Lock() to disable the flash memory access (recommended
* to protect the FLASH memory against possible unwanted operation)
* @param Page_Address: The page address in program memory to be erased.
* @note A Page is erased in the Program memory only if the address to load
* is the start address of a page (multiple of 1024 bytes).
@ -292,10 +291,9 @@ FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
/**
* @brief Erases all FLASH pages.
* @note To correctly run this function, the FLASH_Unlock() function
* must be called before.
* Call the FLASH_Lock() to disable the flash memory access
* (recommended to protect the FLASH memory against possible unwanted operation)
* @note To correctly run this function, the FLASH_Unlock() function must be called before.
* @note Call the FLASH_Lock() to disable the flash memory access (recommended
* to protect the FLASH memory against possible unwanted operation)
* @param None
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
@ -326,10 +324,9 @@ FLASH_Status FLASH_EraseAllPages(void)
/**
* @brief Programs a word at a specified address.
* @note To correctly run this function, the FLASH_Unlock() function
* must be called before.
* Call the FLASH_Lock() to disable the flash memory access
* (recommended to protect the FLASH memory against possible unwanted operation)
* @note To correctly run this function, the FLASH_Unlock() function must be called before.
* @note Call the FLASH_Lock() to disable the flash memory access (recommended
* to protect the FLASH memory against possible unwanted operation)
* @param Address: specifies the address to be programmed.
* @param Data: specifies the data to be programmed.
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
@ -384,10 +381,9 @@ FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
/**
* @brief Programs a half word at a specified address.
* @note To correctly run this function, the FLASH_Unlock() function
* must be called before.
* Call the FLASH_Lock() to disable the flash memory access
* (recommended to protect the FLASH memory against possible unwanted operation)
* @note To correctly run this function, the FLASH_Unlock() function must be called before.
* @note Call the FLASH_Lock() to disable the flash memory access (recommended
* to protect the FLASH memory against possible unwanted operation)
* @param Address: specifies the address to be programmed.
* @param Data: specifies the data to be programmed.
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
@ -517,10 +513,9 @@ void FLASH_OB_Launch(void)
/**
* @brief Erases the FLASH option bytes.
* @note To correctly run this function, the FLASH_OB_Unlock() function
* must be called before.
* Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes
* (recommended to protect the FLASH memory against possible unwanted operation)
* @note To correctly run this function, the FLASH_OB_Unlock() function must be called before.
* @note Call the FLASH_OB_Lock() to disable the flash control register access and the option
* bytes (recommended to protect the FLASH memory against possible unwanted operation)
* @note This functions erases all option bytes except the Read protection (RDP).
* @param None
* @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
@ -585,10 +580,9 @@ FLASH_Status FLASH_OB_Erase(void)
/**
* @brief Write protects the desired pages
* @note To correctly run this function, the FLASH_OB_Unlock() function
* must be called before.
* Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes
* (recommended to protect the FLASH memory against possible unwanted operation)
* @note To correctly run this function, the FLASH_OB_Unlock() function must be called before.
* @note Call the FLASH_OB_Lock() to disable the flash control register access and the option
* bytes (recommended to protect the FLASH memory against possible unwanted operation)
* @param OB_WRP: specifies the address of the pages to be write protected.
* This parameter can be:
* @arg OB_WRP_Pages0to3..OB_WRP_Pages60to63
@ -643,15 +637,15 @@ FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP)
/**
* @brief Enables or disables the read out protection.
* @note To correctly run this function, the FLASH_OB_Unlock() function
* must be called before.
* Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes
* (recommended to protect the FLASH memory against possible unwanted operation)
* @note To correctly run this function, the FLASH_OB_Unlock() function must be called before.
* @note Call the FLASH_OB_Lock() to disable the flash control register access and the option
* bytes (recommended to protect the FLASH memory against possible unwanted operation)
* @param FLASH_ReadProtection_Level: specifies the read protection level.
* This parameter can be:
* @arg OB_RDP_Level_0: No protection
* @arg OB_RDP_Level_1: Read protection of the memory
* @arg OB_RDP_Level_2: Chip protection
* @note When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
* @retval FLASH Status: The returned value can be:
* FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
@ -705,10 +699,9 @@ FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP)
/**
* @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
* @note To correctly run this function, the FLASH_OB_Unlock() function
* must be called before.
* Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes
* (recommended to protect the FLASH memory against possible unwanted operation)
* @note To correctly run this function, the FLASH_OB_Unlock() function must be called before.
* @note Call the FLASH_OB_Lock() to disable the flash control register access and the option
* bytes (recommended to protect the FLASH memory against possible unwanted operation)
* @param OB_IWDG: Selects the WDG mode
* This parameter can be one of the following values:
* @arg OB_IWDG_SW: Software WDG selected
@ -757,11 +750,11 @@ FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_ST
}
/**
* @brief Sets or resets the BOOT1.
* @param OB_BOOT1: Set or Reset the BOOT1.
* @brief Sets or resets the BOOT1 option bit.
* @param OB_BOOT1: Set or Reset the BOOT1 option bit.
* This parameter can be one of the following values:
* @arg OB_BOOT1_RESET: BOOT1 Reset
* @arg OB_BOOT1_SET: BOOT1 Set
* @arg OB_BOOT1_RESET: BOOT1 option bit reset
* @arg OB_BOOT1_SET: BOOT1 option bit set
* @retval None
*/
FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1)
@ -873,10 +866,9 @@ FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity)
/**
* @brief Programs the FLASH User Option Byte: IWDG_SW, RST_STOP, RST_STDBY,
* BOOT1 and VDDA ANALOG monitoring.
* @note To correctly run this function, the FLASH_OB_Unlock() function
* must be called before.
* Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes
* (recommended to protect the FLASH memory against possible unwanted operation)
* @note To correctly run this function, the FLASH_OB_Unlock() function must be called before.
* @note Call the FLASH_OB_Lock() to disable the flash control register access and the option
* bytes (recommended to protect the FLASH memory against possible unwanted operation)
* @param OB_USER: Selects all user option bytes
* This parameter is a combination of the following values:
* @arg OB_IWDG_SW / OB_IWDG_HW: Software / Hardware WDG selected
@ -918,10 +910,9 @@ FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER)
/**
* @brief Programs a half word at a specified Option Byte Data address.
* @note To correctly run this function, the FLASH_OB_Unlock() function
* must be called before.
* Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes
* (recommended to protect the FLASH memory against possible unwanted operation)
* @note To correctly run this function, the FLASH_OB_Unlock() function must be called before.
* @note Call the FLASH_OB_Lock() to disable the flash control register access and the option
* bytes (recommended to protect the FLASH memory against possible unwanted operation)
* @param Address: specifies the address to be programmed.
* This parameter can be 0x1FFFF804 or 0x1FFFF806.
* @param Data: specifies the data to be programmed.

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_gpio.c
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the GPIO peripheral:
* + Initialization and Configuration functions
@ -155,8 +155,8 @@ void GPIO_DeInit(GPIO_TypeDef* GPIOx)
* @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @note The configured pins can be: GPIO_Pin_0 -> GPIO_Pin_15 for GPIOA, GPIOB and GPIOC,
* GPIO_Pin_0 -> GPIO_Pin_2 for GPIOD, GPIO_Pin_0 -> GPIO_Pin_3 for GPIOF.
* @note The configured pins can be: GPIO_Pin_0 to GPIO_Pin_15 for GPIOA, GPIOB and GPIOC,
* GPIO_Pin_0 to GPIO_Pin_2 for GPIOD, GPIO_Pin_0 to GPIO_Pin_3 for GPIOF.
* @retval None
*/
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
@ -226,10 +226,10 @@ void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
/**
* @brief Locks GPIO Pins configuration registers.
* The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
* @note The configuration of the locked GPIO pins can no longer be modified
* until the next reset.
* until the next device reset.
* @param GPIOx: where x can be (A or B) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
@ -418,8 +418,7 @@ void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
/**
* @brief Writes data to the specified GPIO data port.
* @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.
* @param PortVal: specifies the value to be written to the port output data
* register.
* @param PortVal: specifies the value to be written to the port output data register.
* @retval None
*/
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
@ -456,11 +455,11 @@ void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
* @arg GPIO_AF_0: WKUP, EVENTOUT, TIM15, SPI1, TIM17,MCO, SWDAT, SWCLK, TIM14,
* BOOT,USART1, CEC, IR_OUT, SPI2
* @arg GPIO_AF_1: USART2, CEC, Tim3, USART1, USART2,EVENTOUT, I2C1, I2C2, TIM15
* @arg GPIO_AF_2:TIM2, TIM1, EVENTOUT, TIM16, TIM17.
* @arg GPIO_AF_2: TIM2, TIM1, EVENTOUT, TIM16, TIM17
* @arg GPIO_AF_3: TS, I2C1, TIM15, EVENTOUT
* @arg GPIO_AF_4:TIM14.
* @arg GPIO_AF_5:TIM16, TIM17.
* @arg GPIO_AF_6:EVENTOUT.
* @arg GPIO_AF_4: TIM14
* @arg GPIO_AF_5: TIM16, TIM17
* @arg GPIO_AF_6: EVENTOUT
* @arg GPIO_AF_7: COMP1 OUT, COMP2 OUT
* @note The pin should already been configured in Alternate Function mode(AF)
* using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF

View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_i2c.c
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the Inter-Integrated circuit (I2C):
* + Initialization and Configuration
@ -94,6 +94,8 @@
#define CR1_CLEAR_MASK ((uint32_t)0x00CFE0FF) /*<! I2C CR1 clear register Mask */
#define CR2_CLEAR_MASK ((uint32_t)0x07FF7FFF) /*<! I2C CR2 clear register Mask */
#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! I2C TIMING clear register Mask */
#define ERROR_IT_MASK ((uint32_t)0x00003F00) /*<! I2C Error interrupt register Mask */
#define TC_IT_MASK ((uint32_t)0x000000C0) /*<! I2C TC interrupt register Mask */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
@ -1496,18 +1498,36 @@ ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
{
uint32_t tmpreg = 0;
ITStatus bitstatus = RESET;
uint32_t enablestatus = 0;
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
assert_param(IS_I2C_GET_IT(I2C_IT));
/* Check if the interrupt source is enabled or not */
/* If Error interrupt */
if((I2C_IT & ERROR_IT_MASK) != 0)
{
enablestatus = (uint32_t)((I2C_CR1_ERRIE) & (I2Cx->CR1));
}
/* If TC interrupt */
else if((I2C_IT & TC_IT_MASK) != 0)
{
enablestatus = (uint32_t)((I2C_CR1_TCIE) & (I2Cx->CR1));
}
else
{
enablestatus = (uint32_t)((I2C_IT) & (I2Cx->CR1));
}
/* Get the ISR register value */
tmpreg = I2Cx->ISR;
/* Get flag status */
tmpreg &= I2C_IT;
if(tmpreg != 0)
/* Check the status of the specified I2C flag */
if((tmpreg != RESET) && enablestatus)
{
/* I2C_IT is set */
bitstatus = SET;
@ -1517,6 +1537,8 @@ ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
/* I2C_IT is reset */
bitstatus = RESET;
}
/* Return the I2C_IT status */
return bitstatus;
}

View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_iwdg.c
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the Independent watchdog (IWDG) peripheral:
* + Prescaler and Counter configuration
@ -224,8 +224,8 @@ void IWDG_SetWindowValue(uint16_t WindowValue)
/**
* @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
* @param None.
* @retval None.
* @param None
* @retval None
*/
void IWDG_Enable(void)
{

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_misc.c
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file provides all the miscellaneous firmware functions (add-on
* to CMSIS functions).
******************************************************************************

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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_pwr.c
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
* + Backup Domain Access
@ -142,14 +142,17 @@ void PWR_BackupAccessCmd(FunctionalState NewState)
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
* @param PWR_PVDLevel: specifies the PVD detection level
* This parameter can be one of the following values:
* @arg PWR_PVDLevel_0: PVD detection level set to 1.9V
* @arg PWR_PVDLevel_1: PVD detection level set to 2.1V
* @arg PWR_PVDLevel_2: PVD detection level set to 2.3V
* @arg PWR_PVDLevel_3: PVD detection level set to 2.5V
* @arg PWR_PVDLevel_4: PVD detection level set to 2.7V
* @arg PWR_PVDLevel_5: PVD detection level set to 2.9V
* @arg PWR_PVDLevel_6: PVD detection level set to 3.1V
* @arg PWR_PVDLevel_7: PVD detection level set to 3.3V
* @arg PWR_PVDLevel_0
* @arg PWR_PVDLevel_1
* @arg PWR_PVDLevel_2
* @arg PWR_PVDLevel_3
* @arg PWR_PVDLevel_4
* @arg PWR_PVDLevel_5
* @arg PWR_PVDLevel_6
* @arg PWR_PVDLevel_7
* @note Refer to the electrical characteristics of your device datasheet for
* more details about the voltage threshold corresponding to each
* detection level.
* @retval None
*/
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
@ -435,10 +438,10 @@ void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
/**
* @brief Enters STANDBY mode.
* @note In Standby mode, all I/O pins are high impedance except for:
* Reset pad (still available)
* RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper,
* - Reset pad (still available)
* - RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper,
* time-stamp, RTC Alarm out, or RTC clock calibration out.
* WKUP pin 1 (PA0) if enabled.
* - WKUP pin 1 (PA0) if enabled.
* @param None
* @retval None
*/

View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_rcc.c
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the Reset and clock control (RCC) peripheral:
* + Internal/external clocks, PLL, CSS and MCO configuration
@ -213,7 +213,7 @@ void RCC_HSEConfig(uint8_t RCC_HSE)
* and this flag is not set. The timeout value is defined by the constant
* HSE_STARTUP_TIMEOUT in stm32f0xx.h file. You can tailor it depending
* on the HSE crystal used in your application.
* - The HSE is stopped by hardware when entering STOP and STANDBY modes.
* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
* @param None
* @retval An ErrorStatus enumeration value:
* - SUCCESS: HSE oscillator is stable and ready to use
@ -247,7 +247,7 @@ ErrorStatus RCC_WaitForHSEStartUp(void)
* @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
* @note The calibration is used to compensate for the variations in voltage
* and temperature that influence the frequency of the internal HSI RC.
* Refer to the Application Note AN3300 for more details on how to
* Refer to the Application Note AN4067 for more details on how to
* calibrate the HSI.
* @param HSICalibrationValue: specifies the HSI calibration trimming value.
* This parameter must be a number between 0 and 0x1F.
@ -307,7 +307,7 @@ void RCC_HSICmd(FunctionalState NewState)
* calibration value.
* @note The calibration is used to compensate for the variations in voltage
* and temperature that influence the frequency of the internal HSI RC.
* Refer to the Application Note AN3300 for more details on how to
* Refer to the Application Note AN4067 for more details on how to
* calibrate the HSI14.
* @param HSI14CalibrationValue: specifies the HSI14 calibration trimming value.
* This parameter must be a number between 0 and 0x1F.
@ -493,11 +493,11 @@ void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
/**
* @brief Enables or disables the PLL.
* @note - After enabling the PLL, the application software should wait on
* @note After enabling the PLL, the application software should wait on
* PLLRDY flag to be set indicating that PLL clock is stable and can
* be used as system clock source.
* - The PLL can not be disabled if it is used as system clock source
* - The PLL is disabled by hardware when entering STOP and STANDBY modes.
* @note The PLL can not be disabled if it is used as system clock source
* @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
* @param NewState: new state of the PLL.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -886,16 +886,16 @@ void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK)
* @note If SYSCLK source is PLL, function returns constant HSE_VALUE(**)
* or HSI_VALUE(*) multiplied by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value
* @note (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value
* 8 MHz) but the real value may vary depending on the variations
* in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().
*
* (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value
* @note (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* return wrong result.
*
* - The result of this function could be not correct when using fractional
* @note The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
@ -1027,10 +1027,8 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
/* USART1 Clock is HSI Osc. */
RCC_Clocks->USART1CLK_Frequency = HSI_VALUE;
}
}
/**
* @}
*/

View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_rtc.c
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the Real-Time Clock (RTC) peripheral:
* + Initialization
@ -241,8 +241,8 @@
#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_ALRAF | \
RTC_FLAG_RSF | RTC_FLAG_INITS |RTC_FLAG_INITF | \
RTC_FLAG_TAMP1F | RTC_FLAG_TAMP2F | RTC_FLAG_TAMP3F | \
RTC_FLAG_RECALPF | RTC_FLAG_SHPF))
RTC_FLAG_TAMP1F | RTC_FLAG_TAMP2F | RTC_FLAG_RECALPF | \
RTC_FLAG_SHPF))
#define INITMODE_TIMEOUT ((uint32_t) 0x00004000)
#define SYNCHRO_TIMEOUT ((uint32_t) 0x00008000)
@ -1301,8 +1301,7 @@ ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState)
* Only SS[12:0] are compared
* @arg RTC_AlarmSubSecondMask_SS14: SS[14] is don't care in Alarm comparison.
* Only SS[13:0] are compared
* @arg RTC_AlarmSubSecondMask_None: SS[14:0] are compared and must match
* to activate alarm
* @arg RTC_AlarmSubSecondMask_None: SS[14:0] are compared and must match to activate alarm
* @retval None
*/
void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint8_t RTC_AlarmSubSecondMask)
@ -1375,8 +1374,8 @@ uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)
* @param RTC_StoreOperation: Specifies the value to be written in the BCK bit
* in CR register to store the operation.
* This parameter can be one of the following values:
* @arg RTC_StoreOperation_Reset
* @arg RTC_StoreOperation_Set
* @arg RTC_StoreOperation_Reset: BCK Bit Reset
* @arg RTC_StoreOperation_Set: BCK Bit Set
* @retval None
*/
void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
@ -1479,8 +1478,7 @@ void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
*/
/**
* @brief Enables or disables the RTC clock to be output through the relative
* pin.
* @brief Enables or disables the RTC clock to be output through the relative pin.
* @param NewState: new state of the digital calibration Output.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -1745,7 +1743,6 @@ uint32_t RTC_GetTimeStampSubSecond(void)
* This parameter can be any combination of the following values:
* @arg RTC_Tamper_1: Select Tamper 1.
* @arg RTC_Tamper_2: Select Tamper 2.
* @arg RTC_Tamper_3: Select Tamper 3.
* @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that
* stimulates tamper event.
* This parameter can be one of the following values:
@ -1779,7 +1776,6 @@ void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
* This parameter can be any combination of the following values:
* @arg RTC_Tamper_1: Select Tamper 1.
* @arg RTC_Tamper_2: Select Tamper 2.
* @arg RTC_Tamper_3: Select Tamper 3.
* @param NewState: new state of the tamper pin.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -2197,7 +2193,6 @@ void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)
* @param RTC_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg RTC_FLAG_RECALPF: RECALPF event flag
* @arg RTC_FLAG_TAMP3F: Tamper 3 event flag
* @arg RTC_FLAG_TAMP2F: Tamper 2 event flag
* @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
* @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag
@ -2235,7 +2230,6 @@ FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)
* @brief Clears the RTC's pending flags.
* @param RTC_FLAG: specifies the RTC flag to clear.
* This parameter can be any combination of the following values:
* @arg RTC_FLAG_TAMP3F: Tamper 3 event flag
* @arg RTC_FLAG_TAMP2F: Tamper 2 event flag
* @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
* @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag
@ -2261,7 +2255,6 @@ void RTC_ClearFlag(uint32_t RTC_FLAG)
* @arg RTC_IT_ALRA: Alarm A interrupt
* @arg RTC_IT_TAMP1: Tamper1 event interrupt
* @arg RTC_IT_TAMP2: Tamper2 event interrupt
* @arg RTC_IT_TAMP3: Tamper3 event interrupt
* @retval The new state of RTC_IT (SET or RESET).
*/
ITStatus RTC_GetITStatus(uint32_t RTC_IT)
@ -2301,7 +2294,6 @@ ITStatus RTC_GetITStatus(uint32_t RTC_IT)
* @arg RTC_IT_ALRA: Alarm A interrupt
* @arg RTC_IT_TAMP1: Tamper1 event interrupt
* @arg RTC_IT_TAMP2: Tamper2 event interrupt
* @arg RTC_IT_TAMP3: Tamper3 event interrupt
* @retval None
*/
void RTC_ClearITPendingBit(uint32_t RTC_IT)

View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_spi.c
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the Serial peripheral interface (SPI):
* + Initialization and Configuration
@ -316,12 +316,11 @@ void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
/**
* @brief Initializes the SPIx peripheral according to the specified
* parameters in the I2S_InitStruct.
* @param SPIx: where x can be 1 to select the SPI peripheral.
* @param SPIx: where x can be 1 to select the SPI peripheral (configured in I2S mode).
* @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
* contains the configuration information for the specified SPI peripheral
* configured in I2S mode.
* @note
* The function calculates the optimal prescaler needed to obtain the most
* @note This function calculates the optimal prescaler needed to obtain the most
* accurate audio frequency (depending on the I2S clock source, the PLL values
* and the product configuration). But in case the prescaler value is greater
* than 511, the default value (0x02) will be configured instead.
@ -450,11 +449,13 @@ void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
/**
* @brief Enables or disables the TI Mode.
*
* @note This function can be called only after the SPI_Init() function has
* been called.
* @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA
* are not taken into consideration and are configured by hardware
* respectively to the TI mode requirements.
*
* @param SPIx: where x can be 1 to select the SPI peripheral.
* @param NewState: new state of the selected SPI TI communication mode.
* This parameter can be: ENABLE or DISABLE.
@ -590,7 +591,7 @@ void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
/**
* @brief Configures internally by software the NSS pin for the selected SPI.
* @note - This function can be called only after the SPI_Init() function has
* @note This function can be called only after the SPI_Init() function has
* been called.
* @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
* @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
@ -619,7 +620,7 @@ void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSo
/**
* @brief Enables or disables the SS output for the selected SPI.
* @note - This function can be called only after the SPI_Init() function has
* @note This function can be called only after the SPI_Init() function has
* been called and the NSS hardware management mode is selected.
* @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
* @param NewState: new state of the SPIx SS output.
@ -830,7 +831,7 @@ uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx)
/**
* @brief Configures the CRC calculation length for the selected SPI.
* @note - This function can be called only after the SPI_Init() function has
* @note This function can be called only after the SPI_Init() function has
* been called.
* @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
* @param SPI_CRCLength: specifies the SPI CRC calculation length.
@ -854,7 +855,7 @@ void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength)
/**
* @brief Enables or disables the CRC value calculation of the transferred bytes.
* @note - This function can be called only after the SPI_Init() function has
* @note This function can be called only after the SPI_Init() function has
* been called.
* @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
* @param NewState: new state of the SPIx CRC value calculation.
@ -988,7 +989,7 @@ void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState
/**
* @brief Configures the number of data to transfer type(Even/Odd) for the DMA
* last transfers and for the selected SPI.
* @note - This function have a meaning only if DMA mode is selected and if
* @note This function have a meaning only if DMA mode is selected and if
* the packing mode is used (data length <= 8 and DMA transfer size halfword)
* @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
* @param SPI_LastDMATransfer: specifies the SPI last DMA transfers state.
@ -1175,8 +1176,8 @@ uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx)
* @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
* @arg SPI_I2S_FLAG_BSY: Busy flag.
* @arg SPI_I2S_FLAG_OVR: Overrun flag.
* @arg SPI_I2S_FLAG_MODF: Mode Fault flag.
* @arg SPI_I2S_FLAG_CRCERR: CRC Error flag.
* @arg SPI_FLAG_MODF: Mode Fault flag.
* @arg SPI_FLAG_CRCERR: CRC Error flag.
* @arg SPI_I2S_FLAG_FRE: TI frame format error flag.
* @arg I2S_FLAG_UDR: Underrun Error flag.
* @arg I2S_FLAG_CHSIDE: Channel Side flag.

View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_syscfg.c
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the SYSCFG peripheral:
* + Remapping the memory mapped at 0x00000000
@ -84,10 +84,10 @@
* @param None
* @retval None
* @note MEM_MODE bits are not affected by APB reset.
* MEM_MODE bits took the value from the user option bytes.
* @note MEM_MODE bits took the value from the user option bytes.
* @note CFGR2 register is not affected by APB reset.
* CLABBB configuration bits are locked when set.
* To unlock the configuration, perform a system reset.
* @note CLABBB configuration bits are locked when set.
* @note To unlock the configuration, perform a system reset.
*/
void SYSCFG_DeInit(void)
{
@ -144,12 +144,11 @@ void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)
* This parameter can be: ENABLE or DISABLE.
* @note When enabled, DMA channel of the selected peripheral is remapped
* @note When disabled, Default DMA channel is mapped to the selected peripheral
* @note
* By default TIM17 DMA requests is mapped to channel 1
* use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable)
* to remap TIM17 DMA requests to channel 2
* use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable)
* to map TIM17 DMA requests to channel 1 (default mapping)
* @note By default TIM17 DMA requests is mapped to channel 1,
* use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable) to remap
* TIM17 DMA requests to channel 2 and use
* SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable) to map
* TIM17 DMA requests to channel 1 (default mapping)
* @retval None
*/
void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState)

View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_tim.c
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the TIM peripheral:
* + TimeBase management
@ -295,8 +295,8 @@ void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseIn
/**
* @brief Fills each TIM_TimeBaseInitStruct member with its default value.
* @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
* structure which will be initialized.
* @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure
* which will be initialized.
* @retval None
*/
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
@ -453,9 +453,9 @@ void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
* peripheral.
* @param TIM_UpdateSource: specifies the Update source.
* This parameter can be one of the following values:
* @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
or the setting of UG bit, or an update generation
through the slave mode controller.
* @arg TIM_UpdateSource_Regular: Source of update is the counter
* overflow/underflow or the setting of UG bit, or an update
* generation through the slave mode controller.
* @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
* @retval None
*/
@ -606,8 +606,8 @@ void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
* @{
*/
/**
* @brief Configures the: Break feature, dead time, Lock level, the OSSI,
* the OSSR State and the AOE(automatic output enable).
* @brief Configures the: Break feature, dead time, Lock level, OSSI/OSSR State
* and the AOE(automatic output enable).
* @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM
* @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
* contains the BDTR Register configuration information for the TIM peripheral.
@ -1196,8 +1196,7 @@ void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
/**
* @brief Forces the TIMx output 2 waveform to active or inactive level.
* @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM
* peripheral.
* @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
* This parameter can be one of the following values:
* @arg TIM_ForcedAction_Active: Force active level on OC2REF
@ -1274,8 +1273,7 @@ void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
/**
* @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
* @param TIMx: where x can be 1, 2, 3 or 15
* to select the TIMx peripheral
* @param TIMx: where x can be 1, 2, 3 or 15 to select the TIMx peripheral
* @param NewState: new state of the Capture Compare Preload Control bit
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -1538,7 +1536,6 @@ void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
* @brief Clears or safeguards the OCREF2 signal on an external event
* @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
* This parameter can be one of the following values:
* @arg TIM_OCClear_Enable: TIM Output clear enable
* @arg TIM_OCClear_Disable: TIM Output clear disable
@ -1761,7 +1758,6 @@ void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
TIMx->CCER = tmpccer;
}
/**
* @brief Configures the TIMx channel 4 polarity.
* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
@ -2254,13 +2250,13 @@ void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
* @arg TIM_IT_COM: TIM Commutation Interrupt source
* @arg TIM_IT_Trigger: TIM Trigger Interrupt source
* @arg TIM_IT_Break: TIM Break Interrupt source
* @note
* - TIM6 can only generate an update interrupt.
* - TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
* TIM_IT_CC2 or TIM_IT_Trigger.
* - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
* - TIM_IT_Break is used only with TIM1 and TIM15.
* - TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17.
*
* @note TIM6 can only generate an update interrupt.
* @note TIM15 can have only TIM_IT_Update, TIM_IT_CC1,TIM_IT_CC2 or TIM_IT_Trigger.
* @note TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
* @note TIM_IT_Break is used only with TIM1 and TIM15.
* @note TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17.
*
* @param NewState: new state of the TIM interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@ -2298,11 +2294,12 @@ void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
* @arg TIM_EventSource_COM: Timer COM event source
* @arg TIM_EventSource_Trigger: Timer Trigger Event source
* @arg TIM_EventSource_Break: Timer Break event source
* @note
* - TIM6 can only generate an update event.
* - TIM9 can only generate an update event, Capture Compare 1 event,
*
* @note TIM6 can only generate an update event.
* @note TIM9 can only generate an update event, Capture Compare 1 event,
* Capture Compare 2 event and TIM_EventSource_Trigger.
* - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1.
* @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1.
*
* @retval None
*/
void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
@ -2331,13 +2328,13 @@ void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
* @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
* @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
* @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
* @note
* - TIM6 can have only one update flag.
* - TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, TIM_FLAG_CC2 or
* TIM_FLAG_Trigger.
* - TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
* - TIM_FLAG_Break is used only with TIM1 and TIM15.
* - TIM_FLAG_COM is used only with TIM1 TIM15, TIM16 and TIM17.
*
* @note TIM6 can have only one update flag.
* @note TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, TIM_FLAG_CC2 or TIM_FLAG_Trigger.
* @note TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
* @note TIM_FLAG_Break is used only with TIM1 and TIM15.
* @note TIM_FLAG_COM is used only with TIM1 TIM15, TIM16 and TIM17.
*
* @retval The new state of TIM_FLAG (SET or RESET).
*/
FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
@ -2376,13 +2373,14 @@ FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
* @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
* @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
* @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
* @note
* - TIM6 can have only one update flag.
* - TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,TIM_FLAG_CC2 or
*
* @note TIM6 can have only one update flag.
* @note TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,TIM_FLAG_CC2 or
* TIM_FLAG_Trigger.
* - TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
* - TIM_FLAG_Break is used only with TIM1 and TIM15.
* - TIM_FLAG_COM is used only with TIM1, TIM15, TIM16 and TIM17.
* @note TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
* @note TIM_FLAG_Break is used only with TIM1 and TIM15.
* @note TIM_FLAG_COM is used only with TIM1, TIM15, TIM16 and TIM17.
*
* @retval None
*/
void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
@ -2408,12 +2406,13 @@ void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
* @arg TIM_IT_COM: TIM Commutation Interrupt source
* @arg TIM_IT_Trigger: TIM Trigger Interrupt source
* @arg TIM_IT_Break: TIM Break Interrupt source
* @note
* - TIM6 can generate only an update interrupt.
* - TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
* - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
* - TIM_IT_Break is used only with TIM1 and TIM15.
* - TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17.
*
* @note TIM6 can generate only an update interrupt.
* @note TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
* @note TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
* @note TIM_IT_Break is used only with TIM1 and TIM15.
* @note TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17.
*
* @retval The new state of the TIM_IT(SET or RESET).
*/
ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
@ -2452,12 +2451,13 @@ ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
* @arg TIM_IT_COM: TIM Commutation Interrupt source
* @arg TIM_IT_Trigger: TIM Trigger Interrupt source
* @arg TIM_IT_Break: TIM Break Interrupt source
* @note
* - TIM6 can generate only an update interrupt.
* - TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
* - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
* - TIM_IT_Break is used only with TIM1 and TIM15.
* - TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17.
*
* @note TIM6 can generate only an update interrupt.
* @note TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
* @note TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
* @note TIM_IT_Break is used only with TIM1 and TIM15.
* @note TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17.
*
* @retval None
*/
void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
@ -2475,15 +2475,26 @@ void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
* @param TIMx: where x can be 1, 2, 3, 15, 16 or 17 to select the TIM peripheral.
* @param TIM_DMABase: DMA Base address.
* This parameter can be one of the following values:
* @arg TIM_DMABase_CR1, TIM_DMABase_CR2, TIM_DMABase_SMCR,
* TIM_DMABase_DIER, TIM_DMABase_SR, TIM_DMABase_EGR,
* TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
* TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
* TIM_DMABase_CCR1, TIM_DMABase_CCR2, TIM_DMABase_CCR3,
* TIM_DMABase_CCR4, TIM_DMABase_DCR, TIM_DMABase_OR.
* @param TIM_DMABurstLength: DMA Burst length.
* This parameter can be one value between:
* TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
* @arg TIM_DMABase_CR1
* @arg TIM_DMABase_CR2
* @arg TIM_DMABase_SMCR
* @arg TIM_DMABase_DIER
* @arg TIM_DMABase_SR
* @arg TIM_DMABase_EGR
* @arg TIM_DMABase_CCMR1
* @arg TIM_DMABase_CCMR2
* @arg TIM_DMABase_CCER
* @arg TIM_DMABase_CNT
* @arg TIM_DMABase_PSC
* @arg TIM_DMABase_ARR
* @arg TIM_DMABase_CCR1
* @arg TIM_DMABase_CCR2
* @arg TIM_DMABase_CCR3
* @arg TIM_DMABase_CCR4
* @arg TIM_DMABase_DCR
* @arg TIM_DMABase_OR
* @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value
* between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
* @retval None
*/
void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
@ -2794,14 +2805,14 @@ void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
* @brief Selects the TIMx Trigger Output Mode.
* @param TIMx: where x can be 1, 2, 3, 6, or 15 to select the TIM peripheral.
* @param TIM_TRGOSource: specifies the Trigger Output source.
* This paramter can be one of the following values:
* This parameter can be one of the following values:
*
* For all TIMx
* - For all TIMx
* @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
* @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
* @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
*
* For all TIMx except TIM6
* - For all TIMx except TIM6
* @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
* is to be set, as soon as a capture or compare match occurs (TRGO).
* @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
@ -2827,7 +2838,7 @@ void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
* @brief Selects the TIMx Slave Mode.
* @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
* @param TIM_SlaveMode: specifies the Timer Slave Mode.
* This paramter can be one of the following values:
* This parameter can be one of the following values:
* @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
* the counter and triggers an update of the registers.
* @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
@ -2851,7 +2862,7 @@ void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
* @brief Sets or Resets the TIMx Master/Slave Mode.
* @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
* @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
* This paramter can be one of the following values:
* This parameter can be one of the following values:
* @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
* and its slaves (through TRGO).
* @arg TIM_MasterSlaveMode_Disable: No action
@ -2968,7 +2979,6 @@ void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
/* Set the TI1 and the TI2 Polarities */
//tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));
tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)) & (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
/* Write to TIMx SMCR */
@ -3030,7 +3040,7 @@ void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
* @arg TIM14_HSE_DIV32: TIM14 Channel 1 is connected to HSE/32 clock.
* @arg TIM14_MCO: TIM14 Channel 1 is connected to MCO clock.
* MCO clock can be HSI14, SYSCLK, HSI, HSE or PLL/2.
* @retval : None
* @retval None
*/
void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
{

View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_usart.c
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the Universal synchronous asynchronous receiver
* transmitter (USART):
@ -193,15 +193,13 @@ void USART_DeInit(USART_TypeDef* USARTx)
* @brief Initializes the USARTx peripheral according to the specified
* parameters in the USART_InitStruct .
* @param USARTx: where x can be 1 or 2 to select the USART peripheral.
* @param USART_InitStruct: pointer to a USART_InitTypeDef structure
* that contains the configuration information for the specified USART peripheral.
* @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains
* the configuration information for the specified USART peripheral.
* @retval None
*/
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
{
uint32_t tmpreg = 0, apbclock = 0;
uint32_t integerdivider = 0;
uint32_t fractionaldivider = 0;
uint32_t divider = 0, apbclock = 0, tmpreg = 0;
RCC_ClocksTypeDef RCC_ClocksStatus;
/* Check the parameters */
@ -267,34 +265,39 @@ void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
{
apbclock = RCC_ClocksStatus.PCLK_Frequency;
}
/* Determine the integer part */
if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
{
/* Integer part computing in case Oversampling mode is 8 Samples */
integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));
/* (divider * 10) computing in case Oversampling mode is 8 Samples */
divider = (uint32_t)((2 * apbclock) / (USART_InitStruct->USART_BaudRate));
tmpreg = (uint32_t)((2 * apbclock) % (USART_InitStruct->USART_BaudRate));
}
else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
{
/* Integer part computing in case Oversampling mode is 16 Samples */
integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
/* (divider * 10) computing in case Oversampling mode is 16 Samples */
divider = (uint32_t)((apbclock) / (USART_InitStruct->USART_BaudRate));
tmpreg = (uint32_t)((apbclock) % (USART_InitStruct->USART_BaudRate));
}
tmpreg = (integerdivider / 100) << 4;
/* Determine the fractional part */
fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
/* round the divider : if fractional part i greater than 0.5 increment divider */
if (tmpreg >= (USART_InitStruct->USART_BaudRate) / 2)
{
divider++;
}
/* Implement the fractional part in the register */
/* Implement the divider in case Oversampling mode is 8 Samples */
if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
{
tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
}
else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
{
tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
/* get the LSB of divider and shift it to the right by 1 bit */
tmpreg = (divider & (uint16_t)0x000F) >> 1;
/* update the divider value */
divider = (divider & (uint16_t)0xFFF0) | tmpreg;
}
/* Write to USART BRR */
USARTx->BRR = (uint16_t)tmpreg;
USARTx->BRR = (uint16_t)divider;
}
/**
@ -424,9 +427,8 @@ void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode,
* @param USARTx: where x can be 1 or 2 to select the USART peripheral.
* @param NewState: new state of the USART 8x oversampling mode.
* This parameter can be: ENABLE or DISABLE.
* @note
* This function has to be called before calling USART_Init()
* function in order to have correct baudrate Divider value.
* @note This function has to be called before calling USART_Init() function
* in order to have correct baudrate Divider value.
* @retval None
*/
void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
@ -452,8 +454,7 @@ void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
* @param USARTx: where x can be 1 or 2 to select the USART peripheral.
* @param NewState: new state of the USART one bit sampling method.
* This parameter can be: ENABLE or DISABLE.
* @note
* This function has to be called before calling USART_Cmd() function.
* @note This function has to be called before calling USART_Cmd() function.
* @retval None
*/
void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
@ -481,8 +482,7 @@ void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
* @param NewState: new state of the USART most significant bit first
* transmitted/received following the start bit.
* This parameter can be: ENABLE or DISABLE.
* @note
* This function has to be called before calling USART_Cmd() function.
* @note This function has to be called before calling USART_Cmd() function.
* @retval None
*/
void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState)
@ -509,13 +509,12 @@ void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState)
* @brief Enables or disables the binary data inversion.
* @param USARTx: where x can be 1 or 2 to select the USART peripheral.
* @param NewState: new defined levels for the USART data.
* This parameter can be: ENABLE or DISABLE.
* - ENABLE: Logical data from the data register are send/received in negative
* logic. (1=L, 0=H). The parity bit is also inverted.
* - DISABLE: Logical data from the data register are send/received in positive
* logic. (1=H, 0=L)
* @note
* This function has to be called before calling USART_Cmd() function.
* This parameter can be:
* @arg ENABLE: Logical data from the data register are send/received in negative
* logic (1=L, 0=H). The parity bit is also inverted.
* @arg DISABLE: Logical data from the data register are send/received in positive
* logic (1=H, 0=L)
* @note This function has to be called before calling USART_Cmd() function.
* @retval None
*/
void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState)
@ -546,11 +545,10 @@ void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState)
* @arg USART_InvPin_Tx: USART Tx pin active level inversion.
* @arg USART_InvPin_Rx: USART Rx pin active level inversion.
* @param NewState: new active level status for the USART pin(s).
* This parameter can be: ENABLE or DISABLE.
* - ENABLE: pin(s) signal values are inverted (Vdd =0, Gnd =1).
* - DISABLE: pin(s) signal works using the standard logic levels (Vdd =1, Gnd =0).
* @note
* This function has to be called before calling USART_Cmd() function.
* This parameter can be:
* @arg ENABLE: pin(s) signal values are inverted (Vdd =0, Gnd =1).
* @arg DISABLE: pin(s) signal works using the standard logic levels (Vdd =1, Gnd =0).
* @note This function has to be called before calling USART_Cmd() function.
* @retval None
*/
void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState)
@ -578,11 +576,10 @@ void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalSta
* @brief Enables or disables the swap Tx/Rx pins.
* @param USARTx: where x can be 1 or 2 to select the USART peripheral.
* @param NewState: new state of the USARTx TX/RX pins pinout.
* This parameter can be: ENABLE or DISABLE.
* - ENABLE: The TX and RX pins functions are swapped.
* - DISABLE: TX/RX pins are used as defined in standard pinout
* @note
* This function has to be called before calling USART_Cmd() function.
* This parameter can be:
* @arg ENABLE: The TX and RX pins functions are swapped.
* @arg DISABLE: TX/RX pins are used as defined in standard pinout
* @note This function has to be called before calling USART_Cmd() function.
* @retval None
*/
void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState)
@ -654,8 +651,7 @@ void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTime
* @brief Sets the system clock prescaler.
* @param USARTx: where x can be 1 to select the USART peripheral.
* @param USART_Prescaler: specifies the prescaler clock.
* @note
* This function has to be called before calling USART_Cmd() function.
* @note This function has to be called before calling USART_Cmd() function.
* @retval None
*/
void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
@ -702,8 +698,7 @@ void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
* @param USARTx: where x can be 1 to select the USART peripheral.
* @param NewState: new state of the USARTx peripheral state in stop mode.
* This parameter can be: ENABLE or DISABLE.
* @note
* This function has to be called when USART clock is set to HSI or LSE.
* @note This function has to be called when USART clock is set to HSI or LSE.
* @retval None
*/
void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState)
@ -734,8 +729,7 @@ void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState)
* @arg USART_WakeUpSource_AddressMatch: WUF active on address match.
* @arg USART_WakeUpSource_StartBit: WUF active on Start bit detection.
* @arg USART_WakeUpSource_RXNE: WUF active on RXNE.
* @note
* This function has to be called before calling USART_Cmd() function.
* @note This function has to be called before calling USART_Cmd() function.
* @retval None
*/
void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource)
@ -770,7 +764,7 @@ void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_Wake
(#)USART_AutoBaudRate_FallingEdge : any character starting with a 10xx bit pattern.
[..] At any later time, another request for AutoBaudRate detection can be performed
using USART_AutoBaudRateNewRequest() function.
using USART_RequestCmd() function.
[..] The AutoBaudRate detection is monitored by the status of ABRF flag which indicate
that the AutoBaudRate detection is completed. In addition to ABRF flag, the ABRE flag
@ -815,8 +809,7 @@ void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState)
* This parameter can be one of the following values:
* @arg USART_AutoBaudRate_StartBit: Start Bit duration measurement.
* @arg USART_AutoBaudRate_FallingEdge: Falling edge to falling edge measurement.
* @note
* This function has to be called before calling USART_Cmd() function.
* @note This function has to be called before calling USART_Cmd() function.
* @retval None
*/
void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate)
@ -829,19 +822,6 @@ void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate
USARTx->CR2 |= USART_AutoBaudRate;
}
/**
* @brief Requests a new AutoBaudRate detection.
* @param USARTx: where x can be 1 to select the USART peripheral.
* @retval None
*/
void USART_AutoBaudRateNewRequest(USART_TypeDef* USARTx)
{
/* Check the parameters */
assert_param(IS_USART_ALL_PERIPH(USARTx));
USARTx->ISR &= (uint32_t)~((uint32_t)USART_FLAG_ABRF);
}
/**
* @}
*/
@ -1475,8 +1455,8 @@ void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity)
/**
* @brief Sets the specified RS485 DE assertion time
* @param USARTx: where x can be 1 or 2 to select the USART peripheral.
* @param USART_AssertionTime: specifies the time between the activation of the DE
* signal and the beginning of the start bit
* @param USART_DEAssertionTime: specifies the time between the activation of
* the DE signal and the beginning of the start bit
* @retval None
*/
void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime)
@ -1611,15 +1591,15 @@ void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnEr
acknowledge flag
(#) USART_FLAG_TEACK: to indicate the status of the Transmit Enable
acknowledge flag.
(#) USART_FLAG_WUF: to indicate the status of the Wake up flag.
(#) USART_FLAG_WU: to indicate the status of the Wake up flag.
(#) USART_FLAG_RWU: to indicate the status of the Receive Wake up flag.
(#) USART_FLAG_SBK: to indicate the status of the Send Break flag.
(#) USART_FLAG_CMF: to indicate the status of the Character match flag.
(#) USART_FLAG_CM: to indicate the status of the Character match flag.
(#) USART_FLAG_BUSY: to indicate the status of the Busy flag.
(#) USART_FLAG_ABRF: to indicate the status of the Auto baud rate flag.
(#) USART_FLAG_ABRE: to indicate the status of the Auto baud rate error flag.
(#) USART_FLAG_EOBF: to indicate the status of the End of block flag.
(#) USART_FLAG_RTOF: to indicate the status of the Receive time out flag.
(#) USART_FLAG_EOB: to indicate the status of the End of block flag.
(#) USART_FLAG_RTO: to indicate the status of the Receive time out flag.
(#) USART_FLAG_nCTSS: to indicate the status of the Inverted nCTS input
bit status.
(#) USART_FLAG_TXE: to indicate the status of the transmit buffer register.
@ -1787,10 +1767,10 @@ void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalS
* @param USARTx: where x can be 1 or 2 to select the USART peripheral.
* @param USART_OVRDetection: specifies the OVR detection status in case of OVR error.
* This parameter can be any combination of the following values:
* @arg USART_OVRDetection_Enable: OVR error detection enabled when the USART OVR error
* is asserted.
* @arg USART_OVRDetection_Disable: OVR error detection disabled when the USART OVR error
* is asserted.
* @arg USART_OVRDetection_Enable: OVR error detection enabled when
* the USART OVR error is asserted.
* @arg USART_OVRDetection_Disable: OVR error detection disabled when
* the USART OVR error is asserted.
* @retval None
*/
void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection)
@ -1812,15 +1792,15 @@ void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetec
* This parameter can be one of the following values:
* @arg USART_FLAG_REACK: Receive Enable acknowledge flag.
* @arg USART_FLAG_TEACK: Transmit Enable acknowledge flag.
* @arg USART_FLAG_WUF: Wake up flag.
* @arg USART_FLAG_WU: Wake up flag.
* @arg USART_FLAG_RWU: Receive Wake up flag.
* @arg USART_FLAG_SBK: Send Break flag.
* @arg USART_FLAG_CMF: Character match flag.
* @arg USART_FLAG_CM: Character match flag.
* @arg USART_FLAG_BUSY: Busy flag.
* @arg USART_FLAG_ABRF: Auto baud rate flag.
* @arg USART_FLAG_ABRE: Auto baud rate error flag.
* @arg USART_FLAG_EOBF: End of block flag.
* @arg USART_FLAG_RTOF: Receive time out flag.
* @arg USART_FLAG_EOB: End of block flag.
* @arg USART_FLAG_RTO: Receive time out flag.
* @arg USART_FLAG_nCTSS: Inverted nCTS input bit status.
* @arg USART_FLAG_CTS: CTS Change flag.
* @arg USART_FLAG_LBD: LIN Break detection flag.
@ -1857,10 +1837,10 @@ FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG)
* @param USARTx: where x can be 1 or 2 to select the USART peripheral.
* @param USART_FLAG: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg USART_FLAG_WUF: Wake up flag.
* @arg USART_FLAG_CMF: Character match flag.
* @arg USART_FLAG_EOBF: End of block flag.
* @arg USART_FLAG_RTOF: Receive time out flag.
* @arg USART_FLAG_WU: Wake up flag.
* @arg USART_FLAG_CM: Character match flag.
* @arg USART_FLAG_EOB: End of block flag.
* @arg USART_FLAG_RTO: Receive time out flag.
* @arg USART_FLAG_CTS: CTS Change flag.
* @arg USART_FLAG_LBD: LIN Break detection flag.
* @arg USART_FLAG_TC: Transmission Complete flag.

View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx_wwdg.c
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief This file provides firmware functions to manage the following
* functionalities of the Window watchdog (WWDG) peripheral:
* + Prescaler, Refresh window and Counter configuration
@ -195,8 +195,8 @@ void WWDG_EnableIT(void)
/**
* @brief Sets the WWDG counter value.
* @param Counter: specifies the watchdog counter value.
* This parameter must be a number between 0x40 and 0x7F (to prevent generating
* an immediate reset).
* This parameter must be a number between 0x40 and 0x7F (to prevent
* generating an immediate reset).
* @retval None
*/
void WWDG_SetCounter(uint8_t Counter)
@ -227,8 +227,8 @@ void WWDG_SetCounter(uint8_t Counter)
/**
* @brief Enables WWDG and load the counter value.
* @param Counter: specifies the watchdog counter value.
* This parameter must be a number between 0x40 and 0x7F (to prevent generating
* an immediate reset).
* This parameter must be a number between 0x40 and 0x7F (to prevent
* generating an immediate reset).
* @retval None
*/
void WWDG_Enable(uint8_t Counter)

View File

@ -6,6 +6,9 @@ SRCS = main.c system_stm32f0xx.c
PROJ_NAME=main
# location of OpenOCD Board .cfg files (only used with 'make program')
OPENOCD_BOARD_DIR=/usr/share/openocd/scripts/board
# that's it, no need to change anything below this line!
###################################################
@ -13,20 +16,20 @@ PROJ_NAME=main
CC=arm-none-eabi-gcc
OBJCOPY=arm-none-eabi-objcopy
CFLAGS = -g -O2 -Wall -Tstm32_flash.ld
CFLAGS = -g -O2 -Wall -TDevice/stm32_flash.ld
CFLAGS += -mlittle-endian -mthumb -mcpu=cortex-m0 -march=armv6s-m
###################################################
vpath %.c src
vpath %.a lib
vpath %.a Libraries
ROOT=$(shell pwd)
CFLAGS += -Iinc -Ilib -Ilib/inc
CFLAGS += -Ilib/inc/core -Ilib/inc/peripherals
CFLAGS += -Iinc -IDevice -ILibraries/CMSIS/Device/ST/STM32F0xx/Include
CFLAGS += -ILibraries/CMSIS/Include -ILibraries/STM32F0xx_StdPeriph_Driver/inc
SRCS += lib/startup_stm32f0xx.s # add startup file to build
SRCS += Device/startup_stm32f0xx.s # add startup file to build
OBJS = $(SRCS:.c=.o)
@ -37,15 +40,18 @@ OBJS = $(SRCS:.c=.o)
all: lib proj
lib:
$(MAKE) -C lib
$(MAKE) -C Libraries
proj: $(PROJ_NAME).elf
$(PROJ_NAME).elf: $(SRCS)
$(CC) $(CFLAGS) $^ -o $@ -Llib -lstm32f0
$(CC) $(CFLAGS) $^ -o $@ -LLibraries -lstm32f0
$(OBJCOPY) -O ihex $(PROJ_NAME).elf $(PROJ_NAME).hex
$(OBJCOPY) -O binary $(PROJ_NAME).elf $(PROJ_NAME).bin
program: $(PROJ_NAME).bin
openocd -f $(OPENOCD_BOARD_DIR)/stm32f0discovery.cfg -f extra/stm32f0-openocd.cfg -c "stm_flash `pwd`/$(PROJ_NAME).bin" -c shutdown
clean:
rm -f *.o
rm -f $(PROJ_NAME).elf

View File

@ -1,5 +1,53 @@
This program illuminates the blue LED on an STM32F0-Discovery board.
(it's actually blinking really really fast)
#STM32F0-Discovery Application Template
This package is for use when compiling programs for STM32F05xx ARM microcontrollers using arm-none-eabi-gcc (I'm using the [Code Sourcery G++:Lite Edition](http://www.mentor.com/embedded-software/sourcery-tools/sourcery-codebench/editions/lite-edition/) toolchain). The Makefile in the main directory will call the Make file in the Libraries directory, thereby automatically building the STM peripheral library. However, running 'make clean' will not affect the peripherals library (the same command can be run from the Libraries directory to do this).
This template will serve as a quick-start for those who do not wish to use an IDE, but rather develop in a text editor of choice and build from the command line. It is based on [an example template for the F4 Discovery board](http://jeremyherbert.net/get/stm32f4_getting_started) put together by Jeremy Herbert.
##Possible bug in the STM32F0xx peripheral library??
>It should be noted that I currently cannot compile the stock STM32F0xx peripheral library files (v1.0.0) without getting the following error:
>>STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dac.c:151:26: error: 'RCC_APB1Periph_DAC' undeclared (first use in this function)
>The workaround is to include stm32f0xx_rcc.h in the stm32f0xx_dac.c file. That is because the constant the compiler is complaining about is defined in that header file.
>**Compiler warning about assert_param():** When compiling the standard peripherals a warning is thrown about implicit declaration of assert_param(). This is due to the order in which files are being included. The function prototype is found in the stm32f0xx_conf.h file which for some reason is included after the peripherals are compiled. I don't know how to give it priority so it is included at right away. Please open an issue (or submit a pull request) if you know the compiler directives necessary to fix these warnings.
##Subfolders:
1. Library/
* This is the Library/ folder from the STM32F0xx_StdPeriph_Lib_V1.0.0 standard peripheral driver library produced by STM. This preserves the original structure which should make it easy to roll in library upgrades as they are published
* **Makefile** is not part of the STM release, and must be copied over if the library is upgraded.
* **IMPORTANT:** Please read the section about regarding a possible bug in one of the peripheral library files.
* Device/
* Folder contains device specific files:
* **stm32_flash.ld** is the linker script taken from the STM32F0-Discovery firmware package. It is found in the following directory:
>Project/Demonstration/TrueSTUDIO/STM32F0-Discovery_Demo/
* **startup_stm32f0xx.s** is the startup file taken from the STM32F0-Discovery firmware package. It is found in the following directory:
>Libraries/CMSIS/ST/STM32F0xx/Source/Templates/TrueSTUDIO/
* **stm32f0xx_conf.h** is used to configure the peripheral library. The file was file taken from the STM32F0-Discovery firmware package. It is found in the following directory:
>Project/Demonstration/
* inc/
* All include files for this particular project.
* src/
* All source files for this particular project (including main.c).
* **system_stm32f0xx.c** can be generated using an XLS file developed by STM. This sets up the system clock values for the project. The file included in this repository is taken from the STM32F0-Discovery firmware package. It is found in the following directory:
>Libraries/CMSIS/ST/STM32F0xx/Source/Templates/
* extra/
* This contains a procedure file used to write the image to the board via OpenOCD
##Loading the image on the board
If you have OpenOCD installed 'make program' can be used to flash the .bin file to the board. OpenOCD must be installed with stlink enabled. Clone the github repository and use these commands to compile/install it:
>./bootstrap
>./configure --prefix=/usr --enable-maintainer-mode --enable-stlink
>make
>sudo make install
If there is an error finding the .cfg file, please double-check the OPENOCD_BOARD_DIR constant at the top of the Makefile (in this template directory, not in OpenOCD).
This is modelled afer the STM32F4 example found here:
http://jeremyherbert.net/get/stm32f4_getting_started

22
extra/stm32f0-openocd.cfg Normal file
View File

@ -0,0 +1,22 @@
#This file can be used to automatically program the STM32F0-Discovery board's Flash memory from the command line
#After programming, the board must be power-cycled (briefly remove the power) for the program to start running
#This can be done by unpluggin the USB cable, or removing JP2
init
proc stm_flash {IMGFILE} {
reset halt
sleep 100
wait_halt 2
flash write_image erase $IMGFILE 0x08000000
sleep 100
verify_image $IMGFILE 0x08000000
sleep 100
}
proc stm_erase {} {
reset halt
sleep 100
stm32f1x mass_erase 0
sleep 100
}

View File

@ -1,156 +0,0 @@
/**
******************************************************************************
* @file stm32f0_discovery.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @brief This file contains definitions for STM32F0-Discovery's Leds, push-
* buttons hardware resources.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0_DISCOVERY_H
#define __STM32F0_DISCOVERY_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx.h"
/** @addtogroup Utilities
* @{
*/
/** @addtogroup STM32F0_DISCOVERY
* @{
*/
/** @addtogroup STM32F0_DISCOVERY_LOW_LEVEL
* @{
*/
/** @defgroup STM32F0_DISCOVERY_LOW_LEVEL_Exported_Types
* @{
*/
typedef enum
{
LED3 = 0,
LED4 = 1
} Led_TypeDef;
typedef enum
{
BUTTON_USER = 0,
} Button_TypeDef;
typedef enum
{
BUTTON_MODE_GPIO = 0,
BUTTON_MODE_EXTI = 1
} ButtonMode_TypeDef;
/**
* @}
*/
/** @defgroup STM32F0_DISCOVERY_LOW_LEVEL_Exported_Constants
* @{
*/
/** @addtogroup STM32F0_DISCOVERY_LOW_LEVEL_LED
* @{
*/
#define LEDn 2
#define LED3_PIN GPIO_Pin_9
#define LED3_GPIO_PORT GPIOC
#define LED3_GPIO_CLK RCC_AHBPeriph_GPIOC
#define LED4_PIN GPIO_Pin_8
#define LED4_GPIO_PORT GPIOC
#define LED4_GPIO_CLK RCC_AHBPeriph_GPIOC
/**
* @}
*/
/** @addtogroup SSTM32F0_DISCOVERY_LOW_LEVEL_BUTTON
* @{
*/
#define BUTTONn 1
/**
* @brief USER push-button
*/
#define USER_BUTTON_PIN GPIO_Pin_0
#define USER_BUTTON_GPIO_PORT GPIOA
#define USER_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOA
#define USER_BUTTON_EXTI_LINE EXTI_Line0
#define USER_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOA
#define USER_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource0
#define USER_BUTTON_EXTI_IRQn EXTI0_1_IRQn
/**
* @}
*/
/** @defgroup STM32F0_DISCOVERY_LOW_LEVEL_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup STM32F0_DISCOVERY_LOW_LEVEL_Exported_Functions
* @{
*/
void STM_EVAL_LEDInit(Led_TypeDef Led);
void STM_EVAL_LEDOn(Led_TypeDef Led);
void STM_EVAL_LEDOff(Led_TypeDef Led);
void STM_EVAL_LEDToggle(Led_TypeDef Led);
void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F0_DISCOVERY_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@ -1,256 +0,0 @@
/**
******************************************************************************
* @file stm32f0_discovery.c
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @brief This file provides set of firmware functions to manage Leds and
* push-button available on STM32F0-DISCOVERY Kit from STMicroelectronics.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f0_discovery.h"
/** @addtogroup Utilities
* @{
*/
/** @addtogroup STM32F0_DISCOVERY
* @{
*/
/** @defgroup STM32F0_DISCOVERY_LOW_LEVEL
* @brief This file provides firmware functions to manage Leds and push-buttons,
* available on STM32F0_DISCOVERY evaluation board from STMicroelectronics.
* @{
*/
/** @defgroup STM32F0_DISCOVERY_LOW_LEVEL_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup STM32F0_DISCOVERY_LOW_LEVEL_Private_Defines
* @{
*/
/**
* @}
*/
/** @defgroup STM32F0_DISCOVERY_LOW_LEVEL_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup STM32F0_DISCOVERY_LOW_LEVEL_Private_Variables
* @{
*/
GPIO_TypeDef* GPIO_PORT[LEDn] = {LED3_GPIO_PORT, LED4_GPIO_PORT};
const uint16_t GPIO_PIN[LEDn] = {LED3_PIN, LED4_PIN};
const uint32_t GPIO_CLK[LEDn] = {LED3_GPIO_CLK, LED4_GPIO_CLK};
GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {USER_BUTTON_GPIO_PORT};
const uint16_t BUTTON_PIN[BUTTONn] = {USER_BUTTON_PIN};
const uint32_t BUTTON_CLK[BUTTONn] = {USER_BUTTON_GPIO_CLK};
const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {USER_BUTTON_EXTI_LINE};
const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {USER_BUTTON_EXTI_PORT_SOURCE};
const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {USER_BUTTON_EXTI_PIN_SOURCE};
const uint16_t BUTTON_IRQn[BUTTONn] = {USER_BUTTON_EXTI_IRQn};
/**
* @}
*/
/** @defgroup STM32F0_DISCOVERY_LOW_LEVEL_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup STM32F0_DISCOVERY_LOW_LEVEL_Private_Functions
* @{
*/
/**
* @brief Configures LED GPIO.
* @param Led: Specifies the Led to be configured.
* This parameter can be one of following parameters:
* @arg LED3
* @arg LED4
* @retval None
*/
void STM_EVAL_LEDInit(Led_TypeDef Led)
{
GPIO_InitTypeDef GPIO_InitStructure;
/* Enable the GPIO_LED Clock */
RCC_AHBPeriphClockCmd(GPIO_CLK[Led], ENABLE);
/* Configure the GPIO_LED pin */
GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);
}
/**
* @brief Turns selected LED On.
* @param Led: Specifies the Led to be set on.
* This parameter can be one of following parameters:
* @arg LED3
* @arg LED4
* @retval None
*/
void STM_EVAL_LEDOn(Led_TypeDef Led)
{
GPIO_PORT[Led]->BSRR = GPIO_PIN[Led];
}
/**
* @brief Turns selected LED Off.
* @param Led: Specifies the Led to be set off.
* This parameter can be one of following parameters:
* @arg LED3
* @arg LED4
* @retval None
*/
void STM_EVAL_LEDOff(Led_TypeDef Led)
{
GPIO_PORT[Led]->BRR = GPIO_PIN[Led];
}
/**
* @brief Toggles the selected LED.
* @param Led: Specifies the Led to be toggled.
* This parameter can be one of following parameters:
* @arg LED3
* @arg LED4
* @retval None
*/
void STM_EVAL_LEDToggle(Led_TypeDef Led)
{
GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];
}
/**
* @brief Configures Button GPIO and EXTI Line.
* @param Button: Specifies the Button to be configured.
* This parameter can be:
* @arg BUTTON_USER: User Push Button
* @param Button_Mode: Specifies Button mode.
* This parameter can be one of following parameters:
* @arg BUTTON_MODE_GPIO: Button will be used as simple IO
* @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt
* generation capability
* @retval None
*/
void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
{
GPIO_InitTypeDef GPIO_InitStructure;
EXTI_InitTypeDef EXTI_InitStructure;
NVIC_InitTypeDef NVIC_InitStructure;
/* Enable the BUTTON Clock */
RCC_AHBPeriphClockCmd(BUTTON_CLK[Button], ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
/* Configure Button pin as input */
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];
GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);
if (Button_Mode == BUTTON_MODE_EXTI)
{
/* Connect Button EXTI Line to Button GPIO Pin */
SYSCFG_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);
/* Configure Button EXTI line */
EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
if (Button != BUTTON_USER)
{
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
}
else
{
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
}
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
EXTI_Init(&EXTI_InitStructure);
/* Enable and set Button EXTI Interrupt to the lowest priority */
NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];
NVIC_InitStructure.NVIC_IRQChannelPriority = 0x03;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
}
}
/**
* @brief Returns the selected Button state.
* @param Button: Specifies the Button to be checked.
* This parameter can be one of following parameters:
* @arg BUTTON_USER: User Push Button
* @retval The Button GPIO pin value.
*/
uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)
{
/* There is no Wakeup button on STM32f0-Discovery Kit */
return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@ -1,14 +1,5 @@
#include "stm32f0xx_conf.h"
/*
void TIM2_IRQHandler(void) {
// flash on update event
if (TIM2->SR & TIM_SR_UIF) GPIOC->ODR ^= (1 << 8);
TIM2->SR = 0x0; // reset the status register
}
*/
void SysTick_Handler(void) {
static uint16_t tick = 0;
@ -23,24 +14,12 @@ void SysTick_Handler(void) {
int main(void)
{
//#elif CONFIG_STM32F0_DISCOVERY
//
//#define GPIOC 0x48000800 /* port C */
//#define GPIOC_MODER (GPIOC + 0x00) /* port mode register */
//#define LED_PORT_ODR (GPIOC + 0x14) /* port output data register */
//
//#define LED_BLUE (1 << 8) /* port C, pin 8 */
//#define LED_GREEN (1 << 9) /* port C, pin 9 */
//#define LED_ORANGE 0
//#define LED_RED 0
RCC->AHBENR |= RCC_AHBENR_GPIOCEN; // enable the clock to GPIOC
//(RM0091 lists this as IOPCEN, not GPIOCEN)
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; // enable TIM2 clock
GPIOC->MODER = (1 << 16);
//NVIC->ISER[0] |= 1<< (TIM2_IRQn); // enable the TIM2 IRQ
SysTick_Config(SystemCoreClock/100);
TIM2->PSC = 0x0; // no prescaler, timer counts up in sync with the peripheral clock

0
src/system_stm32f0xx.c Executable file → Normal file
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