diff --git a/lib/Makefile b/lib/Makefile
index feee00e..d6105ea 100755
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -10,7 +10,6 @@ CFLAGS += -mlittle-endian -mthumb -mcpu=cortex-m0 -march=armv6s-m
 CFLAGS += -ffreestanding -nostdlib
 CFLAGS += -Iinc -Iinc/core -Iinc/peripherals
 
-SRCS  = stm32f0_discovery.c
 SRCS = stm32f0xx_adc.c stm32f0xx_cec.c stm32f0xx_comp.c stm32f0xx_crc.c \
 	stm32f0xx_dac.c stm32f0xx_dbgmcu.c stm32f0xx_dma.c stm32f0xx_exti.c \
 	stm32f0xx_flash.c stm32f0xx_gpio.c stm32f0xx_i2c.c stm32f0xx_iwdg.c \
diff --git a/src/main.c b/src/main.c
index 6124cdd..9f198ce 100755
--- a/src/main.c
+++ b/src/main.c
@@ -1,11 +1,24 @@
 #include "stm32f0xx_conf.h"
 
+/*
 void TIM2_IRQHandler(void) {
   // flash on update event
   if (TIM2->SR & TIM_SR_UIF) GPIOC->ODR ^= (1 << 8);
    
   TIM2->SR = 0x0; // reset the status register
 }
+*/
+
+void SysTick_Handler(void) {
+  static uint16_t tick = 0;
+  
+  switch (tick++) {
+  	case 100:
+  		tick = 0;
+  		GPIOC->ODR ^= (1 << 8);
+  		break;
+  }
+}
 
 int main(void)
 {
@@ -27,7 +40,8 @@ int main(void)
 
 	GPIOC->MODER = (1 << 16);
 	
-	NVIC->ISER[0] |= 1<< (TIM2_IRQn); // enable the TIM2 IRQ
+	//NVIC->ISER[0] |= 1<< (TIM2_IRQn); // enable the TIM2 IRQ
+	SysTick_Config(SystemCoreClock/100);
 	
 	TIM2->PSC = 0x0; // no prescaler, timer counts up in sync with the peripheral clock
 	TIM2->DIER |= TIM_DIER_UIE; // enable update interrupt