STM32F0-Discovery template (not yet compiling)
This commit is contained in:
Mike Szczys
commit
e7b8823c4f
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@ -0,0 +1,53 @@
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# put your *.o targets here, make should handle the rest!
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SRCS = main.c system_stm32f0xx.c
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# all the files will be generated with this name (main.elf, main.bin, main.hex, etc)
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PROJ_NAME=main
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# that's it, no need to change anything below this line!
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###################################################
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CC=arm-none-eabi-gcc
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OBJCOPY=arm-none-eabi-objcopy
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CFLAGS = -g -O2 -Wall -Tstm32_flash.ld
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CFLAGS += -mlittle-endian -mthumb -mcpu=cortex-m0 -march=armv6s-m
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###################################################
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vpath %.c src
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vpath %.a lib
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ROOT=$(shell pwd)
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CFLAGS += -Iinc -Ilib -Ilib/inc
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CFLAGS += -Ilib/inc/core -Ilib/inc/peripherals
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SRCS += lib/startup_stm32f0xx.s # add startup file to build
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OBJS = $(SRCS:.c=.o)
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###################################################
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.PHONY: lib proj
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all: lib proj
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lib:
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$(MAKE) -C lib
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proj: $(PROJ_NAME).elf
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$(PROJ_NAME).elf: $(SRCS)
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$(CC) $(CFLAGS) $^ -o $@ -Llib -lstm32f0
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$(OBJCOPY) -O ihex $(PROJ_NAME).elf $(PROJ_NAME).hex
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$(OBJCOPY) -O binary $(PROJ_NAME).elf $(PROJ_NAME).bin
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clean:
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rm -f *.o
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rm -f $(PROJ_NAME).elf
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rm -f $(PROJ_NAME).hex
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rm -f $(PROJ_NAME).bin
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@ -0,0 +1,81 @@
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/**
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******************************************************************************
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* @file IO_Toggle/stm32f0xx_conf.h
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* @author MCD Application Team
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* @version V1.0.0
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* @date 23-March-2012
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* @brief Library configuration file.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
|
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* limitations under the License.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F0XX_CONF_H
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#define __STM32F0XX_CONF_H
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/* Includes ------------------------------------------------------------------*/
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/* Comment the line below to disable peripheral header file inclusion */
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#include "stm32f0xx_adc.h"
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#include "stm32f0xx_cec.h"
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#include "stm32f0xx_crc.h"
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#include "stm32f0xx_comp.h"
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#include "stm32f0xx_dac.h"
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#include "stm32f0xx_dbgmcu.h"
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#include "stm32f0xx_dma.h"
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#include "stm32f0xx_exti.h"
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#include "stm32f0xx_flash.h"
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#include "stm32f0xx_gpio.h"
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#include "stm32f0xx_syscfg.h"
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#include "stm32f0xx_i2c.h"
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#include "stm32f0xx_iwdg.h"
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#include "stm32f0xx_pwr.h"
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#include "stm32f0xx_rcc.h"
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#include "stm32f0xx_rtc.h"
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#include "stm32f0xx_spi.h"
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#include "stm32f0xx_tim.h"
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#include "stm32f0xx_usart.h"
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#include "stm32f0xx_wwdg.h"
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#include "stm32f0xx_misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/* Uncomment the line below to expanse the "assert_param" macro in the
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Standard Peripheral Library drivers code */
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/* #define USE_FULL_ASSERT 1 */
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/* Exported macro ------------------------------------------------------------*/
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#ifdef USE_FULL_ASSERT
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/**
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* @brief The assert_param macro is used for function's parameters check.
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* @param expr: If expr is false, it calls assert_failed function which reports
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* the name of the source file and the source line number of the call
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* that failed. If expr is true, it returns no value.
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* @retval None
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*/
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#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
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/* Exported functions ------------------------------------------------------- */
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void assert_failed(uint8_t* file, uint32_t line);
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#else
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#define assert_param(expr) ((void)0)
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#endif /* USE_FULL_ASSERT */
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#endif /* __STM32F0XX_CONF_H */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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@ -0,0 +1,34 @@
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CC=arm-none-eabi-gcc
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AR=arm-none-eabi-ar
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###########################################
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vpath %.c src src/peripherals
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CFLAGS = -g -O2 -Wall
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CFLAGS += -mlittle-endian -mthumb -mcpu=cortex-m0 -march=armv6s-m
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CFLAGS += -ffreestanding -nostdlib
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CFLAGS += -Iinc -Iinc/core -Iinc/peripherals
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#SRCS = stm32f0_discovery.c
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SRCS = stm32f0xx_adc.c stm32f0xx_cec.c stm32f0xx_comp.c stm32f0xx_crc.c \
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stm32f0xx_dac.c stm32f0xx_dbgmcu.c stm32f0xx_dma.c stm32f0xx_exti.c \
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stm32f0xx_flash.c stm32f0xx_gpio.c stm32f0xx_i2c.c stm32f0xx_iwdg.c \
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stm32f0xx_misc.c stm32f0xx_pwr.c stm32f0xx_rcc.c stm32f0xx_rtc.c \
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stm32f0xx_spi.c stm32f0xx_syscfg.c stm32f0xx_tim.c \
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stm32f0xx_usart.c stm32f0xx_wwdg.c
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OBJS = $(SRCS:.c=.o)
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.PHONY: libstm32f0.a
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all: libstm32f0.a
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%.o : %.c
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$(CC) $(CFLAGS) -c -o $@ $^
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libstm32f0.a: $(OBJS)
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$(AR) -r $@ $(OBJS)
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clean:
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rm -f $(OBJS) libstm32f0.a
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/* ----------------------------------------------------------------------
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* Copyright (C) 2010 ARM Limited. All rights reserved.
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*
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* $Date: 11. November 2010
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* $Revision: V1.0.2
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*
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* Project: CMSIS DSP Library
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* Title: arm_common_tables.h
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*
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* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
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*
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* Target Processor: Cortex-M4/Cortex-M3
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*
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* Version 1.0.2 2010/11/11
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* Documentation updated.
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*
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* Version 1.0.1 2010/10/05
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* Production release and review comments incorporated.
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*
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* Version 1.0.0 2010/09/20
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* Production release and review comments incorporated.
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* -------------------------------------------------------------------- */
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#ifndef _ARM_COMMON_TABLES_H
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#define _ARM_COMMON_TABLES_H
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#include "arm_math.h"
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extern uint16_t armBitRevTable[256];
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extern q15_t armRecipTableQ15[64];
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extern q31_t armRecipTableQ31[64];
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extern const q31_t realCoefAQ31[1024];
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extern const q31_t realCoefBQ31[1024];
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#endif /* ARM_COMMON_TABLES_H */
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File diff suppressed because it is too large
Load Diff
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/**************************************************************************//**
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* @file core_cm0.h
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* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
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* @version V2.10
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* @date 19. July 2011
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*
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* @note
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* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
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*
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#if defined ( __ICCARM__ )
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#pragma system_include /* treat file as system include file for MISRA check */
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef __CORE_CM0_H_GENERIC
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#define __CORE_CM0_H_GENERIC
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/** \mainpage CMSIS Cortex-M0
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This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
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It consists of:
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- Cortex-M Core Register Definitions
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- Cortex-M functions
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- Cortex-M instructions
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The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease
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access to the Cortex-M Core
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*/
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/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions
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CMSIS violates following MISRA-C2004 Rules:
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- Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>
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Function definitions in header files are used to allow 'inlining'.
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- Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
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Unions are used for effective representation of core registers.
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- Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>
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Function-like macros are used to allow more efficient code.
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*/
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/*******************************************************************************
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* CMSIS definitions
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******************************************************************************/
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/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
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This file defines all structures and symbols for CMSIS core:
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- CMSIS version number
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- Cortex-M core
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- Cortex-M core Revision Number
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@{
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*/
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/* CMSIS CM0 definitions */
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#define __CM0_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */
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#define __CM0_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
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#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
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#define __CORTEX_M (0x00) /*!< Cortex core */
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#if defined ( __CC_ARM )
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#define __ASM __asm /*!< asm keyword for ARM Compiler */
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#define __INLINE __inline /*!< inline keyword for ARM Compiler */
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#elif defined ( __ICCARM__ )
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#define __ASM __asm /*!< asm keyword for IAR Compiler */
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#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
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#elif defined ( __GNUC__ )
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#define __ASM __asm /*!< asm keyword for GNU Compiler */
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#define __INLINE inline /*!< inline keyword for GNU Compiler */
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|
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#elif defined ( __TASKING__ )
|
||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
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#define __INLINE inline /*!< inline keyword for TASKING Compiler */
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|
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#endif
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|
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/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
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#define __FPU_USED 0
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#if defined ( __CC_ARM )
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#if defined __TARGET_FPU_VFP
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#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#elif defined ( __ICCARM__ )
|
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#if defined __ARMVFP__
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#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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#endif
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|
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#elif defined ( __GNUC__ )
|
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#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
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#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
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#elif defined ( __TASKING__ )
|
||||
/* add preprocessor checks */
|
||||
#endif
|
||||
|
||||
#include <stdint.h> /*!< standard types definitions */
|
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#include "core_cmInstr.h" /*!< Core Instruction Access */
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||||
#include "core_cmFunc.h" /*!< Core Function Access */
|
||||
|
||||
#endif /* __CORE_CM0_H_GENERIC */
|
||||
|
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#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM0_H_DEPENDANT
|
||||
#define __CORE_CM0_H_DEPENDANT
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||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM0_REV
|
||||
#define __CM0_REV 0x0000
|
||||
#warning "__CM0_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< defines 'write only' permissions */
|
||||
#define __IO volatile /*!< defines 'read / write' permissions */
|
||||
|
||||
/*@} end of group CMSIS_core_definitions */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
******************************************************************************/
|
||||
/** \defgroup CMSIS_core_register CMSIS Core Register
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
*/
|
||||
|
||||
/** \ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE CMSIS Core
|
||||
Type definitions for the Cortex-M Core Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/** \brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
#if (__CORTEX_M != 0x04)
|
||||
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
|
||||
#else
|
||||
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
|
||||
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
|
||||
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
|
||||
#endif
|
||||
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
|
||||
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
|
||||
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
#if (__CORTEX_M != 0x04)
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
#else
|
||||
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
|
||||
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
|
||||
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
|
||||
#endif
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
|
||||
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
|
||||
/** \brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
|
||||
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/** \ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC CMSIS NVIC
|
||||
Type definitions for the Cortex-M NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31];
|
||||
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31];
|
||||
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31];
|
||||
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31];
|
||||
uint32_t RESERVED4[64];
|
||||
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/** \ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB CMSIS SCB
|
||||
Type definitions for the Cortex-M System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/** \brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
uint32_t RESERVED0;
|
||||
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/** \ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick CMSIS SysTick
|
||||
Type definitions for the Cortex-M System Timer Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/** \brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
|
||||
/** \ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug CMSIS Core Debug
|
||||
Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP
|
||||
and not via processor. Therefore they are not covered by the Cortex-M0 header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/** \ingroup CMSIS_core_register
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Cortex-M0 Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
******************************************************************************/
|
||||
/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
|
||||
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
|
||||
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
|
||||
|
||||
|
||||
/** \brief Enable External Interrupt
|
||||
|
||||
This function enables a device specific interrupt in the NVIC interrupt controller.
|
||||
The interrupt number cannot be a negative value.
|
||||
|
||||
\param [in] IRQn Number of the external interrupt to enable
|
||||
*/
|
||||
static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable External Interrupt
|
||||
|
||||
This function disables a device specific interrupt in the NVIC interrupt controller.
|
||||
The interrupt number cannot be a negative value.
|
||||
|
||||
\param [in] IRQn Number of the external interrupt to disable
|
||||
*/
|
||||
static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Pending Interrupt
|
||||
|
||||
This function reads the pending register in the NVIC and returns the pending bit
|
||||
for the specified interrupt.
|
||||
|
||||
\param [in] IRQn Number of the interrupt for get pending
|
||||
\return 0 Interrupt status is not pending
|
||||
\return 1 Interrupt status is pending
|
||||
*/
|
||||
static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Pending Interrupt
|
||||
|
||||
This function sets the pending bit for the specified interrupt.
|
||||
The interrupt number cannot be a negative value.
|
||||
|
||||
\param [in] IRQn Number of the interrupt for set pending
|
||||
*/
|
||||
static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
|
||||
/** \brief Clear Pending Interrupt
|
||||
|
||||
This function clears the pending bit for the specified interrupt.
|
||||
The interrupt number cannot be a negative value.
|
||||
|
||||
\param [in] IRQn Number of the interrupt for clear pending
|
||||
*/
|
||||
static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Interrupt Priority
|
||||
|
||||
This function sets the priority for the specified interrupt. The interrupt
|
||||
number can be positive to specify an external (device specific)
|
||||
interrupt, or negative to specify an internal (core) interrupt.
|
||||
|
||||
Note: The priority cannot be set for every core interrupt.
|
||||
|
||||
\param [in] IRQn Number of the interrupt for set priority
|
||||
\param [in] priority Priority to set
|
||||
*/
|
||||
static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if(IRQn < 0) {
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
|
||||
else {
|
||||
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Interrupt Priority
|
||||
|
||||
This function reads the priority for the specified interrupt. The interrupt
|
||||
number can be positive to specify an external (device specific)
|
||||
interrupt, or negative to specify an internal (core) interrupt.
|
||||
|
||||
The returned priority value is automatically aligned to the implemented
|
||||
priority bits of the microcontroller.
|
||||
|
||||
\param [in] IRQn Number of the interrupt for get priority
|
||||
\return Interrupt Priority
|
||||
*/
|
||||
static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if(IRQn < 0) {
|
||||
return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
|
||||
else {
|
||||
return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
|
||||
}
|
||||
|
||||
|
||||
/** \brief System Reset
|
||||
|
||||
This function initiate a system reset request to reset the MCU.
|
||||
*/
|
||||
static __INLINE void NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
while(1); /* wait until reset */
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if (__Vendor_SysTickConfig == 0)
|
||||
|
||||
/** \brief System Tick Configuration
|
||||
|
||||
This function initialises the system tick timer and its interrupt and start the system tick timer.
|
||||
Counter is in free running mode to generate periodical interrupts.
|
||||
|
||||
\param [in] ticks Number of ticks between two interrupts
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
static __INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
|
||||
|
||||
SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
|
||||
SysTick->VAL = 0; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#endif /* __CORE_CM0_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,701 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cm4_simd.h
|
||||
* @brief CMSIS Cortex-M4 SIMD Header File
|
||||
* @version V2.10
|
||||
* @date 19. July 2011
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2010-2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM4_SIMD_H
|
||||
#define __CORE_CM4_SIMD_H
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
|
||||
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/
|
||||
/* intrinsic __SADD8 see intrinsics.h */
|
||||
/* intrinsic __QADD8 see intrinsics.h */
|
||||
/* intrinsic __SHADD8 see intrinsics.h */
|
||||
/* intrinsic __UADD8 see intrinsics.h */
|
||||
/* intrinsic __UQADD8 see intrinsics.h */
|
||||
/* intrinsic __UHADD8 see intrinsics.h */
|
||||
/* intrinsic __SSUB8 see intrinsics.h */
|
||||
/* intrinsic __QSUB8 see intrinsics.h */
|
||||
/* intrinsic __SHSUB8 see intrinsics.h */
|
||||
/* intrinsic __USUB8 see intrinsics.h */
|
||||
/* intrinsic __UQSUB8 see intrinsics.h */
|
||||
/* intrinsic __UHSUB8 see intrinsics.h */
|
||||
/* intrinsic __SADD16 see intrinsics.h */
|
||||
/* intrinsic __QADD16 see intrinsics.h */
|
||||
/* intrinsic __SHADD16 see intrinsics.h */
|
||||
/* intrinsic __UADD16 see intrinsics.h */
|
||||
/* intrinsic __UQADD16 see intrinsics.h */
|
||||
/* intrinsic __UHADD16 see intrinsics.h */
|
||||
/* intrinsic __SSUB16 see intrinsics.h */
|
||||
/* intrinsic __QSUB16 see intrinsics.h */
|
||||
/* intrinsic __SHSUB16 see intrinsics.h */
|
||||
/* intrinsic __USUB16 see intrinsics.h */
|
||||
/* intrinsic __UQSUB16 see intrinsics.h */
|
||||
/* intrinsic __UHSUB16 see intrinsics.h */
|
||||
/* intrinsic __SASX see intrinsics.h */
|
||||
/* intrinsic __QASX see intrinsics.h */
|
||||
/* intrinsic __SHASX see intrinsics.h */
|
||||
/* intrinsic __UASX see intrinsics.h */
|
||||
/* intrinsic __UQASX see intrinsics.h */
|
||||
/* intrinsic __UHASX see intrinsics.h */
|
||||
/* intrinsic __SSAX see intrinsics.h */
|
||||
/* intrinsic __QSAX see intrinsics.h */
|
||||
/* intrinsic __SHSAX see intrinsics.h */
|
||||
/* intrinsic __USAX see intrinsics.h */
|
||||
/* intrinsic __UQSAX see intrinsics.h */
|
||||
/* intrinsic __UHSAX see intrinsics.h */
|
||||
/* intrinsic __USAD8 see intrinsics.h */
|
||||
/* intrinsic __USADA8 see intrinsics.h */
|
||||
/* intrinsic __SSAT16 see intrinsics.h */
|
||||
/* intrinsic __USAT16 see intrinsics.h */
|
||||
/* intrinsic __UXTB16 see intrinsics.h */
|
||||
/* intrinsic __SXTB16 see intrinsics.h */
|
||||
/* intrinsic __UXTAB16 see intrinsics.h */
|
||||
/* intrinsic __SXTAB16 see intrinsics.h */
|
||||
/* intrinsic __SMUAD see intrinsics.h */
|
||||
/* intrinsic __SMUADX see intrinsics.h */
|
||||
/* intrinsic __SMLAD see intrinsics.h */
|
||||
/* intrinsic __SMLADX see intrinsics.h */
|
||||
/* intrinsic __SMLALD see intrinsics.h */
|
||||
/* intrinsic __SMLALDX see intrinsics.h */
|
||||
/* intrinsic __SMUSD see intrinsics.h */
|
||||
/* intrinsic __SMUSDX see intrinsics.h */
|
||||
/* intrinsic __SMLSD see intrinsics.h */
|
||||
/* intrinsic __SMLSDX see intrinsics.h */
|
||||
/* intrinsic __SMLSLD see intrinsics.h */
|
||||
/* intrinsic __SMLSLDX see intrinsics.h */
|
||||
/* intrinsic __SEL see intrinsics.h */
|
||||
/* intrinsic __QADD see intrinsics.h */
|
||||
/* intrinsic __QSUB see intrinsics.h */
|
||||
/* intrinsic __PKHBT see intrinsics.h */
|
||||
/* intrinsic __PKHTB see intrinsics.h */
|
||||
|
||||
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#define __SSAT16(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
#define __USAT16(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#define __SMLALD(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
|
||||
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
|
||||
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
|
||||
})
|
||||
|
||||
#define __SMLALDX(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
|
||||
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
|
||||
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
|
||||
})
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#define __SMLSLD(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
|
||||
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
|
||||
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
|
||||
})
|
||||
|
||||
#define __SMLSLDX(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
|
||||
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
|
||||
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
|
||||
})
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
||||
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
||||
if (ARG3 == 0) \
|
||||
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
|
||||
else \
|
||||
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
|
||||
|
||||
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
/* not yet supported */
|
||||
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#endif /* __CORE_CM4_SIMD_H */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,609 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmFunc.h
|
||||
* @brief CMSIS Cortex-M Core Function Access Header File
|
||||
* @version V2.10
|
||||
* @date 26. July 2011
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __CORE_CMFUNC_H
|
||||
#define __CORE_CMFUNC_H
|
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
#if (__ARMCC_VERSION < 400677)
|
||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/* intrinsic void __enable_irq(); */
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/** \brief Get Control Register
|
||||
|
||||
This function returns the content of the Control Register.
|
||||
|
||||
\return Control Register value
|
||||
*/
|
||||
static __INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Control Register
|
||||
|
||||
This function writes the given value to the Control Register.
|
||||
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
static __INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get ISPR Register
|
||||
|
||||
This function returns the content of the ISPR Register.
|
||||
|
||||
\return ISPR Register value
|
||||
*/
|
||||
static __INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get APSR Register
|
||||
|
||||
This function returns the content of the APSR Register.
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
static __INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get xPSR Register
|
||||
|
||||
This function returns the content of the xPSR Register.
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
static __INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Process Stack Pointer
|
||||
|
||||
This function returns the current value of the Process Stack Pointer (PSP).
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
static __INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
static __INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Main Stack Pointer
|
||||
|
||||
This function returns the current value of the Main Stack Pointer (MSP).
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
static __INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
static __INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Priority Mask
|
||||
|
||||
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
|
||||
\return Priority Mask value
|
||||
*/
|
||||
static __INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Priority Mask
|
||||
|
||||
This function assigns the given value to the Priority Mask Register.
|
||||
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
static __INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Enable FIQ
|
||||
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/** \brief Disable FIQ
|
||||
|
||||
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/** \brief Get Base Priority
|
||||
|
||||
This function returns the current value of the Base Priority register.
|
||||
|
||||
\return Base Priority register value
|
||||
*/
|
||||
static __INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Base Priority
|
||||
|
||||
This function assigns the given value to the Base Priority register.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
static __INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xff);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Fault Mask
|
||||
|
||||
This function returns the current value of the Fault Mask register.
|
||||
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
static __INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Fault Mask
|
||||
|
||||
This function assigns the given value to the Fault Mask register.
|
||||
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
static __INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1);
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
This function returns the current value of the Floating Point Status/Control register.
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
static __INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set FPSCR
|
||||
|
||||
This function assigns the given value to the Floating Point Status/Control register.
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
static __INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) */
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/** \brief Enable IRQ Interrupts
|
||||
|
||||
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie i");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable IRQ Interrupts
|
||||
|
||||
This function disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid i");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Control Register
|
||||
|
||||
This function returns the content of the Control Register.
|
||||
|
||||
\return Control Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, control" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Control Register
|
||||
|
||||
This function writes the given value to the Control Register.
|
||||
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
__ASM volatile ("MSR control, %0" : : "r" (control) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get ISPR Register
|
||||
|
||||
This function returns the content of the ISPR Register.
|
||||
|
||||
\return ISPR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get APSR Register
|
||||
|
||||
This function returns the content of the APSR Register.
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get xPSR Register
|
||||
|
||||
This function returns the content of the xPSR Register.
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Process Stack Pointer
|
||||
|
||||
This function returns the current value of the Process Stack Pointer (PSP).
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Main Stack Pointer
|
||||
|
||||
This function returns the current value of the Main Stack Pointer (MSP).
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Priority Mask
|
||||
|
||||
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Priority Mask
|
||||
|
||||
This function assigns the given value to the Priority Mask Register.
|
||||
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Enable FIQ
|
||||
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie f");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable FIQ
|
||||
|
||||
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid f");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Base Priority
|
||||
|
||||
This function returns the current value of the Base Priority register.
|
||||
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Base Priority
|
||||
|
||||
This function assigns the given value to the Base Priority register.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
|
||||
{
|
||||
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Fault Mask
|
||||
|
||||
This function returns the current value of the Fault Mask register.
|
||||
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Fault Mask
|
||||
|
||||
This function assigns the given value to the Fault Mask register.
|
||||
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
This function returns the current value of the Floating Point Status/Control register.
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
|
||||
return(result);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set FPSCR
|
||||
|
||||
This function assigns the given value to the Floating Point Status/Control register.
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) */
|
||||
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all instrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
#endif /* __CORE_CMFUNC_H */
|
||||
|
|
@ -0,0 +1,585 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h
|
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||
* @version V2.10
|
||||
* @date 19. July 2011
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __CORE_CMINSTR_H
|
||||
#define __CORE_CMINSTR_H
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
#if (__ARMCC_VERSION < 400677)
|
||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() __isb(0xF)
|
||||
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() __dsb(0xF)
|
||||
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() __dmb(0xF)
|
||||
|
||||
|
||||
/** \brief Reverse byte order (32 bit)
|
||||
|
||||
This function reverses the byte order in integer value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
static __INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
static __INLINE __ASM int32_t __REVSH(int32_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __RBIT __rbit
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive STR command for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive STR command for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive STR command for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
|
||||
{
|
||||
__ASM volatile ("nop");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
|
||||
{
|
||||
__ASM volatile ("wfi");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
|
||||
{
|
||||
__ASM volatile ("wfe");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
|
||||
{
|
||||
__ASM volatile ("sev");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
|
||||
{
|
||||
__ASM volatile ("isb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
|
||||
{
|
||||
__ASM volatile ("dsb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
|
||||
{
|
||||
__ASM volatile ("dmb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order (32 bit)
|
||||
|
||||
This function reverses the byte order in integer value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
|
||||
{
|
||||
uint8_t result;
|
||||
|
||||
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
|
||||
{
|
||||
uint16_t result;
|
||||
|
||||
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive STR command for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive STR command for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive STR command for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
|
||||
{
|
||||
__ASM volatile ("clrex");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
|
||||
{
|
||||
uint8_t result;
|
||||
|
||||
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
#endif /* __CORE_CMINSTR_H */
|
||||
|
|
@ -0,0 +1,432 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_adc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file contains all the functions prototypes for the ADC firmware
|
||||
* library
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0XX_ADC_H
|
||||
#define __STM32F0XX_ADC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief ADC Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ADC_Resolution; /*!< Selects the resolution of the conversion.
|
||||
This parameter can be a value of @ref ADC_Resolution */
|
||||
|
||||
FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
|
||||
Continuous or Single mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t ADC_ExternalTrigConvEdge; /*!< Selects the external trigger Edge and enables the
|
||||
trigger of a regular group. This parameter can be a value
|
||||
of @ref ADC_external_trigger_edge_conversion */
|
||||
|
||||
uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog
|
||||
to digital conversion of regular channels. This parameter
|
||||
can be a value of @ref ADC_external_trigger_sources_for_channels_conversion */
|
||||
|
||||
uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
|
||||
This parameter can be a value of @ref ADC_data_align */
|
||||
|
||||
uint32_t ADC_ScanDirection; /*!< Specifies in which direction the channels will be scanned
|
||||
in the sequence.
|
||||
This parameter can be a value of @ref ADC_Scan_Direction */
|
||||
}ADC_InitTypeDef;
|
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1)
|
||||
|
||||
/** @defgroup ADC_JitterOff
|
||||
* @{
|
||||
*/
|
||||
#define ADC_JitterOff_PCLKDiv2 ADC_CFGR2_JITOFFDIV2
|
||||
#define ADC_JitterOff_PCLKDiv4 ADC_CFGR2_JITOFFDIV4
|
||||
|
||||
#define IS_ADC_JITTEROFF(JITTEROFF) (((JITTEROFF) & 0x3FFFFFFF) == (uint32_t)RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Resolution
|
||||
* @{
|
||||
*/
|
||||
#define ADC_Resolution_12b ((uint32_t)0x00000000)
|
||||
#define ADC_Resolution_10b ADC_CFGR1_RES_0
|
||||
#define ADC_Resolution_8b ADC_CFGR1_RES_1
|
||||
#define ADC_Resolution_6b ADC_CFGR1_RES
|
||||
|
||||
#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
|
||||
((RESOLUTION) == ADC_Resolution_10b) || \
|
||||
((RESOLUTION) == ADC_Resolution_8b) || \
|
||||
((RESOLUTION) == ADC_Resolution_6b))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_external_trigger_edge_conversion
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)
|
||||
#define ADC_ExternalTrigConvEdge_Rising ADC_CFGR1_EXTEN_0
|
||||
#define ADC_ExternalTrigConvEdge_Falling ADC_CFGR1_EXTEN_1
|
||||
#define ADC_ExternalTrigConvEdge_RisingFalling ADC_CFGR1_EXTEN
|
||||
|
||||
#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
|
||||
((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
|
||||
((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
|
||||
((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_external_trigger_sources_for_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* TIM1 */
|
||||
#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000)
|
||||
#define ADC_ExternalTrigConv_T1_CC4 ADC_CFGR1_EXTSEL_0
|
||||
|
||||
/* TIM2 */
|
||||
#define ADC_ExternalTrigConv_T2_TRGO ADC_CFGR1_EXTSEL_1
|
||||
|
||||
/* TIM3 */
|
||||
#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_0 | ADC_CFGR1_EXTSEL_1))
|
||||
|
||||
/* TIM15 */
|
||||
#define ADC_ExternalTrigConv_T15_TRGO ADC_CFGR1_EXTSEL_2
|
||||
|
||||
#define IS_ADC_EXTERNAL_TRIG_CONV(CONV) (((CONV) == ADC_ExternalTrigConv_T1_TRGO) || \
|
||||
((CONV) == ADC_ExternalTrigConv_T1_CC4) || \
|
||||
((CONV) == ADC_ExternalTrigConv_T2_TRGO) || \
|
||||
((CONV) == ADC_ExternalTrigConv_T3_TRGO) || \
|
||||
((CONV) == ADC_ExternalTrigConv_T15_TRGO))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_data_align
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
|
||||
#define ADC_DataAlign_Left ADC_CFGR1_ALIGN
|
||||
|
||||
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
|
||||
((ALIGN) == ADC_DataAlign_Left))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Scan_Direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_ScanDirection_Upward ((uint32_t)0x00000000)
|
||||
#define ADC_ScanDirection_Backward ADC_CFGR1_SCANDIR
|
||||
|
||||
#define IS_ADC_SCAN_DIRECTION(DIRECTION) (((DIRECTION) == ADC_ScanDirection_Upward) || \
|
||||
((DIRECTION) == ADC_ScanDirection_Backward))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Scan_Direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_DMAMode_OneShot ((uint32_t)0x00000000)
|
||||
#define ADC_DMAMode_Circular ADC_CFGR1_DMACFG
|
||||
|
||||
#define IS_ADC_DMA_MODE(MODE) (((MODE) == ADC_DMAMode_OneShot) || \
|
||||
((MODE) == ADC_DMAMode_Circular))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_analog_watchdog_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_AnalogWatchdog_Channel_0 ((uint32_t)0x00000000)
|
||||
#define ADC_AnalogWatchdog_Channel_1 ((uint32_t)0x04000000)
|
||||
#define ADC_AnalogWatchdog_Channel_2 ((uint32_t)0x08000000)
|
||||
#define ADC_AnalogWatchdog_Channel_3 ((uint32_t)0x0C000000)
|
||||
#define ADC_AnalogWatchdog_Channel_4 ((uint32_t)0x10000000)
|
||||
#define ADC_AnalogWatchdog_Channel_5 ((uint32_t)0x14000000)
|
||||
#define ADC_AnalogWatchdog_Channel_6 ((uint32_t)0x18000000)
|
||||
#define ADC_AnalogWatchdog_Channel_7 ((uint32_t)0x1C000000)
|
||||
#define ADC_AnalogWatchdog_Channel_8 ((uint32_t)0x20000000)
|
||||
#define ADC_AnalogWatchdog_Channel_9 ((uint32_t)0x24000000)
|
||||
#define ADC_AnalogWatchdog_Channel_10 ((uint32_t)0x28000000)
|
||||
#define ADC_AnalogWatchdog_Channel_11 ((uint32_t)0x2C000000)
|
||||
#define ADC_AnalogWatchdog_Channel_12 ((uint32_t)0x30000000)
|
||||
#define ADC_AnalogWatchdog_Channel_13 ((uint32_t)0x34000000)
|
||||
#define ADC_AnalogWatchdog_Channel_14 ((uint32_t)0x38000000)
|
||||
#define ADC_AnalogWatchdog_Channel_15 ((uint32_t)0x3C000000)
|
||||
#define ADC_AnalogWatchdog_Channel_16 ((uint32_t)0x40000000)
|
||||
#define ADC_AnalogWatchdog_Channel_17 ((uint32_t)0x44000000)
|
||||
#define ADC_AnalogWatchdog_Channel_18 ((uint32_t)0x48000000)
|
||||
|
||||
|
||||
#define IS_ADC_ANALOG_WATCHDOG_CHANNEL(CHANNEL) (((CHANNEL) == ADC_AnalogWatchdog_Channel_0) || \
|
||||
((CHANNEL) == ADC_AnalogWatchdog_Channel_1) || \
|
||||
((CHANNEL) == ADC_AnalogWatchdog_Channel_2) || \
|
||||
((CHANNEL) == ADC_AnalogWatchdog_Channel_3) || \
|
||||
((CHANNEL) == ADC_AnalogWatchdog_Channel_4) || \
|
||||
((CHANNEL) == ADC_AnalogWatchdog_Channel_5) || \
|
||||
((CHANNEL) == ADC_AnalogWatchdog_Channel_6) || \
|
||||
((CHANNEL) == ADC_AnalogWatchdog_Channel_7) || \
|
||||
((CHANNEL) == ADC_AnalogWatchdog_Channel_8) || \
|
||||
((CHANNEL) == ADC_AnalogWatchdog_Channel_9) || \
|
||||
((CHANNEL) == ADC_AnalogWatchdog_Channel_10) || \
|
||||
((CHANNEL) == ADC_AnalogWatchdog_Channel_11) || \
|
||||
((CHANNEL) == ADC_AnalogWatchdog_Channel_12) || \
|
||||
((CHANNEL) == ADC_AnalogWatchdog_Channel_13) || \
|
||||
((CHANNEL) == ADC_AnalogWatchdog_Channel_14) || \
|
||||
((CHANNEL) == ADC_AnalogWatchdog_Channel_15) || \
|
||||
((CHANNEL) == ADC_AnalogWatchdog_Channel_16) || \
|
||||
((CHANNEL) == ADC_AnalogWatchdog_Channel_17) || \
|
||||
((CHANNEL) == ADC_AnalogWatchdog_Channel_18))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_sampling_times
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_SampleTime_1_5Cycles ((uint32_t)0x00000000)
|
||||
#define ADC_SampleTime_7_5Cycles ((uint32_t)0x00000001)
|
||||
#define ADC_SampleTime_13_5Cycles ((uint32_t)0x00000002)
|
||||
#define ADC_SampleTime_28_5Cycles ((uint32_t)0x00000003)
|
||||
#define ADC_SampleTime_41_5Cycles ((uint32_t)0x00000004)
|
||||
#define ADC_SampleTime_55_5Cycles ((uint32_t)0x00000005)
|
||||
#define ADC_SampleTime_71_5Cycles ((uint32_t)0x00000006)
|
||||
#define ADC_SampleTime_239_5Cycles ((uint32_t)0x00000007)
|
||||
|
||||
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1_5Cycles) || \
|
||||
((TIME) == ADC_SampleTime_7_5Cycles) || \
|
||||
((TIME) == ADC_SampleTime_13_5Cycles) || \
|
||||
((TIME) == ADC_SampleTime_28_5Cycles) || \
|
||||
((TIME) == ADC_SampleTime_41_5Cycles) || \
|
||||
((TIME) == ADC_SampleTime_55_5Cycles) || \
|
||||
((TIME) == ADC_SampleTime_71_5Cycles) || \
|
||||
((TIME) == ADC_SampleTime_239_5Cycles))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_thresholds
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_channels
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_Channel_0 ADC_CHSELR_CHSEL0
|
||||
#define ADC_Channel_1 ADC_CHSELR_CHSEL1
|
||||
#define ADC_Channel_2 ADC_CHSELR_CHSEL2
|
||||
#define ADC_Channel_3 ADC_CHSELR_CHSEL3
|
||||
#define ADC_Channel_4 ADC_CHSELR_CHSEL4
|
||||
#define ADC_Channel_5 ADC_CHSELR_CHSEL5
|
||||
#define ADC_Channel_6 ADC_CHSELR_CHSEL6
|
||||
#define ADC_Channel_7 ADC_CHSELR_CHSEL7
|
||||
#define ADC_Channel_8 ADC_CHSELR_CHSEL8
|
||||
#define ADC_Channel_9 ADC_CHSELR_CHSEL9
|
||||
#define ADC_Channel_10 ADC_CHSELR_CHSEL10
|
||||
#define ADC_Channel_11 ADC_CHSELR_CHSEL11
|
||||
#define ADC_Channel_12 ADC_CHSELR_CHSEL12
|
||||
#define ADC_Channel_13 ADC_CHSELR_CHSEL13
|
||||
#define ADC_Channel_14 ADC_CHSELR_CHSEL14
|
||||
#define ADC_Channel_15 ADC_CHSELR_CHSEL15
|
||||
#define ADC_Channel_16 ADC_CHSELR_CHSEL16
|
||||
#define ADC_Channel_17 ADC_CHSELR_CHSEL17
|
||||
#define ADC_Channel_18 ADC_CHSELR_CHSEL18
|
||||
|
||||
#define ADC_Channel_TempSensor ((uint32_t)ADC_Channel_16)
|
||||
#define ADC_Channel_Vrefint ((uint32_t)ADC_Channel_17)
|
||||
#define ADC_Channel_Vbat ((uint32_t)ADC_Channel_18)
|
||||
|
||||
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) != (uint32_t)RESET) && (((CHANNEL) & 0xFFF80000) == (uint32_t)RESET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_IT_ADRDY ADC_IER_ADRDYIE
|
||||
#define ADC_IT_EOSMP ADC_IER_EOSMPIE
|
||||
#define ADC_IT_EOC ADC_IER_EOCIE
|
||||
#define ADC_IT_EOSEQ ADC_IER_EOSEQIE
|
||||
#define ADC_IT_OVR ADC_IER_OVRIE
|
||||
#define ADC_IT_AWD ADC_IER_AWDIE
|
||||
|
||||
#define IS_ADC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET))
|
||||
|
||||
#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_ADRDY) || ((IT) == ADC_IT_EOSMP) || \
|
||||
((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_EOSEQ) || \
|
||||
((IT) == ADC_IT_OVR) || ((IT) == ADC_IT_AWD))
|
||||
|
||||
#define IS_ADC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_FLAG_ADRDY ADC_ISR_ADRDY
|
||||
#define ADC_FLAG_EOSMP ADC_ISR_EOSMP
|
||||
#define ADC_FLAG_EOC ADC_ISR_EOC
|
||||
#define ADC_FLAG_EOSEQ ADC_ISR_EOSEQ
|
||||
#define ADC_FLAG_OVR ADC_ISR_OVR
|
||||
#define ADC_FLAG_AWD ADC_ISR_AWD
|
||||
|
||||
#define ADC_FLAG_ADEN ((uint32_t)0x01000001)
|
||||
#define ADC_FLAG_ADDIS ((uint32_t)0x01000002)
|
||||
#define ADC_FLAG_ADSTART ((uint32_t)0x01000004)
|
||||
#define ADC_FLAG_ADSTP ((uint32_t)0x01000008)
|
||||
#define ADC_FLAG_ADCAL ((uint32_t)0x11000000)
|
||||
|
||||
#define IS_ADC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xEFFFFF60) == (uint32_t)RESET))
|
||||
|
||||
#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_ADRDY) || ((FLAG) == ADC_FLAG_EOSMP) || \
|
||||
((FLAG) == ADC_FLAG_EOC) || ((FLAG)== ADC_FLAG_EOSEQ) || \
|
||||
((FLAG) == ADC_FLAG_AWD) || ((FLAG)== ADC_FLAG_OVR) || \
|
||||
((FLAG) == ADC_FLAG_ADEN) || ((FLAG)== ADC_FLAG_ADDIS) || \
|
||||
((FLAG) == ADC_FLAG_ADSTART) || ((FLAG)== ADC_FLAG_ADSTP) || \
|
||||
((FLAG) == ADC_FLAG_ADCAL))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the ADC configuration to the default reset state *****/
|
||||
void ADC_DeInit(ADC_TypeDef* ADCx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
|
||||
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
|
||||
void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState NewState);
|
||||
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
|
||||
/* Power saving functions *****************************************************/
|
||||
void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
|
||||
/* Analog Watchdog configuration functions ************************************/
|
||||
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
|
||||
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog_Channel);
|
||||
void ADC_AnalogWatchdogSingleChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
|
||||
/* Temperature Sensor , Vrefint and Vbat management function ******************/
|
||||
void ADC_TempSensorCmd(FunctionalState NewState);
|
||||
void ADC_VrefintCmd(FunctionalState NewState);
|
||||
void ADC_VbatCmd(FunctionalState NewState);
|
||||
|
||||
/* Channels Configuration functions *******************************************/
|
||||
void ADC_ChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_Channel, uint32_t ADC_SampleTime);
|
||||
void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
uint32_t ADC_GetCalibrationFactor(ADC_TypeDef* ADCx);
|
||||
void ADC_StopOfConversion(ADC_TypeDef* ADCx);
|
||||
void ADC_StartOfConversion(ADC_TypeDef* ADCx);
|
||||
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
|
||||
|
||||
/* Regular Channels DMA Configuration functions *******************************/
|
||||
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState);
|
||||
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
|
||||
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
|
||||
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT);
|
||||
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F0XX_ADC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,300 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_cec.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file contains all the functions prototypes for the CEC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0XX_CEC_H
|
||||
#define __STM32F0XX_CEC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief CEC Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t CEC_SignalFreeTime; /*!< Specifies the CEC Signal Free Time configuration.
|
||||
This parameter can be a value of @ref CEC_Signal_Free_Time */
|
||||
uint32_t CEC_RxTolerance; /*!< Specifies the CEC Reception Tolerance.
|
||||
This parameter can be a value of @ref CEC_RxTolerance */
|
||||
uint32_t CEC_StopReception; /*!< Specifies the CEC Stop Reception.
|
||||
This parameter can be a value of @ref CEC_Stop_Reception */
|
||||
uint32_t CEC_BitRisingError; /*!< Specifies the CEC Bit Rising Error generation.
|
||||
This parameter can be a value of @ref CEC_Bit_Rising_Error_Generation */
|
||||
uint32_t CEC_LongBitPeriodError; /*!< Specifies the CEC Long Bit Error generation.
|
||||
This parameter can be a value of @ref CEC_Long_Bit_Error_Generation */
|
||||
uint32_t CEC_BRDNoGen; /*!< Specifies the CEC Broadcast Error generation.
|
||||
This parameter can be a value of @ref CEC_BDR_No_Gen */
|
||||
uint32_t CEC_SFTOption; /*!< Specifies the CEC Signal Free Time option.
|
||||
This parameter can be a value of @ref CEC_SFT_Option */
|
||||
|
||||
}CEC_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CEC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Signal_Free_Time
|
||||
* @{
|
||||
*/
|
||||
#define CEC_SignalFreeTime_Standard ((uint32_t)0x00000000) /*!< CEC Signal Free Time Standard */
|
||||
#define CEC_SignalFreeTime_1T ((uint32_t)0x00000001) /*!< CEC 1.5 nominal data bit periods */
|
||||
#define CEC_SignalFreeTime_2T ((uint32_t)0x00000002) /*!< CEC 2.5 nominal data bit periods */
|
||||
#define CEC_SignalFreeTime_3T ((uint32_t)0x00000003) /*!< CEC 3.5 nominal data bit periods */
|
||||
#define CEC_SignalFreeTime_4T ((uint32_t)0x00000004) /*!< CEC 4.5 nominal data bit periods */
|
||||
#define CEC_SignalFreeTime_5T ((uint32_t)0x00000005) /*!< CEC 5.5 nominal data bit periods */
|
||||
#define CEC_SignalFreeTime_6T ((uint32_t)0x00000006) /*!< CEC 6.5 nominal data bit periods */
|
||||
#define CEC_SignalFreeTime_7T ((uint32_t)0x00000007) /*!< CEC 7.5 nominal data bit periods */
|
||||
|
||||
#define IS_CEC_SIGNAL_FREE_TIME(TIME) (((TIME) == CEC_SignalFreeTime_Standard) || \
|
||||
((TIME) == CEC_SignalFreeTime_1T)|| \
|
||||
((TIME) == CEC_SignalFreeTime_2T)|| \
|
||||
((TIME) == CEC_SignalFreeTime_3T)|| \
|
||||
((TIME) == CEC_SignalFreeTime_4T)|| \
|
||||
((TIME) == CEC_SignalFreeTime_5T)|| \
|
||||
((TIME) == CEC_SignalFreeTime_6T)|| \
|
||||
((TIME) == CEC_SignalFreeTime_7T))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_RxTolerance
|
||||
* @{
|
||||
*/
|
||||
#define CEC_RxTolerance_Standard ((uint32_t)0x00000000) /*!< Standard Tolerance Margin */
|
||||
#define CEC_RxTolerance_Extended CEC_CFGR_RXTOL /*!< Extended Tolerance Margin */
|
||||
|
||||
#define IS_CEC_RX_TOLERANCE(TOLERANCE) (((TOLERANCE) == CEC_RxTolerance_Standard) || \
|
||||
((TOLERANCE) == CEC_RxTolerance_Extended))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Stop_Reception
|
||||
* @{
|
||||
*/
|
||||
#define CEC_StopReception_Off ((uint32_t)0x00000000) /*!< No RX Stop on bit Rising Error (BRE) */
|
||||
#define CEC_StopReception_On CEC_CFGR_BRESTP /*!< RX Stop on bit Rising Error (BRE) */
|
||||
|
||||
#define IS_CEC_STOP_RECEPTION(RECEPTION) (((RECEPTION) == CEC_StopReception_On) || \
|
||||
((RECEPTION) == CEC_StopReception_Off))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Bit_Rising_Error_Generation
|
||||
* @{
|
||||
*/
|
||||
#define CEC_BitRisingError_Off ((uint32_t)0x00000000) /*!< Bit Rising Error generation turned Off */
|
||||
#define CEC_BitRisingError_On CEC_CFGR_BREGEN /*!< Bit Rising Error generation turned On */
|
||||
|
||||
#define IS_CEC_BIT_RISING_ERROR(ERROR) (((ERROR) == CEC_BitRisingError_Off) || \
|
||||
((ERROR) == CEC_BitRisingError_On))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Long_Bit_Error_Generation
|
||||
* @{
|
||||
*/
|
||||
#define CEC_LongBitPeriodError_Off ((uint32_t)0x00000000) /*!< Long Bit Period Error generation turned Off */
|
||||
#define CEC_LongBitPeriodError_On CEC_CFGR_LREGEN /*!< Long Bit Period Error generation turned On */
|
||||
|
||||
#define IS_CEC_LONG_BIT_PERIOD_ERROR(ERROR) (((ERROR) == CEC_LongBitPeriodError_Off) || \
|
||||
((ERROR) == CEC_LongBitPeriodError_On))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BDR_No_Gen
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CEC_BRDNoGen_Off ((uint32_t)0x00000000) /*!< Broadcast Bit Rising Error generation turned Off */
|
||||
#define CEC_BRDNoGen_On CEC_CFGR_BRDNOGEN /*!< Broadcast Bit Rising Error generation turned On */
|
||||
|
||||
#define IS_CEC_BDR_NO_GEN_ERROR(ERROR) (((ERROR) == CEC_BRDNoGen_Off) || \
|
||||
((ERROR) == CEC_BRDNoGen_On))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_SFT_Option
|
||||
* @{
|
||||
*/
|
||||
#define CEC_SFTOption_Off ((uint32_t)0x00000000) /*!< SFT option turned Off */
|
||||
#define CEC_SFTOption_On CEC_CFGR_SFTOPT /*!< SFT option turned On */
|
||||
|
||||
#define IS_CEC_SFT_OPTION(OPTION) (((OPTION) == CEC_SFTOption_Off) || \
|
||||
((OPTION) == CEC_SFTOption_On))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Own_Address
|
||||
* @{
|
||||
*/
|
||||
#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Interrupt_Configuration_definition
|
||||
* @{
|
||||
*/
|
||||
#define CEC_IT_TXACKE CEC_IER_TXACKEIE
|
||||
#define CEC_IT_TXERR CEC_IER_TXERRIE
|
||||
#define CEC_IT_TXUDR CEC_IER_TXUDRIE
|
||||
#define CEC_IT_TXEND CEC_IER_TXENDIE
|
||||
#define CEC_IT_TXBR CEC_IER_TXBRIE
|
||||
#define CEC_IT_ARBLST CEC_IER_ARBLSTIE
|
||||
#define CEC_IT_RXACKE CEC_IER_RXACKEIE
|
||||
#define CEC_IT_LBPE CEC_IER_LBPEIE
|
||||
#define CEC_IT_SBPE CEC_IER_SBPEIE
|
||||
#define CEC_IT_BRE CEC_IER_BREIEIE
|
||||
#define CEC_IT_RXOVR CEC_IER_RXOVRIE
|
||||
#define CEC_IT_RXEND CEC_IER_RXENDIE
|
||||
#define CEC_IT_RXBR CEC_IER_RXBRIE
|
||||
|
||||
#define IS_CEC_IT(IT) ((((IT) & (uint32_t)0xFFFFE000) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TXACKE) || \
|
||||
((IT) == CEC_IT_TXERR)|| \
|
||||
((IT) == CEC_IT_TXUDR)|| \
|
||||
((IT) == CEC_IT_TXEND)|| \
|
||||
((IT) == CEC_IT_TXBR)|| \
|
||||
((IT) == CEC_IT_ARBLST)|| \
|
||||
((IT) == CEC_IT_RXACKE)|| \
|
||||
((IT) == CEC_IT_LBPE)|| \
|
||||
((IT) == CEC_IT_SBPE)|| \
|
||||
((IT) == CEC_IT_BRE)|| \
|
||||
((IT) == CEC_IT_RXOVR)|| \
|
||||
((IT) == CEC_IT_RXEND)|| \
|
||||
((IT) == CEC_IT_RXBR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_ISR_register_flags_definition
|
||||
* @{
|
||||
*/
|
||||
#define CEC_FLAG_TXACKE CEC_ISR_TXACKE
|
||||
#define CEC_FLAG_TXERR CEC_ISR_TXERR
|
||||
#define CEC_FLAG_TXUDR CEC_ISR_TXUDR
|
||||
#define CEC_FLAG_TXEND CEC_ISR_TXEND
|
||||
#define CEC_FLAG_TXBR CEC_ISR_TXBR
|
||||
#define CEC_FLAG_ARBLST CEC_ISR_ARBLST
|
||||
#define CEC_FLAG_RXACKE CEC_ISR_RXACKE
|
||||
#define CEC_FLAG_LBPE CEC_ISR_LBPE
|
||||
#define CEC_FLAG_SBPE CEC_ISR_SBPE
|
||||
#define CEC_FLAG_BRE CEC_ISR_BRE
|
||||
#define CEC_FLAG_RXOVR CEC_ISR_RXOVR
|
||||
#define CEC_FLAG_RXEND CEC_ISR_RXEND
|
||||
#define CEC_FLAG_RXBR CEC_ISR_RXBR
|
||||
|
||||
#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFE000) == 0x00) && ((FLAG) != 0x00))
|
||||
|
||||
#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_TXACKE) || \
|
||||
((FLAG) == CEC_FLAG_TXERR)|| \
|
||||
((FLAG) == CEC_FLAG_TXUDR)|| \
|
||||
((FLAG) == CEC_FLAG_TXEND)|| \
|
||||
((FLAG) == CEC_FLAG_TXBR)|| \
|
||||
((FLAG) == CEC_FLAG_ARBLST)|| \
|
||||
((FLAG) == CEC_FLAG_RXACKE)|| \
|
||||
((FLAG) == CEC_FLAG_LBPE)|| \
|
||||
((FLAG) == CEC_FLAG_SBPE)|| \
|
||||
((FLAG) == CEC_FLAG_BRE)|| \
|
||||
((FLAG) == CEC_FLAG_RXOVR)|| \
|
||||
((FLAG) == CEC_FLAG_RXEND)|| \
|
||||
((FLAG) == CEC_FLAG_RXBR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the CEC configuration to the default reset state *****/
|
||||
void CEC_DeInit(void);
|
||||
|
||||
/* CEC_Initialization and Configuration functions *****************************/
|
||||
void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
|
||||
void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct);
|
||||
void CEC_Cmd(FunctionalState NewState);
|
||||
void CEC_ListenModeCmd(FunctionalState NewState);
|
||||
void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
|
||||
void CEC_OwnAddressClear(void);
|
||||
|
||||
/* CEC_Data transfers functions ***********************************************/
|
||||
void CEC_SendData(uint8_t Data);
|
||||
uint8_t CEC_ReceiveData(void);
|
||||
void CEC_StartOfMessage(void);
|
||||
void CEC_EndOfMessage(void);
|
||||
|
||||
/* CEC_Interrupts and flags management functions ******************************/
|
||||
void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState);
|
||||
FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG);
|
||||
void CEC_ClearFlag(uint32_t CEC_FLAG);
|
||||
ITStatus CEC_GetITStatus(uint16_t CEC_IT);
|
||||
void CEC_ClearITPendingBit(uint16_t CEC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0XX_CEC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,243 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_comp.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file contains all the functions prototypes for the COMP firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0XX_COMP_H
|
||||
#define __STM32F0XX_COMP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief COMP Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator.
|
||||
This parameter can be a value of @ref COMP_InvertingInput */
|
||||
|
||||
uint32_t COMP_Output; /*!< Selects the output redirection of the comparator.
|
||||
This parameter can be a value of @ref COMP_Output */
|
||||
|
||||
uint32_t COMP_OutputPol; /*!< Selects the output polarity of the comparator.
|
||||
This parameter can be a value of @ref COMP_OutputPolarity */
|
||||
|
||||
uint32_t COMP_Hysteresis; /*!< Selects the hysteresis voltage of the comparator.
|
||||
This parameter can be a value of @ref COMP_Hysteresis */
|
||||
|
||||
uint32_t COMP_Mode; /*!< Selects the operating mode of the comparator
|
||||
and allows to adjust the speed/consumption.
|
||||
This parameter can be a value of @ref COMP_Mode */
|
||||
|
||||
}COMP_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup COMP_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define COMP_Selection_COMP1 ((uint32_t)0x00000000) /*!< COMP1 Selection */
|
||||
#define COMP_Selection_COMP2 ((uint32_t)0x00000010) /*!< COMP2 Selection */
|
||||
|
||||
#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \
|
||||
((PERIPH) == COMP_Selection_COMP2))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_InvertingInput
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
|
||||
#define COMP_InvertingInput_1_2VREFINT COMP_CSR_COMP1INSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */
|
||||
#define COMP_InvertingInput_3_4VREFINT COMP_CSR_COMP1INSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */
|
||||
#define COMP_InvertingInput_VREFINT ((uint32_t)0x00000030) /*!< VREFINT connected to comparator inverting input */
|
||||
#define COMP_InvertingInput_DAC1 COMP_CSR_COMP1INSEL_2 /*!< DAC1_OUT connected to comparator inverting input */
|
||||
#define COMP_InvertingInput_IO ((uint32_t)0x00000060) /*!< I/O (PA0 for COMP1 and PA2 for COMP2) connected to comparator inverting input */
|
||||
|
||||
#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
|
||||
((INPUT) == COMP_InvertingInput_1_2VREFINT) || \
|
||||
((INPUT) == COMP_InvertingInput_3_4VREFINT) || \
|
||||
((INPUT) == COMP_InvertingInput_VREFINT) || \
|
||||
((INPUT) == COMP_InvertingInput_DAC1) || \
|
||||
((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
|
||||
((INPUT) == COMP_InvertingInput_IO))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Output
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define COMP_Output_None ((uint32_t)0x00000000) /*!< COMP output isn't connected to other peripherals */
|
||||
#define COMP_Output_TIM1BKIN COMP_CSR_COMP1OUTSEL_0 /*!< COMP output connected to TIM1 Break Input (BKIN) */
|
||||
#define COMP_Output_TIM1IC1 COMP_CSR_COMP1OUTSEL_1 /*!< COMP output connected to TIM1 Input Capture 1 */
|
||||
#define COMP_Output_TIM1OCREFCLR ((uint32_t)0x00000300) /*!< COMP output connected to TIM1 OCREF Clear */
|
||||
#define COMP_Output_TIM2IC4 COMP_CSR_COMP1OUTSEL_2 /*!< COMP output connected to TIM2 Input Capture 4 */
|
||||
#define COMP_Output_TIM2OCREFCLR ((uint32_t)0x00000500) /*!< COMP output connected to TIM2 OCREF Clear */
|
||||
#define COMP_Output_TIM3IC1 ((uint32_t)0x00000600) /*!< COMP output connected to TIM3 Input Capture 1 */
|
||||
#define COMP_Output_TIM3OCREFCLR COMP_CSR_COMP1OUTSEL /*!< COMP output connected to TIM3 OCREF Clear */
|
||||
|
||||
|
||||
#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_Output_None) || \
|
||||
((OUTPUT) == COMP_Output_TIM1BKIN) || \
|
||||
((OUTPUT) == COMP_Output_TIM1IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM1OCREFCLR) || \
|
||||
((OUTPUT) == COMP_Output_TIM2IC4) || \
|
||||
((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \
|
||||
((OUTPUT) == COMP_Output_TIM3IC1) || \
|
||||
((OUTPUT) == COMP_Output_TIM3OCREFCLR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_OutputPolarity
|
||||
* @{
|
||||
*/
|
||||
#define COMP_OutputPol_NonInverted ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */
|
||||
#define COMP_OutputPol_Inverted COMP_CSR_COMP1POL /*!< COMP output on GPIO is inverted */
|
||||
|
||||
#define IS_COMP_OUTPUT_POL(POL) (((POL) == COMP_OutputPol_NonInverted) || \
|
||||
((POL) == COMP_OutputPol_Inverted))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Hysteresis
|
||||
* @{
|
||||
*/
|
||||
/* Please refer to the electrical characteristics in the device datasheet for
|
||||
the hysteresis level */
|
||||
#define COMP_Hysteresis_No 0x00000000 /*!< No hysteresis */
|
||||
#define COMP_Hysteresis_Low COMP_CSR_COMP1HYST_0 /*!< Hysteresis level low */
|
||||
#define COMP_Hysteresis_Medium COMP_CSR_COMP1HYST_1 /*!< Hysteresis level medium */
|
||||
#define COMP_Hysteresis_High COMP_CSR_COMP1HYST /*!< Hysteresis level high */
|
||||
|
||||
#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_Hysteresis_No) || \
|
||||
((HYSTERESIS) == COMP_Hysteresis_Low) || \
|
||||
((HYSTERESIS) == COMP_Hysteresis_Medium) || \
|
||||
((HYSTERESIS) == COMP_Hysteresis_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Mode
|
||||
* @{
|
||||
*/
|
||||
/* Please refer to the electrical characteristics in the device datasheet for
|
||||
the power consumption values */
|
||||
#define COMP_Mode_HighSpeed 0x00000000 /*!< High Speed */
|
||||
#define COMP_Mode_MediumSpeed COMP_CSR_COMP1MODE_0 /*!< Medium Speed */
|
||||
#define COMP_Mode_LowPower COMP_CSR_COMP1MODE_1 /*!< Low power mode */
|
||||
#define COMP_Mode_UltraLowPower COMP_CSR_COMP1MODE /*!< Ultra-low power mode */
|
||||
|
||||
#define IS_COMP_MODE(MODE) (((MODE) == COMP_Mode_UltraLowPower) || \
|
||||
((MODE) == COMP_Mode_LowPower) || \
|
||||
((MODE) == COMP_Mode_MediumSpeed) || \
|
||||
((MODE) == COMP_Mode_HighSpeed))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_OutputLevel
|
||||
* @{
|
||||
*/
|
||||
/* When output polarity is not inverted, comparator output is high when
|
||||
the non-inverting input is at a higher voltage than the inverting input */
|
||||
#define COMP_OutputLevel_High COMP_CSR_COMP1OUT
|
||||
/* When output polarity is not inverted, comparator output is low when
|
||||
the non-inverting input is at a lower voltage than the inverting input*/
|
||||
#define COMP_OutputLevel_Low ((uint32_t)0x00000000)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the COMP configuration to the default reset state ****/
|
||||
void COMP_DeInit(void);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct);
|
||||
void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct);
|
||||
void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState);
|
||||
void COMP_SwitchCmd(FunctionalState NewState);
|
||||
uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection);
|
||||
|
||||
/* Window mode control function ***********************************************/
|
||||
void COMP_WindowCmd(FunctionalState NewState);
|
||||
|
||||
/* COMP configuration locking function ****************************************/
|
||||
void COMP_LockConfig(uint32_t COMP_Selection);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F0XX_COMP_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_crc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file contains all the functions prototypes for the CRC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0XX_CRC_H
|
||||
#define __STM32F0XX_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!< Includes ----------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
#define CRC_ReverseInputData_No ((uint32_t)0x00000000) /*!< No reverse operation of Input Data */
|
||||
#define CRC_ReverseInputData_8bits CRC_CR_REV_IN_0 /*!< Reverse operation of Input Data on 8 bits */
|
||||
#define CRC_ReverseInputData_16bits CRC_CR_REV_IN_1 /*!< Reverse operation of Input Data on 16 bits */
|
||||
#define CRC_ReverseInputData_32bits CRC_CR_REV_IN /*!< Reverse operation of Input Data on 32 bits */
|
||||
|
||||
#define IS_CRC_REVERSE_INPUT_DATA(DATA) (((DATA) == CRC_ReverseInputData_No) || \
|
||||
((DATA) == CRC_ReverseInputData_8bits) || \
|
||||
((DATA) == CRC_ReverseInputData_16bits) || \
|
||||
((DATA) == CRC_ReverseInputData_32bits))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Configuration of the CRC computation unit **********************************/
|
||||
void CRC_DeInit(void);
|
||||
void CRC_ResetDR(void);
|
||||
void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData);
|
||||
void CRC_ReverseOutputDataCmd(FunctionalState NewState);
|
||||
void CRC_SetInitRegister(uint32_t CRC_InitValue);
|
||||
|
||||
/* CRC computation ************************************************************/
|
||||
uint32_t CRC_CalcCRC(uint32_t CRC_Data);
|
||||
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
|
||||
uint32_t CRC_GetCRC(void);
|
||||
|
||||
/* Independent register (IDR) access (write/read) *****************************/
|
||||
void CRC_SetIDRegister(uint8_t CRC_IDValue);
|
||||
uint8_t CRC_GetIDRegister(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0XX_CRC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,207 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_dac.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file contains all the functions prototypes for the DAC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0XX_DAC_H
|
||||
#define __STM32F0XX_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief DAC Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_Trigger */
|
||||
|
||||
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_OutputBuffer */
|
||||
}DAC_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Trigger
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
|
||||
((TRIGGER) == DAC_Trigger_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T3_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T15_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_Ext_IT9) || \
|
||||
((TRIGGER) == DAC_Trigger_Software))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_OutputBuffer
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
|
||||
#define DAC_OutputBuffer_Disable DAC_CR_BOFF1
|
||||
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
|
||||
((STATE) == DAC_OutputBuffer_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Channel_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Channel_1 ((uint32_t)0x00000000)
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data_alignment
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Align_12b_R ((uint32_t)0x00000000)
|
||||
#define DAC_Align_12b_L ((uint32_t)0x00000004)
|
||||
#define DAC_Align_8b_R ((uint32_t)0x00000008)
|
||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
|
||||
((ALIGN) == DAC_Align_12b_L) || \
|
||||
((ALIGN) == DAC_Align_8b_R))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_IT_DMAUDR DAC_SR_DMAUDR1
|
||||
#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DAC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_FLAG_DMAUDR DAC_SR_DMAUDR1
|
||||
|
||||
#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the DAC configuration to the default reset state *****/
|
||||
void DAC_DeInit(void);
|
||||
|
||||
/* DAC channels configuration: trigger, output buffer, data format functions */
|
||||
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
|
||||
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
|
||||
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
|
||||
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
|
||||
|
||||
/* DMA management functions ***************************************************/
|
||||
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
|
||||
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
|
||||
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
|
||||
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
|
||||
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F0XX_DAC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,105 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_dbgmcu.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file contains all the functions prototypes for the DBGMCU firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0XX_DBGMCU_H
|
||||
#define __STM32F0XX_DBGMCU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DBGMCU
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
|
||||
/** @defgroup DBGMCU_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DBGMCU_STOP DBGMCU_CR_DBG_STOP
|
||||
#define DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY
|
||||
#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF9) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
#define DBGMCU_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP
|
||||
#define DBGMCU_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP
|
||||
#define DBGMCU_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP
|
||||
#define DBGMCU_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP
|
||||
#define DBGMCU_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP
|
||||
#define DBGMCU_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP
|
||||
#define DBGMCU_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
|
||||
#define DBGMCU_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT
|
||||
#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFFDFE2EC) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
#define DBGMCU_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP
|
||||
#define DBGMCU_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP
|
||||
#define DBGMCU_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP
|
||||
#define DBGMCU_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP
|
||||
#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8F7FF) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Device and Revision ID management functions ********************************/
|
||||
uint32_t DBGMCU_GetREVID(void);
|
||||
uint32_t DBGMCU_GetDEVID(void);
|
||||
|
||||
/* Peripherals Configuration functions ****************************************/
|
||||
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||
void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||
void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0XX_DBGMCU_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,351 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_dma.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file contains all the functions prototypes for the DMA firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0XX_DMA_H
|
||||
#define __STM32F0XX_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief DMA Init structures definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
|
||||
|
||||
uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
|
||||
|
||||
uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
|
||||
This parameter can be a value of @ref DMA_data_transfer_direction */
|
||||
|
||||
uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
|
||||
The data unit is equal to the configuration set in DMA_PeripheralDataSize
|
||||
or DMA_MemoryDataSize members depending in the transfer direction */
|
||||
|
||||
uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
|
||||
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
|
||||
|
||||
uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
|
||||
This parameter can be a value of @ref DMA_memory_incremented_mode */
|
||||
|
||||
uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_peripheral_data_size */
|
||||
|
||||
uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_memory_data_size */
|
||||
|
||||
uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_circular_normal_mode
|
||||
@note: The circular buffer mode cannot be used if the memory-to-memory
|
||||
data transfer is configured on the selected Channel */
|
||||
|
||||
uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_priority_level */
|
||||
|
||||
uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
|
||||
This parameter can be a value of @ref DMA_memory_to_memory */
|
||||
}DMA_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
|
||||
((PERIPH) == DMA1_Channel2) || \
|
||||
((PERIPH) == DMA1_Channel3) || \
|
||||
((PERIPH) == DMA1_Channel4) || \
|
||||
((PERIPH) == DMA1_Channel5))
|
||||
|
||||
/** @defgroup DMA_data_transfer_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
|
||||
#define DMA_DIR_PeripheralDST DMA_CCR_DIR
|
||||
|
||||
#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \
|
||||
((DIR) == DMA_DIR_PeripheralDST))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_peripheral_incremented_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
|
||||
#define DMA_PeripheralInc_Enable DMA_CCR_PINC
|
||||
|
||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \
|
||||
((STATE) == DMA_PeripheralInc_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_memory_incremented_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
|
||||
#define DMA_MemoryInc_Enable DMA_CCR_MINC
|
||||
|
||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \
|
||||
((STATE) == DMA_MemoryInc_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_peripheral_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0
|
||||
#define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1
|
||||
|
||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
|
||||
((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
|
||||
((SIZE) == DMA_PeripheralDataSize_Word))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_memory_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0
|
||||
#define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1
|
||||
|
||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
|
||||
((SIZE) == DMA_MemoryDataSize_HalfWord) || \
|
||||
((SIZE) == DMA_MemoryDataSize_Word))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_circular_normal_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_Mode_Normal ((uint32_t)0x00000000)
|
||||
#define DMA_Mode_Circular DMA_CCR_CIRC
|
||||
|
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_priority_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_Priority_VeryHigh DMA_CCR_PL
|
||||
#define DMA_Priority_High DMA_CCR_PL_1
|
||||
#define DMA_Priority_Medium DMA_CCR_PL_0
|
||||
#define DMA_Priority_Low ((uint32_t)0x00000000)
|
||||
|
||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
|
||||
((PRIORITY) == DMA_Priority_High) || \
|
||||
((PRIORITY) == DMA_Priority_Medium) || \
|
||||
((PRIORITY) == DMA_Priority_Low))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_memory_to_memory
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_M2M_Disable ((uint32_t)0x00000000)
|
||||
#define DMA_M2M_Enable DMA_CCR_MEM2MEM
|
||||
|
||||
#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_IT_TC DMA_CCR_TCIE
|
||||
#define DMA_IT_HT DMA_CCR_HTIE
|
||||
#define DMA_IT_TE DMA_CCR_TEIE
|
||||
|
||||
#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
#define DMA1_IT_GL1 DMA_ISR_GIF1
|
||||
#define DMA1_IT_TC1 DMA_ISR_TCIF1
|
||||
#define DMA1_IT_HT1 DMA_ISR_HTIF1
|
||||
#define DMA1_IT_TE1 DMA_ISR_TEIF1
|
||||
#define DMA1_IT_GL2 DMA_ISR_GIF2
|
||||
#define DMA1_IT_TC2 DMA_ISR_TCIF2
|
||||
#define DMA1_IT_HT2 DMA_ISR_HTIF2
|
||||
#define DMA1_IT_TE2 DMA_ISR_TEIF2
|
||||
#define DMA1_IT_GL3 DMA_ISR_GIF3
|
||||
#define DMA1_IT_TC3 DMA_ISR_TCIF3
|
||||
#define DMA1_IT_HT3 DMA_ISR_HTIF3
|
||||
#define DMA1_IT_TE3 DMA_ISR_TEIF3
|
||||
#define DMA1_IT_GL4 DMA_ISR_GIF4
|
||||
#define DMA1_IT_TC4 DMA_ISR_TCIF4
|
||||
#define DMA1_IT_HT4 DMA_ISR_HTIF4
|
||||
#define DMA1_IT_TE4 DMA_ISR_TEIF4
|
||||
#define DMA1_IT_GL5 DMA_ISR_GIF5
|
||||
#define DMA1_IT_TC5 DMA_ISR_TCIF5
|
||||
#define DMA1_IT_HT5 DMA_ISR_HTIF5
|
||||
#define DMA1_IT_TE5 DMA_ISR_TEIF5
|
||||
|
||||
#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0xFFF00000) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
|
||||
((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
|
||||
((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
|
||||
((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
|
||||
((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
|
||||
((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
|
||||
((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
|
||||
((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
|
||||
((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
|
||||
((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_flags_definition
|
||||
* @{
|
||||
*/
|
||||
#define DMA1_FLAG_GL1 DMA_ISR_GIF1
|
||||
#define DMA1_FLAG_TC1 DMA_ISR_TCIF1
|
||||
#define DMA1_FLAG_HT1 DMA_ISR_HTIF1
|
||||
#define DMA1_FLAG_TE1 DMA_ISR_TEIF1
|
||||
#define DMA1_FLAG_GL2 DMA_ISR_GIF2
|
||||
#define DMA1_FLAG_TC2 DMA_ISR_TCIF2
|
||||
#define DMA1_FLAG_HT2 DMA_ISR_HTIF2
|
||||
#define DMA1_FLAG_TE2 DMA_ISR_TEIF2
|
||||
#define DMA1_FLAG_GL3 DMA_ISR_GIF3
|
||||
#define DMA1_FLAG_TC3 DMA_ISR_TCIF3
|
||||
#define DMA1_FLAG_HT3 DMA_ISR_HTIF3
|
||||
#define DMA1_FLAG_TE3 DMA_ISR_TEIF3
|
||||
#define DMA1_FLAG_GL4 DMA_ISR_GIF4
|
||||
#define DMA1_FLAG_TC4 DMA_ISR_TCIF4
|
||||
#define DMA1_FLAG_HT4 DMA_ISR_HTIF4
|
||||
#define DMA1_FLAG_TE4 DMA_ISR_TEIF4
|
||||
#define DMA1_FLAG_GL5 DMA_ISR_GIF5
|
||||
#define DMA1_FLAG_TC5 DMA_ISR_TCIF5
|
||||
#define DMA1_FLAG_HT5 DMA_ISR_HTIF5
|
||||
#define DMA1_FLAG_TE5 DMA_ISR_TEIF5
|
||||
|
||||
#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0xFFF00000) == 0x00) && ((FLAG) != 0x00))
|
||||
|
||||
#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
|
||||
((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
|
||||
((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
|
||||
((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
|
||||
((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
|
||||
((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
|
||||
((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
|
||||
((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
|
||||
((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
|
||||
((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Buffer_Size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the DMA configuration to the default reset state ******/
|
||||
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
|
||||
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
|
||||
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
|
||||
|
||||
/* Data Counter functions******************************************************/
|
||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
|
||||
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
|
||||
FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
|
||||
void DMA_ClearFlag(uint32_t DMA_FLAG);
|
||||
ITStatus DMA_GetITStatus(uint32_t DMA_IT);
|
||||
void DMA_ClearITPendingBit(uint32_t DMA_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F0XX_DMA_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,194 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_exti.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file contains all the functions prototypes for the EXTI
|
||||
* firmware library
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0XX_EXTI_H
|
||||
#define __STM32F0XX_EXTI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief EXTI mode enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Mode_Interrupt = 0x00,
|
||||
EXTI_Mode_Event = 0x04
|
||||
}EXTIMode_TypeDef;
|
||||
|
||||
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
|
||||
|
||||
/**
|
||||
* @brief EXTI Trigger enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Trigger_Rising = 0x08,
|
||||
EXTI_Trigger_Falling = 0x0C,
|
||||
EXTI_Trigger_Rising_Falling = 0x10
|
||||
}EXTITrigger_TypeDef;
|
||||
|
||||
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
|
||||
((TRIGGER) == EXTI_Trigger_Falling) || \
|
||||
((TRIGGER) == EXTI_Trigger_Rising_Falling))
|
||||
/**
|
||||
* @brief EXTI Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
|
||||
This parameter can be any combination of @ref EXTI_Lines */
|
||||
|
||||
EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTIMode_TypeDef */
|
||||
|
||||
EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTIMode_TypeDef */
|
||||
|
||||
FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
}EXTI_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup EXTI_Lines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EXTI_Line0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */
|
||||
#define EXTI_Line1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */
|
||||
#define EXTI_Line2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */
|
||||
#define EXTI_Line3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */
|
||||
#define EXTI_Line4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */
|
||||
#define EXTI_Line5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */
|
||||
#define EXTI_Line6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */
|
||||
#define EXTI_Line7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */
|
||||
#define EXTI_Line8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */
|
||||
#define EXTI_Line9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */
|
||||
#define EXTI_Line10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */
|
||||
#define EXTI_Line11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */
|
||||
#define EXTI_Line12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */
|
||||
#define EXTI_Line13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */
|
||||
#define EXTI_Line14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */
|
||||
#define EXTI_Line15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */
|
||||
#define EXTI_Line16 ((uint32_t)0x00010000) /*!< External interrupt line 16
|
||||
Connected to the PVD Output */
|
||||
#define EXTI_Line17 ((uint32_t)0x00020000) /*!< Internal interrupt line 17
|
||||
Connected to the RTC Alarm
|
||||
event */
|
||||
#define EXTI_Line19 ((uint32_t)0x00080000) /*!< Internal interrupt line 19
|
||||
Connected to the RTC Tamper
|
||||
and Time Stamp events */
|
||||
#define EXTI_Line21 ((uint32_t)0x00200000) /*!< Internal interrupt line 21
|
||||
Connected to the Comparator 1
|
||||
event */
|
||||
#define EXTI_Line22 ((uint32_t)0x00400000) /*!< Internal interrupt line 22
|
||||
Connected to the Comparator 2
|
||||
event */
|
||||
#define EXTI_Line23 ((uint32_t)0x00800000) /*!< Internal interrupt line 23
|
||||
Connected to the I2C1 wakeup
|
||||
event */
|
||||
#define EXTI_Line25 ((uint32_t)0x02000000) /*!< Internal interrupt line 25
|
||||
Connected to the USART1 wakeup
|
||||
event */
|
||||
#define EXTI_Line27 ((uint32_t)0x08000000) /*!< Internal interrupt line 27
|
||||
Connected to the CEC wakeup
|
||||
event */
|
||||
|
||||
#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xF5140000) == 0x00) && ((LINE) != (uint16_t)0x00))
|
||||
|
||||
#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
|
||||
((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
|
||||
((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
|
||||
((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
|
||||
((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
|
||||
((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
|
||||
((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
|
||||
((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
|
||||
((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
|
||||
((LINE) == EXTI_Line19) || ((LINE) == EXTI_Line21) || \
|
||||
((LINE) == EXTI_Line22))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Function used to set the EXTI configuration to the default reset state *****/
|
||||
void EXTI_DeInit(void);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
|
||||
void EXTI_ClearFlag(uint32_t EXTI_Line);
|
||||
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
|
||||
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0XX_EXTI_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_flash.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file contains all the functions prototypes for the FLASH
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0XX_FLASH_H
|
||||
#define __STM32F0XX_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Status
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_BUSY = 1,
|
||||
FLASH_ERROR_WRP,
|
||||
FLASH_ERROR_PROGRAM,
|
||||
FLASH_COMPLETE,
|
||||
FLASH_TIMEOUT
|
||||
}FLASH_Status;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Latency
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
|
||||
#define FLASH_Latency_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */
|
||||
|
||||
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
|
||||
((LATENCY) == FLASH_Latency_1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of programming interrupt source */
|
||||
#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error interrupt source */
|
||||
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0800FFFF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_DATA_ADDRESS
|
||||
* @{
|
||||
*/
|
||||
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Option_Bytes_Write_Protection
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
#define OB_WRP_Pages0to3 ((uint32_t)0x00000001) /* Write protection of page 0 to 3 */
|
||||
#define OB_WRP_Pages4to7 ((uint32_t)0x00000002) /* Write protection of page 4 to 7 */
|
||||
#define OB_WRP_Pages8to11 ((uint32_t)0x00000004) /* Write protection of page 8 to 11 */
|
||||
#define OB_WRP_Pages12to15 ((uint32_t)0x00000008) /* Write protection of page 12 to 15 */
|
||||
#define OB_WRP_Pages16to19 ((uint32_t)0x00000010) /* Write protection of page 16 to 19 */
|
||||
#define OB_WRP_Pages20to23 ((uint32_t)0x00000020) /* Write protection of page 20 to 23 */
|
||||
#define OB_WRP_Pages24to27 ((uint32_t)0x00000040) /* Write protection of page 24 to 27 */
|
||||
#define OB_WRP_Pages28to31 ((uint32_t)0x00000080) /* Write protection of page 28 to 31 */
|
||||
#define OB_WRP_Pages32to35 ((uint32_t)0x00000100) /* Write protection of page 32 to 35 */
|
||||
#define OB_WRP_Pages36to39 ((uint32_t)0x00000200) /* Write protection of page 36 to 39 */
|
||||
#define OB_WRP_Pages40to43 ((uint32_t)0x00000400) /* Write protection of page 40 to 43 */
|
||||
#define OB_WRP_Pages44to47 ((uint32_t)0x00000800) /* Write protection of page 44 to 47 */
|
||||
#define OB_WRP_Pages48to51 ((uint32_t)0x00001000) /* Write protection of page 48 to 51 */
|
||||
#define OB_WRP_Pages52to55 ((uint32_t)0x00002000) /* Write protection of page 52 to 55 */
|
||||
#define OB_WRP_Pages56to59 ((uint32_t)0x00004000) /* Write protection of page 56 to 59 */
|
||||
#define OB_WRP_Pages60to63 ((uint32_t)0x00008000) /* Write protection of page 60 to 63 */
|
||||
|
||||
#define OB_WRP_AllPages ((uint32_t)0x0000FFFF) /*!< Write protection of all Sectors */
|
||||
|
||||
#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Option_Bytes_Read_Protection
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH_Read Protection Level
|
||||
*/
|
||||
#define OB_RDP_Level_0 ((uint8_t)0xAA)
|
||||
#define OB_RDP_Level_1 ((uint8_t)0xBB)
|
||||
/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2
|
||||
it's no more possible to go back to level 1 or 0 */
|
||||
|
||||
#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
|
||||
((LEVEL) == OB_RDP_Level_1))/*||\
|
||||
((LEVEL) == OB_RDP_Level_2))*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Option_Bytes_IWatchdog
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */
|
||||
#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
|
||||
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Option_Bytes_nRST_STOP
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_STOP_NoRST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
|
||||
#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
|
||||
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Option_Bytes_nRST_STDBY
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_STDBY_NoRST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
|
||||
#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
|
||||
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Option_Bytes_BOOT1
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */
|
||||
#define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */
|
||||
#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Option_Bytes_VDDA_Analog_Monitoring
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_VDDA_ANALOG_ON ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source ON */
|
||||
#define OB_VDDA_ANALOG_OFF ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source OFF */
|
||||
|
||||
#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Option_Bytes_SRAM_Parity_Enable
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_SRAM_PARITY_SET ((uint8_t)0x00) /*!< SRAM parity enable Set */
|
||||
#define OB_SRAM_PARITY_RESET ((uint8_t)0x40) /*!< SRAM parity enable reset */
|
||||
|
||||
#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
|
||||
#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
|
||||
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
|
||||
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */
|
||||
|
||||
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFC3) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||
|
||||
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \
|
||||
((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Timeout_definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x000B0000)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/**
|
||||
* @brief FLASH memory functions that can be executed from FLASH.
|
||||
*/
|
||||
/* FLASH Interface configuration functions ************************************/
|
||||
void FLASH_SetLatency(uint32_t FLASH_Latency);
|
||||
void FLASH_PrefetchBufferCmd(FunctionalState NewState);
|
||||
FlagStatus FLASH_GetPrefetchBufferStatus(void);
|
||||
|
||||
/* FLASH Memory Programming functions *****************************************/
|
||||
void FLASH_Unlock(void);
|
||||
void FLASH_Lock(void);
|
||||
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
|
||||
FLASH_Status FLASH_EraseAllPages(void);
|
||||
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
|
||||
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
|
||||
|
||||
/* FLASH Option Bytes Programming functions *****************************************/
|
||||
void FLASH_OB_Unlock(void);
|
||||
void FLASH_OB_Lock(void);
|
||||
void FLASH_OB_Launch(void);
|
||||
FLASH_Status FLASH_OB_Erase(void);
|
||||
FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP);
|
||||
FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
|
||||
FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
|
||||
FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
|
||||
FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
|
||||
FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity);
|
||||
FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
|
||||
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
|
||||
uint8_t FLASH_OB_GetUser(void);
|
||||
uint32_t FLASH_OB_GetWRP(void);
|
||||
FlagStatus FLASH_OB_GetRDP(void);
|
||||
|
||||
/* FLASH Interrupts and flags management functions **********************************/
|
||||
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
|
||||
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
|
||||
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
|
||||
FLASH_Status FLASH_GetStatus(void);
|
||||
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0XX_FLASH_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,350 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file contains all the functions prototypes for the GPIO
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0XX_GPIO_H
|
||||
#define __STM32F0XX_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
|
||||
((PERIPH) == GPIOB) || \
|
||||
((PERIPH) == GPIOC) || \
|
||||
((PERIPH) == GPIOD) || \
|
||||
((PERIPH) == GPIOF))
|
||||
|
||||
#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
|
||||
((PERIPH) == GPIOB))
|
||||
|
||||
/** @defgroup Configuration_Mode_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
|
||||
GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
|
||||
GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
|
||||
GPIO_Mode_AN = 0x03 /*!< GPIO Analog In/Out Mode */
|
||||
}GPIOMode_TypeDef;
|
||||
|
||||
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \
|
||||
((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Output_type_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_OType_PP = 0x00,
|
||||
GPIO_OType_OD = 0x01
|
||||
}GPIOOType_TypeDef;
|
||||
|
||||
#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Output_Maximum_frequency_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Speed_Level_1 = 0x01, /*!< Medium Speed */
|
||||
GPIO_Speed_Level_2 = 0x02, /*!< Fast Speed */
|
||||
GPIO_Speed_Level_3 = 0x03 /*!< High Speed */
|
||||
}GPIOSpeed_TypeDef;
|
||||
|
||||
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \
|
||||
((SPEED) == GPIO_Speed_Level_3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PuPd_NOPULL = 0x00,
|
||||
GPIO_PuPd_UP = 0x01,
|
||||
GPIO_PuPd_DOWN = 0x02
|
||||
}GPIOPuPd_TypeDef;
|
||||
|
||||
#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
|
||||
((PUPD) == GPIO_PuPd_DOWN))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Bit_SET_and_Bit_RESET_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
Bit_RESET = 0,
|
||||
Bit_SET
|
||||
}BitAction;
|
||||
|
||||
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins_define */
|
||||
|
||||
GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIOMode_TypeDef */
|
||||
|
||||
GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIOSpeed_TypeDef */
|
||||
|
||||
GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
|
||||
This parameter can be a value of @ref GPIOOType_TypeDef */
|
||||
|
||||
GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
|
||||
This parameter can be a value of @ref GPIOPuPd_TypeDef */
|
||||
}GPIO_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pins_define
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
|
||||
#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
|
||||
#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
|
||||
#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
|
||||
#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
|
||||
#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
|
||||
#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
|
||||
#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
|
||||
#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
|
||||
#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
|
||||
#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
|
||||
#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
|
||||
#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
|
||||
#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
|
||||
#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
|
||||
#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
|
||||
#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
|
||||
|
||||
#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
|
||||
|
||||
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
|
||||
((PIN) == GPIO_Pin_1) || \
|
||||
((PIN) == GPIO_Pin_2) || \
|
||||
((PIN) == GPIO_Pin_3) || \
|
||||
((PIN) == GPIO_Pin_4) || \
|
||||
((PIN) == GPIO_Pin_5) || \
|
||||
((PIN) == GPIO_Pin_6) || \
|
||||
((PIN) == GPIO_Pin_7) || \
|
||||
((PIN) == GPIO_Pin_8) || \
|
||||
((PIN) == GPIO_Pin_9) || \
|
||||
((PIN) == GPIO_Pin_10) || \
|
||||
((PIN) == GPIO_Pin_11) || \
|
||||
((PIN) == GPIO_Pin_12) || \
|
||||
((PIN) == GPIO_Pin_13) || \
|
||||
((PIN) == GPIO_Pin_14) || \
|
||||
((PIN) == GPIO_Pin_15))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Pin_sources
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PinSource0 ((uint8_t)0x00)
|
||||
#define GPIO_PinSource1 ((uint8_t)0x01)
|
||||
#define GPIO_PinSource2 ((uint8_t)0x02)
|
||||
#define GPIO_PinSource3 ((uint8_t)0x03)
|
||||
#define GPIO_PinSource4 ((uint8_t)0x04)
|
||||
#define GPIO_PinSource5 ((uint8_t)0x05)
|
||||
#define GPIO_PinSource6 ((uint8_t)0x06)
|
||||
#define GPIO_PinSource7 ((uint8_t)0x07)
|
||||
#define GPIO_PinSource8 ((uint8_t)0x08)
|
||||
#define GPIO_PinSource9 ((uint8_t)0x09)
|
||||
#define GPIO_PinSource10 ((uint8_t)0x0A)
|
||||
#define GPIO_PinSource11 ((uint8_t)0x0B)
|
||||
#define GPIO_PinSource12 ((uint8_t)0x0C)
|
||||
#define GPIO_PinSource13 ((uint8_t)0x0D)
|
||||
#define GPIO_PinSource14 ((uint8_t)0x0E)
|
||||
#define GPIO_PinSource15 ((uint8_t)0x0F)
|
||||
|
||||
#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
|
||||
((PINSOURCE) == GPIO_PinSource1) || \
|
||||
((PINSOURCE) == GPIO_PinSource2) || \
|
||||
((PINSOURCE) == GPIO_PinSource3) || \
|
||||
((PINSOURCE) == GPIO_PinSource4) || \
|
||||
((PINSOURCE) == GPIO_PinSource5) || \
|
||||
((PINSOURCE) == GPIO_PinSource6) || \
|
||||
((PINSOURCE) == GPIO_PinSource7) || \
|
||||
((PINSOURCE) == GPIO_PinSource8) || \
|
||||
((PINSOURCE) == GPIO_PinSource9) || \
|
||||
((PINSOURCE) == GPIO_PinSource10) || \
|
||||
((PINSOURCE) == GPIO_PinSource11) || \
|
||||
((PINSOURCE) == GPIO_PinSource12) || \
|
||||
((PINSOURCE) == GPIO_PinSource13) || \
|
||||
((PINSOURCE) == GPIO_PinSource14) || \
|
||||
((PINSOURCE) == GPIO_PinSource15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Alternate_function_selection_define
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF_0 ((uint8_t)0x00) /* WKUP, EVENTOUT, TIM15, SPI1, TIM17,
|
||||
MCO, SWDAT, SWCLK, TIM14, BOOT,
|
||||
USART1, CEC, IR_OUT, SPI2 */
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF_1 ((uint8_t)0x01) /* USART2, CEC, Tim3, USART1, USART2,
|
||||
EVENTOUT, I2C1, I2C2, TIM15 */
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF_2 ((uint8_t)0x02) /* TIM2, TIM1, EVENTOUT, TIM16, TIM17 */
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF_3 ((uint8_t)0x03) /* TS, I2C1, TIM15, EVENTOUT */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF_4 ((uint8_t)0x04) /* TIM14 */
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF_5 ((uint8_t)0x05) /* TIM16, TIM17 */
|
||||
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF_6 ((uint8_t)0x06) /* EVENTOUT */
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF_7 ((uint8_t)0x07) /* COMP1 OUT and COMP2 OUT */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_0) || ((AF) == GPIO_AF_1) || \
|
||||
((AF) == GPIO_AF_2) || ((AF) == GPIO_AF_3) || \
|
||||
((AF) == GPIO_AF_4) || ((AF) == GPIO_AF_5) || \
|
||||
((AF) == GPIO_AF_6) || ((AF) == GPIO_AF_7))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Speed_Legacy
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_Speed_10MHz GPIO_Speed_Level_1 /*!< Fast Speed:10MHz */
|
||||
#define GPIO_Speed_2MHz GPIO_Speed_Level_2 /*!< Medium Speed:2MHz */
|
||||
#define GPIO_Speed_50MHz GPIO_Speed_Level_3 /*!< High Speed:50MHz */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Function used to set the GPIO configuration to the default reset state *****/
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
|
||||
/* GPIO Read and Write functions **********************************************/
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
|
||||
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
|
||||
|
||||
/* GPIO Alternate functions configuration functions ***************************/
|
||||
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0XX_GPIO_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,478 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file contains all the functions prototypes for the I2C firmware
|
||||
* library
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0XX_I2C_H
|
||||
#define __STM32F0XX_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief I2C Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t I2C_Timing; /*!< Specifies the I2C_TIMINGR_register value.
|
||||
This parameter must be set by referring to I2C_Timing_Config_Tool*/
|
||||
|
||||
uint32_t I2C_AnalogFilter; /*!< Enables or disables analog noise filter.
|
||||
This parameter can be a value of @ref I2C_Analog_Filter*/
|
||||
|
||||
uint32_t I2C_DigitalFilter; /*!< Configures the digital noise filter.
|
||||
This parameter can be a number between 0x00 and 0x0F*/
|
||||
|
||||
uint32_t I2C_Mode; /*!< Specifies the I2C mode.
|
||||
This parameter can be a value of @ref I2C_mode*/
|
||||
|
||||
uint32_t I2C_OwnAddress1; /*!< Specifies the device own address 1.
|
||||
This parameter can be a 7-bit or 10-bit address*/
|
||||
|
||||
uint32_t I2C_Ack; /*!< Enables or disables the acknowledgement.
|
||||
This parameter can be a value of @ref I2C_acknowledgement*/
|
||||
|
||||
uint32_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
|
||||
This parameter can be a value of @ref I2C_acknowledged_address*/
|
||||
}I2C_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
|
||||
/** @defgroup I2C_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
|
||||
((PERIPH) == I2C2))
|
||||
|
||||
#define IS_I2C_1_PERIPH(PERIPH) ((PERIPH) == I2C1)
|
||||
|
||||
/** @defgroup I2C_Analog_Filter
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_AnalogFilter_Enable ((uint32_t)0x00000000)
|
||||
#define I2C_AnalogFilter_Disable I2C_CR1_ANFOFF
|
||||
|
||||
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_AnalogFilter_Enable) || \
|
||||
((FILTER) == I2C_AnalogFilter_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Digital_Filter
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Mode_I2C ((uint32_t)0x00000000)
|
||||
#define I2C_Mode_SMBusDevice I2C_CR1_SMBDEN
|
||||
#define I2C_Mode_SMBusHost I2C_CR1_SMBHEN
|
||||
|
||||
#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
|
||||
((MODE) == I2C_Mode_SMBusDevice) || \
|
||||
((MODE) == I2C_Mode_SMBusHost))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_acknowledgement
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Ack_Enable ((uint32_t)0x00000000)
|
||||
#define I2C_Ack_Disable I2C_CR2_NACK
|
||||
|
||||
#define IS_I2C_ACK(ACK) (((ACK) == I2C_Ack_Enable) || \
|
||||
((ACK) == I2C_Ack_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_acknowledged_address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_AcknowledgedAddress_7bit ((uint32_t)0x00000000)
|
||||
#define I2C_AcknowledgedAddress_10bit I2C_OAR1_OA1MODE
|
||||
|
||||
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
|
||||
((ADDRESS) == I2C_AcknowledgedAddress_10bit))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_own_address1
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_transfer_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Direction_Transmitter ((uint16_t)0x0000)
|
||||
#define I2C_Direction_Receiver ((uint16_t)0x0400)
|
||||
|
||||
#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
|
||||
((DIRECTION) == I2C_Direction_Receiver))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_DMA_transfer_requests
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_DMAReq_Tx I2C_CR1_TXDMAEN
|
||||
#define I2C_DMAReq_Rx I2C_CR1_RXDMAEN
|
||||
|
||||
#define IS_I2C_DMA_REQ(REQ) ((((REQ) & (uint32_t)0xFFFF3FFF) == 0x00) && ((REQ) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_slave_address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_SLAVE_ADDRESS(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup I2C_own_address2
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_own_address2_mask
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_OA2_NoMask ((uint8_t)0x00)
|
||||
#define I2C_OA2_Mask01 ((uint8_t)0x01)
|
||||
#define I2C_OA2_Mask02 ((uint8_t)0x02)
|
||||
#define I2C_OA2_Mask03 ((uint8_t)0x03)
|
||||
#define I2C_OA2_Mask04 ((uint8_t)0x04)
|
||||
#define I2C_OA2_Mask05 ((uint8_t)0x05)
|
||||
#define I2C_OA2_Mask06 ((uint8_t)0x06)
|
||||
#define I2C_OA2_Mask07 ((uint8_t)0x07)
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NoMask) || \
|
||||
((MASK) == I2C_OA2_Mask01) || \
|
||||
((MASK) == I2C_OA2_Mask02) || \
|
||||
((MASK) == I2C_OA2_Mask03) || \
|
||||
((MASK) == I2C_OA2_Mask04) || \
|
||||
((MASK) == I2C_OA2_Mask05) || \
|
||||
((MASK) == I2C_OA2_Mask06) || \
|
||||
((MASK) == I2C_OA2_Mask07))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_timeout
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_TIMEOUT(TIMEOUT) ((TIMEOUT) <= (uint16_t)0x0FFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_registers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Register_CR1 ((uint8_t)0x00)
|
||||
#define I2C_Register_CR2 ((uint8_t)0x04)
|
||||
#define I2C_Register_OAR1 ((uint8_t)0x08)
|
||||
#define I2C_Register_OAR2 ((uint8_t)0x0C)
|
||||
#define I2C_Register_TIMINGR ((uint8_t)0x10)
|
||||
#define I2C_Register_TIMEOUTR ((uint8_t)0x14)
|
||||
#define I2C_Register_ISR ((uint8_t)0x18)
|
||||
#define I2C_Register_ICR ((uint8_t)0x1C)
|
||||
#define I2C_Register_PECR ((uint8_t)0x20)
|
||||
#define I2C_Register_RXDR ((uint8_t)0x24)
|
||||
#define I2C_Register_TXDR ((uint8_t)0x28)
|
||||
|
||||
#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
|
||||
((REGISTER) == I2C_Register_CR2) || \
|
||||
((REGISTER) == I2C_Register_OAR1) || \
|
||||
((REGISTER) == I2C_Register_OAR2) || \
|
||||
((REGISTER) == I2C_Register_TIMINGR) || \
|
||||
((REGISTER) == I2C_Register_TIMEOUTR) || \
|
||||
((REGISTER) == I2C_Register_ISR) || \
|
||||
((REGISTER) == I2C_Register_ICR) || \
|
||||
((REGISTER) == I2C_Register_PECR) || \
|
||||
((REGISTER) == I2C_Register_RXDR) || \
|
||||
((REGISTER) == I2C_Register_TXDR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_IT_ERRI I2C_CR1_ERRIE
|
||||
#define I2C_IT_TCI I2C_CR1_TCIE
|
||||
#define I2C_IT_STOPI I2C_CR1_STOPIE
|
||||
#define I2C_IT_NACKI I2C_CR1_NACKIE
|
||||
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
|
||||
#define I2C_IT_RXI I2C_CR1_RXIE
|
||||
#define I2C_IT_TXI I2C_CR1_TXIE
|
||||
|
||||
#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint32_t)0xFFFFFF01) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_FLAG_TXE I2C_ISR_TXE
|
||||
#define I2C_FLAG_TXIS I2C_ISR_TXIS
|
||||
#define I2C_FLAG_RXNE I2C_ISR_RXNE
|
||||
#define I2C_FLAG_ADDR I2C_ISR_ADDR
|
||||
#define I2C_FLAG_NACKF I2C_ISR_NACKF
|
||||
#define I2C_FLAG_STOPF I2C_ISR_STOPF
|
||||
#define I2C_FLAG_TC I2C_ISR_TC
|
||||
#define I2C_FLAG_TCR I2C_ISR_TCR
|
||||
#define I2C_FLAG_BERR I2C_ISR_BERR
|
||||
#define I2C_FLAG_ARLO I2C_ISR_ARLO
|
||||
#define I2C_FLAG_OVR I2C_ISR_OVR
|
||||
#define I2C_FLAG_PECERR I2C_ISR_PECERR
|
||||
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
|
||||
#define I2C_FLAG_ALERT I2C_ISR_ALERT
|
||||
#define I2C_FLAG_BUSY I2C_ISR_BUSY
|
||||
|
||||
#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFF4000) == 0x00) && ((FLAG) != 0x00))
|
||||
|
||||
#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_TXIS) || \
|
||||
((FLAG) == I2C_FLAG_RXNE) || ((FLAG) == I2C_FLAG_ADDR) || \
|
||||
((FLAG) == I2C_FLAG_NACKF) || ((FLAG) == I2C_FLAG_STOPF) || \
|
||||
((FLAG) == I2C_FLAG_TC) || ((FLAG) == I2C_FLAG_TCR) || \
|
||||
((FLAG) == I2C_FLAG_BERR) || ((FLAG) == I2C_FLAG_ARLO) || \
|
||||
((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_PECERR) || \
|
||||
((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_ALERT) || \
|
||||
((FLAG) == I2C_FLAG_BUSY))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup I2C_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_IT_TXIS I2C_ISR_TXIS
|
||||
#define I2C_IT_RXNE I2C_ISR_RXNE
|
||||
#define I2C_IT_ADDR I2C_ISR_ADDR
|
||||
#define I2C_IT_NACKF I2C_ISR_NACKF
|
||||
#define I2C_IT_STOPF I2C_ISR_STOPF
|
||||
#define I2C_IT_TC I2C_ISR_TC
|
||||
#define I2C_IT_TCR I2C_ISR_TCR
|
||||
#define I2C_IT_BERR I2C_ISR_BERR
|
||||
#define I2C_IT_ARLO I2C_ISR_ARLO
|
||||
#define I2C_IT_OVR I2C_ISR_OVR
|
||||
#define I2C_IT_PECERR I2C_ISR_PECERR
|
||||
#define I2C_IT_TIMEOUT I2C_ISR_TIMEOUT
|
||||
#define I2C_IT_ALERT I2C_ISR_ALERT
|
||||
|
||||
#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFFFFC001) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_TXIS) || ((IT) == I2C_IT_RXNE) || \
|
||||
((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_NACKF) || \
|
||||
((IT) == I2C_IT_STOPF) || ((IT) == I2C_IT_TC) || \
|
||||
((IT) == I2C_IT_TCR) || ((IT) == I2C_IT_BERR) || \
|
||||
((IT) == I2C_IT_ARLO) || ((IT) == I2C_IT_OVR) || \
|
||||
((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_TIMEOUT) || \
|
||||
((IT) == I2C_IT_ALERT))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_ReloadEndMode_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Reload_Mode I2C_CR2_RELOAD
|
||||
#define I2C_AutoEnd_Mode I2C_CR2_AUTOEND
|
||||
#define I2C_SoftEnd_Mode ((uint32_t)0x00000000)
|
||||
|
||||
|
||||
#define IS_RELOAD_END_MODE(MODE) (((MODE) == I2C_Reload_Mode) || \
|
||||
((MODE) == I2C_AutoEnd_Mode) || \
|
||||
((MODE) == I2C_SoftEnd_Mode))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_StartStopMode_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_No_StartStop ((uint32_t)0x00000000)
|
||||
#define I2C_Generate_Stop I2C_CR2_STOP
|
||||
#define I2C_Generate_Start_Read (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
|
||||
#define I2C_Generate_Start_Write I2C_CR2_START
|
||||
|
||||
|
||||
#define IS_START_STOP_MODE(MODE) (((MODE) == I2C_Generate_Stop) || \
|
||||
((MODE) == I2C_Generate_Start_Read) || \
|
||||
((MODE) == I2C_Generate_Start_Write) || \
|
||||
((MODE) == I2C_No_StartStop))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void I2C_DeInit(I2C_TypeDef* I2Cx);
|
||||
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
|
||||
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
|
||||
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState);
|
||||
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask);
|
||||
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address);
|
||||
void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
|
||||
/* Communications handling functions ******************************************/
|
||||
void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes);
|
||||
void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction);
|
||||
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx);
|
||||
uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx);
|
||||
void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode);
|
||||
|
||||
/* SMBUS management functions ************************************************/
|
||||
void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
|
||||
void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
|
||||
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
|
||||
|
||||
/* I2C registers management functions *****************************************/
|
||||
uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
|
||||
|
||||
/* Data transfers management functions ****************************************/
|
||||
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
|
||||
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
|
||||
|
||||
/* DMA transfers management functions *****************************************/
|
||||
void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
||||
void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
||||
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
|
||||
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F0XX_I2C_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,140 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_iwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file contains all the functions prototypes for the IWDG
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0XX_IWDG_H
|
||||
#define __STM32F0XX_IWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_WriteAccess
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
|
||||
#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
|
||||
#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
|
||||
((ACCESS) == IWDG_WriteAccess_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IWDG_Prescaler_4 ((uint8_t)0x00)
|
||||
#define IWDG_Prescaler_8 ((uint8_t)0x01)
|
||||
#define IWDG_Prescaler_16 ((uint8_t)0x02)
|
||||
#define IWDG_Prescaler_32 ((uint8_t)0x03)
|
||||
#define IWDG_Prescaler_64 ((uint8_t)0x04)
|
||||
#define IWDG_Prescaler_128 ((uint8_t)0x05)
|
||||
#define IWDG_Prescaler_256 ((uint8_t)0x06)
|
||||
#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
|
||||
((PRESCALER) == IWDG_Prescaler_8) || \
|
||||
((PRESCALER) == IWDG_Prescaler_16) || \
|
||||
((PRESCALER) == IWDG_Prescaler_32) || \
|
||||
((PRESCALER) == IWDG_Prescaler_64) || \
|
||||
((PRESCALER) == IWDG_Prescaler_128)|| \
|
||||
((PRESCALER) == IWDG_Prescaler_256))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IWDG_FLAG_PVU IWDG_SR_PVU
|
||||
#define IWDG_FLAG_RVU IWDG_SR_RVU
|
||||
#define IWDG_FLAG_WVU IWDG_SR_WVU
|
||||
#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU) || \
|
||||
((FLAG) == IWDG_FLAG_WVU))
|
||||
|
||||
#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
|
||||
|
||||
#define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Prescaler and Counter configuration functions ******************************/
|
||||
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
|
||||
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
|
||||
void IWDG_SetReload(uint16_t Reload);
|
||||
void IWDG_ReloadCounter(void);
|
||||
void IWDG_SetWindowValue(uint16_t WindowValue);
|
||||
|
||||
/* IWDG activation function ***************************************************/
|
||||
void IWDG_Enable(void);
|
||||
|
||||
/* Flag management function ***************************************************/
|
||||
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0XX_IWDG_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,143 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_misc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file contains all the functions prototypes for the miscellaneous
|
||||
* firmware library functions (add-on to CMSIS functions).
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0XX_MISC_H
|
||||
#define __STM32F0XX_MISC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup MISC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief NVIC Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
|
||||
This parameter can be a value of @ref IRQn_Type
|
||||
(For the complete STM32 Devices IRQ Channels list,
|
||||
please refer to stm32f0xx.h file) */
|
||||
|
||||
uint8_t NVIC_IRQChannelPriority; /*!< Specifies the priority level for the IRQ channel specified
|
||||
in NVIC_IRQChannel. This parameter can be a value
|
||||
between 0 and 3. */
|
||||
|
||||
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
|
||||
will be enabled or disabled.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
} NVIC_InitTypeDef;
|
||||
|
||||
/**
|
||||
*
|
||||
@verbatim
|
||||
|
||||
@endverbatim
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup MISC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_System_Low_Power
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
|
||||
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
|
||||
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
|
||||
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
|
||||
((LP) == NVIC_LP_SLEEPDEEP) || \
|
||||
((LP) == NVIC_LP_SLEEPONEXIT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Preemption_Priority_Group
|
||||
* @{
|
||||
*/
|
||||
#define IS_NVIC_PRIORITY(PRIORITY) ((PRIORITY) < 0x04)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_SysTick_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
|
||||
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
|
||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
|
||||
((SOURCE) == SysTick_CLKSource_HCLK_Div8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
|
||||
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
|
||||
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0XX_MISC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,186 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file contains all the functions prototypes for the PWR firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0XX_PWR_H
|
||||
#define __STM32F0XX_PWR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_detection_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0
|
||||
#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1
|
||||
#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2
|
||||
#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3
|
||||
#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4
|
||||
#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5
|
||||
#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6
|
||||
#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7
|
||||
|
||||
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
|
||||
((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
|
||||
((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
|
||||
((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_WakeUp_Pins
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_WakeUpPin_1 PWR_CSR_EWUP1
|
||||
#define PWR_WakeUpPin_2 PWR_CSR_EWUP2
|
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \
|
||||
((PIN) == PWR_WakeUpPin_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_Regulator_ON ((uint32_t)0x00000000)
|
||||
#define PWR_Regulator_LowPower PWR_CR_LPSDSR
|
||||
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
|
||||
((REGULATOR) == PWR_Regulator_LowPower))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_SLEEP_mode_entry
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_SLEEPEntry_WFI ((uint8_t)0x01)
|
||||
#define PWR_SLEEPEntry_WFE ((uint8_t)0x02)
|
||||
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_STOP_mode_entry
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
|
||||
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
|
||||
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_FLAG_WU PWR_CSR_WUF
|
||||
#define PWR_FLAG_SB PWR_CSR_SBF
|
||||
#define PWR_FLAG_PVDO PWR_CSR_PVDO
|
||||
#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
|
||||
|
||||
#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
|
||||
((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY))
|
||||
|
||||
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the PWR configuration to the default reset state ******/
|
||||
void PWR_DeInit(void);
|
||||
|
||||
/* Backup Domain Access function **********************************************/
|
||||
void PWR_BackupAccessCmd(FunctionalState NewState);
|
||||
|
||||
/* PVD configuration functions ************************************************/
|
||||
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
|
||||
void PWR_PVDCmd(FunctionalState NewState);
|
||||
|
||||
/* WakeUp pins configuration functions ****************************************/
|
||||
void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);
|
||||
|
||||
/* Low Power modes configuration functions ************************************/
|
||||
void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry);
|
||||
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
|
||||
void PWR_EnterSTANDBYMode(void);
|
||||
|
||||
/* Flags management functions *************************************************/
|
||||
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
|
||||
void PWR_ClearFlag(uint32_t PWR_FLAG);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0XX_PWR_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,523 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_rcc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file contains all the functions prototypes for the RCC
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0XX_RCC_H
|
||||
#define __STM32F0XX_RCC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SYSCLK_Frequency;
|
||||
uint32_t HCLK_Frequency;
|
||||
uint32_t PCLK_Frequency;
|
||||
uint32_t ADCCLK_Frequency;
|
||||
uint32_t CECCLK_Frequency;
|
||||
uint32_t I2C1CLK_Frequency;
|
||||
uint32_t USART1CLK_Frequency;
|
||||
}RCC_ClocksTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RCC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_HSE_configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_HSE_OFF ((uint8_t)0x00)
|
||||
#define RCC_HSE_ON ((uint8_t)0x01)
|
||||
#define RCC_HSE_Bypass ((uint8_t)0x05)
|
||||
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
|
||||
((HSE) == RCC_HSE_Bypass))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PLL_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2
|
||||
#define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_PREDIV1
|
||||
|
||||
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
|
||||
((SOURCE) == RCC_PLLSource_PREDIV1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PLL_Multiplication_Factor
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_PLLMul_2 RCC_CFGR_PLLMULL2
|
||||
#define RCC_PLLMul_3 RCC_CFGR_PLLMULL3
|
||||
#define RCC_PLLMul_4 RCC_CFGR_PLLMULL4
|
||||
#define RCC_PLLMul_5 RCC_CFGR_PLLMULL5
|
||||
#define RCC_PLLMul_6 RCC_CFGR_PLLMULL6
|
||||
#define RCC_PLLMul_7 RCC_CFGR_PLLMULL7
|
||||
#define RCC_PLLMul_8 RCC_CFGR_PLLMULL8
|
||||
#define RCC_PLLMul_9 RCC_CFGR_PLLMULL9
|
||||
#define RCC_PLLMul_10 RCC_CFGR_PLLMULL10
|
||||
#define RCC_PLLMul_11 RCC_CFGR_PLLMULL11
|
||||
#define RCC_PLLMul_12 RCC_CFGR_PLLMULL12
|
||||
#define RCC_PLLMul_13 RCC_CFGR_PLLMULL13
|
||||
#define RCC_PLLMul_14 RCC_CFGR_PLLMULL14
|
||||
#define RCC_PLLMul_15 RCC_CFGR_PLLMULL15
|
||||
#define RCC_PLLMul_16 RCC_CFGR_PLLMULL16
|
||||
#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
|
||||
((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
|
||||
((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
|
||||
((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
|
||||
((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
|
||||
((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
|
||||
((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
|
||||
((MUL) == RCC_PLLMul_16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PREDIV1_division_factor
|
||||
* @{
|
||||
*/
|
||||
#define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1
|
||||
#define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2
|
||||
#define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3
|
||||
#define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4
|
||||
#define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5
|
||||
#define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6
|
||||
#define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7
|
||||
#define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8
|
||||
#define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9
|
||||
#define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10
|
||||
#define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11
|
||||
#define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12
|
||||
#define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13
|
||||
#define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14
|
||||
#define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15
|
||||
#define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16
|
||||
|
||||
#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
|
||||
((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_System_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI
|
||||
#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE
|
||||
#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL
|
||||
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_HSE) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_PLLCLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1
|
||||
#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2
|
||||
#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4
|
||||
#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8
|
||||
#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16
|
||||
#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64
|
||||
#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
|
||||
#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
|
||||
#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
|
||||
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
|
||||
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
|
||||
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
|
||||
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
|
||||
((HCLK) == RCC_SYSCLK_Div512))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_HCLK_Div1 RCC_CFGR_PPRE_DIV1
|
||||
#define RCC_HCLK_Div2 RCC_CFGR_PPRE_DIV2
|
||||
#define RCC_HCLK_Div4 RCC_CFGR_PPRE_DIV4
|
||||
#define RCC_HCLK_Div8 RCC_CFGR_PPRE_DIV8
|
||||
#define RCC_HCLK_Div16 RCC_CFGR_PPRE_DIV16
|
||||
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
|
||||
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
|
||||
((PCLK) == RCC_HCLK_Div16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_ADC_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_ADCCLK_HSI14 ((uint32_t)0x00000000)
|
||||
#define RCC_ADCCLK_PCLK_Div2 ((uint32_t)0x01000000)
|
||||
#define RCC_ADCCLK_PCLK_Div4 ((uint32_t)0x01004000)
|
||||
|
||||
#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADCCLK_HSI14) || ((ADCCLK) == RCC_ADCCLK_PCLK_Div2) || \
|
||||
((ADCCLK) == RCC_ADCCLK_PCLK_Div4))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_CEC_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_CECCLK_HSI_Div244 ((uint32_t)0x00000000)
|
||||
#define RCC_CECCLK_LSE RCC_CFGR3_CECSW
|
||||
|
||||
#define IS_RCC_CECCLK(CECCLK) (((CECCLK) == RCC_CECCLK_HSI_Div244) || ((CECCLK) == RCC_CECCLK_LSE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_I2C_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_I2C1CLK_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW
|
||||
|
||||
#define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_USART_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_USART1CLK_PCLK ((uint32_t)0x00000000)
|
||||
#define RCC_USART1CLK_SYSCLK RCC_CFGR3_USART1SW_0
|
||||
#define RCC_USART1CLK_LSE RCC_CFGR3_USART1SW_1
|
||||
#define RCC_USART1CLK_HSI RCC_CFGR3_USART1SW
|
||||
|
||||
#define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \
|
||||
((USARTCLK) == RCC_USART1CLK_LSE) || ((USARTCLK) == RCC_USART1CLK_HSI))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Interrupt_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_IT_LSIRDY ((uint8_t)0x01)
|
||||
#define RCC_IT_LSERDY ((uint8_t)0x02)
|
||||
#define RCC_IT_HSIRDY ((uint8_t)0x04)
|
||||
#define RCC_IT_HSERDY ((uint8_t)0x08)
|
||||
#define RCC_IT_PLLRDY ((uint8_t)0x10)
|
||||
#define RCC_IT_HSI14RDY ((uint8_t)0x20)
|
||||
#define RCC_IT_CSS ((uint8_t)0x80)
|
||||
|
||||
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
|
||||
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
|
||||
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_HSI14RDY) || \
|
||||
((IT) == RCC_IT_CSS))
|
||||
|
||||
#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_LSE_Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_LSE_OFF ((uint32_t)0x00000000)
|
||||
#define RCC_LSE_ON RCC_BDCR_LSEON
|
||||
#define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))
|
||||
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
|
||||
((LSE) == RCC_LSE_Bypass))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_RTC_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE
|
||||
#define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI
|
||||
#define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE
|
||||
|
||||
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_LSI) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div32))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_LSE_Drive_Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_LSEDrive_Low ((uint32_t)0x00000000)
|
||||
#define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0
|
||||
#define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1
|
||||
#define RCC_LSEDrive_High RCC_BDCR_LSEDRV
|
||||
#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \
|
||||
((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB_Peripherals
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
|
||||
#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
|
||||
#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
|
||||
#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
|
||||
#define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN
|
||||
#define RCC_AHBPeriph_TS RCC_AHBENR_TSEN
|
||||
#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
|
||||
#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
|
||||
#define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN
|
||||
#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN
|
||||
|
||||
#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFEA1FFAA) == 0x00) && ((PERIPH) != 0x00))
|
||||
#define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xFEA1FFFF) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB2_Peripherals
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN
|
||||
#define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN
|
||||
#define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN
|
||||
#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN
|
||||
#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
|
||||
#define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN
|
||||
#define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN
|
||||
#define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN
|
||||
#define RCC_APB2Periph_DBGMCU RCC_APB2ENR_DBGMCUEN
|
||||
|
||||
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFB8A5FE) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB1_Peripherals
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN
|
||||
#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN
|
||||
#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN
|
||||
#define RCC_APB1Periph_TIM14 RCC_APB1ENR_TIM14EN
|
||||
#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN
|
||||
#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN
|
||||
#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN
|
||||
#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN
|
||||
#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN
|
||||
#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN
|
||||
#define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN
|
||||
#define RCC_APB1Periph_CEC RCC_APB1ENR_CECEN
|
||||
|
||||
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x8F9DB6EC) == 0x00) && ((PERIPH) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_MCO_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_MCOSource_NoClock ((uint8_t)0x00)
|
||||
#define RCC_MCOSource_HSI14 ((uint8_t)0x01)
|
||||
#define RCC_MCOSource_LSI ((uint8_t)0x02)
|
||||
#define RCC_MCOSource_LSE ((uint8_t)0x03)
|
||||
#define RCC_MCOSource_SYSCLK ((uint8_t)0x04)
|
||||
#define RCC_MCOSource_HSI ((uint8_t)0x05)
|
||||
#define RCC_MCOSource_HSE ((uint8_t)0x06)
|
||||
#define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07)
|
||||
|
||||
#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_HSI14) || \
|
||||
((SOURCE) == RCC_MCOSource_SYSCLK) || ((SOURCE) == RCC_MCOSource_HSI) || \
|
||||
((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK_Div2)|| \
|
||||
((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Flag
|
||||
* @{
|
||||
*/
|
||||
#define RCC_FLAG_HSIRDY ((uint8_t)0x01)
|
||||
#define RCC_FLAG_HSERDY ((uint8_t)0x11)
|
||||
#define RCC_FLAG_PLLRDY ((uint8_t)0x19)
|
||||
#define RCC_FLAG_LSERDY ((uint8_t)0x21)
|
||||
#define RCC_FLAG_LSIRDY ((uint8_t)0x41)
|
||||
#define RCC_FLAG_V18PWRRSTF ((uint8_t)0x57)
|
||||
#define RCC_FLAG_OBLRST ((uint8_t)0x59)
|
||||
#define RCC_FLAG_PINRST ((uint8_t)0x5A)
|
||||
#define RCC_FLAG_PORRST ((uint8_t)0x5B)
|
||||
#define RCC_FLAG_SFTRST ((uint8_t)0x5C)
|
||||
#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
|
||||
#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
|
||||
#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
|
||||
#define RCC_FLAG_HSI14RDY ((uint8_t)0x61)
|
||||
|
||||
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
|
||||
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
|
||||
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \
|
||||
((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
|
||||
((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
|
||||
((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \
|
||||
((FLAG) == RCC_FLAG_HSI14RDY)|| ((FLAG) == RCC_FLAG_V18PWRRSTF))
|
||||
|
||||
#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
|
||||
#define IS_RCC_HSI14_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the RCC clock configuration to the default reset state */
|
||||
void RCC_DeInit(void);
|
||||
|
||||
/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
|
||||
void RCC_HSEConfig(uint8_t RCC_HSE);
|
||||
ErrorStatus RCC_WaitForHSEStartUp(void);
|
||||
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
|
||||
void RCC_HSICmd(FunctionalState NewState);
|
||||
void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue);
|
||||
void RCC_HSI14Cmd(FunctionalState NewState);
|
||||
void RCC_HSI14ADCRequestCmd(FunctionalState NewState);
|
||||
void RCC_LSEConfig(uint32_t RCC_LSE);
|
||||
void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);
|
||||
void RCC_LSICmd(FunctionalState NewState);
|
||||
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
|
||||
void RCC_PLLCmd(FunctionalState NewState);
|
||||
void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div);
|
||||
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
|
||||
void RCC_MCOConfig(uint8_t RCC_MCOSource);
|
||||
|
||||
/* System, AHB and APB busses clocks configuration functions ******************/
|
||||
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
|
||||
uint8_t RCC_GetSYSCLKSource(void);
|
||||
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
|
||||
void RCC_PCLKConfig(uint32_t RCC_HCLK);
|
||||
void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK);
|
||||
void RCC_CECCLKConfig(uint32_t RCC_CECCLK);
|
||||
void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK);
|
||||
void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK);
|
||||
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
|
||||
|
||||
/* Peripheral clocks configuration functions **********************************/
|
||||
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
|
||||
void RCC_RTCCLKCmd(FunctionalState NewState);
|
||||
void RCC_BackupResetCmd(FunctionalState NewState);
|
||||
|
||||
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
|
||||
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
|
||||
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
|
||||
void RCC_ClearFlag(void);
|
||||
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
|
||||
void RCC_ClearITPendingBit(uint8_t RCC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0XX_RCC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,772 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_rtc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file contains all the functions prototypes for the RTC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0XX_RTC_H
|
||||
#define __STM32F0XX_RTC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief RTC Init structures definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.
|
||||
This parameter can be a value of @ref RTC_Hour_Formats */
|
||||
|
||||
uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
|
||||
This parameter must be set to a value lower than 0x7F */
|
||||
|
||||
uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
|
||||
This parameter must be set to a value lower than 0x1FFF */
|
||||
}RTC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Time structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour.
|
||||
This parameter must be set to a value in the 0-12 range
|
||||
if the RTC_HourFormat_12 is selected or 0-23 range if
|
||||
the RTC_HourFormat_24 is selected. */
|
||||
|
||||
uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes.
|
||||
This parameter must be set to a value in the 0-59 range. */
|
||||
|
||||
uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds.
|
||||
This parameter must be set to a value in the 0-59 range. */
|
||||
|
||||
uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time.
|
||||
This parameter can be a value of @ref RTC_AM_PM_Definitions */
|
||||
}RTC_TimeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Date structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.
|
||||
This parameter can be a value of @ref RTC_WeekDay_Definitions */
|
||||
|
||||
uint8_t RTC_Month; /*!< Specifies the RTC Date Month.
|
||||
This parameter can be a value of @ref RTC_Month_Date_Definitions */
|
||||
|
||||
uint8_t RTC_Date; /*!< Specifies the RTC Date.
|
||||
This parameter must be set to a value in the 1-31 range. */
|
||||
|
||||
uint8_t RTC_Year; /*!< Specifies the RTC Date Year.
|
||||
This parameter must be set to a value in the 0-99 range. */
|
||||
}RTC_DateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Alarm structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */
|
||||
|
||||
uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks.
|
||||
This parameter can be a value of @ref RTC_AlarmMask_Definitions */
|
||||
|
||||
uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
|
||||
This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
|
||||
|
||||
uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
|
||||
This parameter must be set to a value in the 1-31 range
|
||||
if the Alarm Date is selected.
|
||||
This parameter can be a value of @ref RTC_WeekDay_Definitions
|
||||
if the Alarm WeekDay is selected. */
|
||||
}RTC_AlarmTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RTC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_Hour_Formats
|
||||
* @{
|
||||
*/
|
||||
#define RTC_HourFormat_24 ((uint32_t)0x00000000)
|
||||
#define RTC_HourFormat_12 ((uint32_t)0x00000040)
|
||||
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \
|
||||
((FORMAT) == RTC_HourFormat_24))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Asynchronous_Predivider
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_Synchronous_Predivider
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Time_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))
|
||||
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)
|
||||
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
|
||||
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_AM_PM_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_H12_AM ((uint8_t)0x00)
|
||||
#define RTC_H12_PM ((uint8_t)0x40)
|
||||
#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Year_Date_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Month_Date_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_Month_January ((uint8_t)0x01)
|
||||
#define RTC_Month_February ((uint8_t)0x02)
|
||||
#define RTC_Month_March ((uint8_t)0x03)
|
||||
#define RTC_Month_April ((uint8_t)0x04)
|
||||
#define RTC_Month_May ((uint8_t)0x05)
|
||||
#define RTC_Month_June ((uint8_t)0x06)
|
||||
#define RTC_Month_July ((uint8_t)0x07)
|
||||
#define RTC_Month_August ((uint8_t)0x08)
|
||||
#define RTC_Month_September ((uint8_t)0x09)
|
||||
#define RTC_Month_October ((uint8_t)0x10)
|
||||
#define RTC_Month_November ((uint8_t)0x11)
|
||||
#define RTC_Month_December ((uint8_t)0x12)
|
||||
#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))
|
||||
#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_WeekDay_Definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RTC_Weekday_Monday ((uint8_t)0x01)
|
||||
#define RTC_Weekday_Tuesday ((uint8_t)0x02)
|
||||
#define RTC_Weekday_Wednesday ((uint8_t)0x03)
|
||||
#define RTC_Weekday_Thursday ((uint8_t)0x04)
|
||||
#define RTC_Weekday_Friday ((uint8_t)0x05)
|
||||
#define RTC_Weekday_Saturday ((uint8_t)0x6)
|
||||
#define RTC_Weekday_Sunday ((uint8_t)0x07)
|
||||
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Tuesday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Wednesday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Thursday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Friday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Saturday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Sunday))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_Alarm_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Tuesday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Wednesday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Thursday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Friday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Saturday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Sunday))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_AlarmDateWeekDay_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000)
|
||||
#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000)
|
||||
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
|
||||
((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_AlarmMask_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_AlarmMask_None ((uint32_t)0x00000000)
|
||||
#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000)
|
||||
#define RTC_AlarmMask_Hours ((uint32_t)0x00800000)
|
||||
#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000)
|
||||
#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080)
|
||||
#define RTC_AlarmMask_All ((uint32_t)0x80808080)
|
||||
#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarms_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_Alarm_A ((uint32_t)0x00000100)
|
||||
#define IS_RTC_ALARM(ALARM) ((ALARM) == RTC_Alarm_A)
|
||||
#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A)) != (uint32_t)RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarm_Sub_Seconds_Masks Definitions.
|
||||
* @{
|
||||
*/
|
||||
#define RTC_AlarmSubSecondMask_All ((uint8_t)0x00) /*!< All Alarm SS fields are masked.
|
||||
There is no comparison on sub seconds
|
||||
for Alarm */
|
||||
#define RTC_AlarmSubSecondMask_SS14_1 ((uint8_t)0x01) /*!< SS[14:1] are don't care in Alarm
|
||||
comparison. Only SS[0] is compared. */
|
||||
#define RTC_AlarmSubSecondMask_SS14_2 ((uint8_t)0x02) /*!< SS[14:2] are don't care in Alarm
|
||||
comparison. Only SS[1:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_3 ((uint8_t)0x03) /*!< SS[14:3] are don't care in Alarm
|
||||
comparison. Only SS[2:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_4 ((uint8_t)0x04) /*!< SS[14:4] are don't care in Alarm
|
||||
comparison. Only SS[3:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_5 ((uint8_t)0x05) /*!< SS[14:5] are don't care in Alarm
|
||||
comparison. Only SS[4:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_6 ((uint8_t)0x06) /*!< SS[14:6] are don't care in Alarm
|
||||
comparison. Only SS[5:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_7 ((uint8_t)0x07) /*!< SS[14:7] are don't care in Alarm
|
||||
comparison. Only SS[6:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_8 ((uint8_t)0x08) /*!< SS[14:8] are don't care in Alarm
|
||||
comparison. Only SS[7:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_9 ((uint8_t)0x09) /*!< SS[14:9] are don't care in Alarm
|
||||
comparison. Only SS[8:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_10 ((uint8_t)0x0A) /*!< SS[14:10] are don't care in Alarm
|
||||
comparison. Only SS[9:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_11 ((uint8_t)0x0B) /*!< SS[14:11] are don't care in Alarm
|
||||
comparison. Only SS[10:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_12 ((uint8_t)0x0C) /*!< SS[14:12] are don't care in Alarm
|
||||
comparison.Only SS[11:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_13 ((uint8_t)0x0D) /*!< SS[14:13] are don't care in Alarm
|
||||
comparison. Only SS[12:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14 ((uint8_t)0x0E) /*!< SS[14] is don't care in Alarm
|
||||
comparison.Only SS[13:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_None ((uint8_t)0x0F) /*!< SS[14:0] are compared and must match
|
||||
to activate alarm. */
|
||||
#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_None))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarm_Sub_Seconds_Value
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Time_Stamp_Edges_definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000)
|
||||
#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008)
|
||||
#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
|
||||
((EDGE) == RTC_TimeStampEdge_Falling))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_selection_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_Output_Disable ((uint32_t)0x00000000)
|
||||
#define RTC_Output_AlarmA ((uint32_t)0x00200000)
|
||||
|
||||
#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
|
||||
((OUTPUT) == RTC_Output_AlarmA))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_Polarity_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OutputPolarity_High ((uint32_t)0x00000000)
|
||||
#define RTC_OutputPolarity_Low ((uint32_t)0x00100000)
|
||||
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
|
||||
((POL) == RTC_OutputPolarity_Low))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_Calib_Output_selection_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000)
|
||||
#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000)
|
||||
#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \
|
||||
((OUTPUT) == RTC_CalibOutput_1Hz))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Smooth_calib_period_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
|
||||
period is 32s, else 2exp20 RTCCLK seconds */
|
||||
#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
|
||||
period is 16s, else 2exp19 RTCCLK seconds */
|
||||
#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
|
||||
period is 8s, else 2exp18 RTCCLK seconds */
|
||||
#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
|
||||
((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
|
||||
((PERIOD) == RTC_SmoothCalibPeriod_8sec))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added
|
||||
during a X -second window = Y - CALM[8:0].
|
||||
with Y = 512, 256, 128 when X = 32, 16, 8 */
|
||||
#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
|
||||
during a 32-second window = CALM[8:0]. */
|
||||
#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
|
||||
((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_DayLightSaving_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000)
|
||||
#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000)
|
||||
#define IS_RTC_DAYLIGHT_SAVING(SAVING) (((SAVING) == RTC_DayLightSaving_SUB1H) || \
|
||||
((SAVING) == RTC_DayLightSaving_ADD1H))
|
||||
|
||||
#define RTC_StoreOperation_Reset ((uint32_t)0x00000000)
|
||||
#define RTC_StoreOperation_Set ((uint32_t)0x00040000)
|
||||
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
|
||||
((OPERATION) == RTC_StoreOperation_Set))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Trigger_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)
|
||||
#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001)
|
||||
#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000)
|
||||
#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001)
|
||||
#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
|
||||
((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
|
||||
((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
|
||||
((TRIGGER) == RTC_TamperTrigger_HighLevel))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Filter_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
|
||||
|
||||
#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2
|
||||
consecutive samples at the active level */
|
||||
#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4
|
||||
consecutive samples at the active level */
|
||||
#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8
|
||||
consecutive samples at the active leve. */
|
||||
#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
|
||||
((FILTER) == RTC_TamperFilter_2Sample) || \
|
||||
((FILTER) == RTC_TamperFilter_4Sample) || \
|
||||
((FILTER) == RTC_TamperFilter_8Sample))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 32768 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 16384 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 8192 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 4096 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 2048 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 1024 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 512 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 256 */
|
||||
#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
|
||||
sampling during 1 RTCCLK cycle */
|
||||
#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before
|
||||
sampling during 2 RTCCLK cycles */
|
||||
#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before
|
||||
sampling during 4 RTCCLK cycles */
|
||||
#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before
|
||||
sampling during 8 RTCCLK cycles */
|
||||
|
||||
#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
|
||||
((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
|
||||
((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
|
||||
((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Pins_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_Tamper_1 RTC_TAFCR_TAMP1E /*!< Tamper detection enable for
|
||||
input tamper 1 */
|
||||
#define RTC_Tamper_2 RTC_TAFCR_TAMP2E /*!< Tamper detection enable for
|
||||
input tamper 2 */
|
||||
#define RTC_Tamper_3 RTC_TAFCR_TAMP3E /*!< Tamper detection enable for
|
||||
input tamper 3 */
|
||||
|
||||
#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_Type_ALARM_OUT
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000)
|
||||
#define RTC_OutputType_PushPull ((uint32_t)0x00040000)
|
||||
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
|
||||
((TYPE) == RTC_OutputType_PushPull))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Add_1_Second_Parameter_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000)
|
||||
#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000)
|
||||
#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \
|
||||
((SEL) == RTC_ShiftAdd1S_Set))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Substract_Fraction_Of_Second_Value
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Backup_Registers_Definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RTC_BKP_DR0 ((uint32_t)0x00000000)
|
||||
#define RTC_BKP_DR1 ((uint32_t)0x00000001)
|
||||
#define RTC_BKP_DR2 ((uint32_t)0x00000002)
|
||||
#define RTC_BKP_DR3 ((uint32_t)0x00000003)
|
||||
#define RTC_BKP_DR4 ((uint32_t)0x00000004)
|
||||
#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \
|
||||
((BKP) == RTC_BKP_DR1) || \
|
||||
((BKP) == RTC_BKP_DR2) || \
|
||||
((BKP) == RTC_BKP_DR3) || \
|
||||
((BKP) == RTC_BKP_DR4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Input_parameter_format_definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_Format_BIN ((uint32_t)0x000000000)
|
||||
#define RTC_Format_BCD ((uint32_t)0x000000001)
|
||||
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Flags_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FLAG_RECALPF ((uint32_t)0x00010000)
|
||||
#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000)
|
||||
#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000)
|
||||
#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
|
||||
#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)
|
||||
#define RTC_FLAG_TSF ((uint32_t)0x00000800)
|
||||
#define RTC_FLAG_ALRAF ((uint32_t)0x00000100)
|
||||
#define RTC_FLAG_INITF ((uint32_t)0x00000040)
|
||||
#define RTC_FLAG_RSF ((uint32_t)0x00000020)
|
||||
#define RTC_FLAG_INITS ((uint32_t)0x00000010)
|
||||
#define RTC_FLAG_SHPF ((uint32_t)0x00000008)
|
||||
|
||||
#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RECALPF) || ((FLAG) == RTC_FLAG_TAMP3F) || \
|
||||
((FLAG) == RTC_FLAG_TAMP2F) || ((FLAG) == RTC_FLAG_TAMP1F) || \
|
||||
((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
|
||||
((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
|
||||
((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_INITS) || \
|
||||
((FLAG) == RTC_FLAG_SHPF))
|
||||
#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF06DF) == (uint32_t)RESET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Interrupts_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_IT_TS ((uint32_t)0x00008000)
|
||||
#define RTC_IT_ALRA ((uint32_t)0x00001000)
|
||||
#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
|
||||
#define RTC_IT_TAMP1 ((uint32_t)0x00020000)
|
||||
#define RTC_IT_TAMP2 ((uint32_t)0x00040000)
|
||||
#define RTC_IT_TAMP3 ((uint32_t)0x00080000)
|
||||
|
||||
#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF6FFB) == (uint32_t)RESET))
|
||||
#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_ALRA) || \
|
||||
((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_TAMP2) || \
|
||||
((IT) == RTC_IT_TAMP3))
|
||||
#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF16FFF) == (uint32_t)RESET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Function used to set the RTC configuration to the default reset state *****/
|
||||
ErrorStatus RTC_DeInit(void);
|
||||
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
|
||||
void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
|
||||
void RTC_WriteProtectionCmd(FunctionalState NewState);
|
||||
ErrorStatus RTC_EnterInitMode(void);
|
||||
void RTC_ExitInitMode(void);
|
||||
ErrorStatus RTC_WaitForSynchro(void);
|
||||
ErrorStatus RTC_RefClockCmd(FunctionalState NewState);
|
||||
void RTC_BypassShadowCmd(FunctionalState NewState);
|
||||
|
||||
/* Time and Date configuration functions **************************************/
|
||||
ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
|
||||
void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
|
||||
void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
|
||||
uint32_t RTC_GetSubSecond(void);
|
||||
ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
|
||||
void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
|
||||
void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
|
||||
|
||||
/* Alarms (Alarm A) configuration functions **********************************/
|
||||
void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
|
||||
void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
|
||||
void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
|
||||
ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
|
||||
void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint8_t RTC_AlarmSubSecondMask);
|
||||
uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
|
||||
|
||||
/* Daylight Saving configuration functions ************************************/
|
||||
void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
|
||||
uint32_t RTC_GetStoreOperation(void);
|
||||
|
||||
/* Output pin Configuration function ******************************************/
|
||||
void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
|
||||
|
||||
/* Digital Calibration configuration functions ********************************/
|
||||
void RTC_CalibOutputCmd(FunctionalState NewState);
|
||||
void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);
|
||||
ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
|
||||
uint32_t RTC_SmoothCalibPlusPulses,
|
||||
uint32_t RTC_SmouthCalibMinusPulsesValue);
|
||||
|
||||
/* TimeStamp configuration functions ******************************************/
|
||||
void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
|
||||
void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, RTC_DateTypeDef* RTC_StampDateStruct);
|
||||
uint32_t RTC_GetTimeStampSubSecond(void);
|
||||
|
||||
/* Tampers configuration functions ********************************************/
|
||||
void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
|
||||
void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
|
||||
void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
|
||||
void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
|
||||
void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
|
||||
void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
|
||||
void RTC_TamperPullUpCmd(FunctionalState NewState);
|
||||
|
||||
/* Backup Data Registers configuration functions ******************************/
|
||||
void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
|
||||
uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
|
||||
|
||||
/* Output Type Config configuration functions *********************************/
|
||||
void RTC_OutputTypeConfig(uint32_t RTC_OutputType);
|
||||
|
||||
/* RTC_Shift_control_synchonisation_functions *********************************/
|
||||
ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
|
||||
FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
|
||||
void RTC_ClearFlag(uint32_t RTC_FLAG);
|
||||
ITStatus RTC_GetITStatus(uint32_t RTC_IT);
|
||||
void RTC_ClearITPendingBit(uint32_t RTC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F0XX_RTC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,587 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_spi.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file contains all the functions prototypes for the SPI
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0XX_SPI_H
|
||||
#define __STM32F0XX_SPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief SPI Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
|
||||
This parameter can be a value of @ref SPI_data_direction */
|
||||
|
||||
uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave).
|
||||
This parameter can be a value of @ref SPI_mode */
|
||||
|
||||
uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
|
||||
This parameter can be a value of @ref SPI_data_size */
|
||||
|
||||
uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
|
||||
This parameter can be a value of @ref SPI_Clock_Polarity */
|
||||
|
||||
uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
|
||||
This parameter can be a value of @ref SPI_Clock_Phase */
|
||||
|
||||
uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
|
||||
hardware (NSS pin) or by software using the SSI bit.
|
||||
This parameter can be a value of @ref SPI_Slave_Select_management */
|
||||
|
||||
uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
|
||||
used to configure the transmit and receive SCK clock.
|
||||
This parameter can be a value of @ref SPI_BaudRate_Prescaler
|
||||
@note The communication clock is derived from the master
|
||||
clock. The slave clock does not need to be set. */
|
||||
|
||||
uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
||||
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
|
||||
|
||||
uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
|
||||
}SPI_InitTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief I2S Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
|
||||
This parameter can be a value of @ref SPI_I2S_Mode */
|
||||
|
||||
uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
|
||||
This parameter can be a value of @ref SPI_I2S_Standard */
|
||||
|
||||
uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
|
||||
This parameter can be a value of @ref SPI_I2S_Data_Format */
|
||||
|
||||
uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
|
||||
This parameter can be a value of @ref SPI_I2S_MCLK_Output */
|
||||
|
||||
uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
|
||||
This parameter can be a value of @ref SPI_I2S_Audio_Frequency */
|
||||
|
||||
uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
|
||||
This parameter can be a value of @ref SPI_I2S_Clock_Polarity */
|
||||
}I2S_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SPI_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
|
||||
((PERIPH) == SPI2))
|
||||
|
||||
#define IS_SPI_1_PERIPH(PERIPH) (((PERIPH) == SPI1))
|
||||
|
||||
/** @defgroup SPI_data_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
|
||||
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
|
||||
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
|
||||
#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
|
||||
#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
|
||||
((MODE) == SPI_Direction_2Lines_RxOnly) || \
|
||||
((MODE) == SPI_Direction_1Line_Rx) || \
|
||||
((MODE) == SPI_Direction_1Line_Tx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_Mode_Master ((uint16_t)0x0104)
|
||||
#define SPI_Mode_Slave ((uint16_t)0x0000)
|
||||
#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
|
||||
((MODE) == SPI_Mode_Slave))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_DataSize_4b ((uint16_t)0x0300)
|
||||
#define SPI_DataSize_5b ((uint16_t)0x0400)
|
||||
#define SPI_DataSize_6b ((uint16_t)0x0500)
|
||||
#define SPI_DataSize_7b ((uint16_t)0x0600)
|
||||
#define SPI_DataSize_8b ((uint16_t)0x0700)
|
||||
#define SPI_DataSize_9b ((uint16_t)0x0800)
|
||||
#define SPI_DataSize_10b ((uint16_t)0x0900)
|
||||
#define SPI_DataSize_11b ((uint16_t)0x0A00)
|
||||
#define SPI_DataSize_12b ((uint16_t)0x0B00)
|
||||
#define SPI_DataSize_13b ((uint16_t)0x0C00)
|
||||
#define SPI_DataSize_14b ((uint16_t)0x0D00)
|
||||
#define SPI_DataSize_15b ((uint16_t)0x0E00)
|
||||
#define SPI_DataSize_16b ((uint16_t)0x0F00)
|
||||
#define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \
|
||||
((SIZE) == SPI_DataSize_5b) || \
|
||||
((SIZE) == SPI_DataSize_6b) || \
|
||||
((SIZE) == SPI_DataSize_7b) || \
|
||||
((SIZE) == SPI_DataSize_8b) || \
|
||||
((SIZE) == SPI_DataSize_9b) || \
|
||||
((SIZE) == SPI_DataSize_10b) || \
|
||||
((SIZE) == SPI_DataSize_11b) || \
|
||||
((SIZE) == SPI_DataSize_12b) || \
|
||||
((SIZE) == SPI_DataSize_13b) || \
|
||||
((SIZE) == SPI_DataSize_14b) || \
|
||||
((SIZE) == SPI_DataSize_15b) || \
|
||||
((SIZE) == SPI_DataSize_16b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CRCLength_8b ((uint16_t)0x0000)
|
||||
#define SPI_CRCLength_16b SPI_CR1_CRCL
|
||||
#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \
|
||||
((LENGTH) == SPI_CRCLength_16b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CPOL_Low ((uint16_t)0x0000)
|
||||
#define SPI_CPOL_High SPI_CR1_CPOL
|
||||
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
|
||||
((CPOL) == SPI_CPOL_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Phase
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CPHA_1Edge ((uint16_t)0x0000)
|
||||
#define SPI_CPHA_2Edge SPI_CR1_CPHA
|
||||
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
|
||||
((CPHA) == SPI_CPHA_2Edge))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Slave_Select_management
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_NSS_Soft SPI_CR1_SSM
|
||||
#define SPI_NSS_Hard ((uint16_t)0x0000)
|
||||
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
|
||||
((NSS) == SPI_NSS_Hard))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_BaudRate_Prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
|
||||
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
|
||||
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
|
||||
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
|
||||
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
|
||||
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
|
||||
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
|
||||
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
|
||||
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_4) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_8) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_16) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_32) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_64) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_128) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_256))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_MSB_LSB_transmission
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
|
||||
#define SPI_FirstBit_LSB SPI_CR1_LSBFIRST
|
||||
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
|
||||
((BIT) == SPI_FirstBit_LSB))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
|
||||
#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
|
||||
#define I2S_Mode_MasterTx ((uint16_t)0x0200)
|
||||
#define I2S_Mode_MasterRx ((uint16_t)0x0300)
|
||||
#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
|
||||
((MODE) == I2S_Mode_SlaveRx) || \
|
||||
((MODE) == I2S_Mode_MasterTx)|| \
|
||||
((MODE) == I2S_Mode_MasterRx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_Standard
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_Standard_Phillips ((uint16_t)0x0000)
|
||||
#define I2S_Standard_MSB ((uint16_t)0x0010)
|
||||
#define I2S_Standard_LSB ((uint16_t)0x0020)
|
||||
#define I2S_Standard_PCMShort ((uint16_t)0x0030)
|
||||
#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
|
||||
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
|
||||
((STANDARD) == I2S_Standard_MSB) || \
|
||||
((STANDARD) == I2S_Standard_LSB) || \
|
||||
((STANDARD) == I2S_Standard_PCMShort) || \
|
||||
((STANDARD) == I2S_Standard_PCMLong))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_Data_Format
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_DataFormat_16b ((uint16_t)0x0000)
|
||||
#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
|
||||
#define I2S_DataFormat_24b ((uint16_t)0x0003)
|
||||
#define I2S_DataFormat_32b ((uint16_t)0x0005)
|
||||
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
|
||||
((FORMAT) == I2S_DataFormat_16bextended) || \
|
||||
((FORMAT) == I2S_DataFormat_24b) || \
|
||||
((FORMAT) == I2S_DataFormat_32b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_MCLK_Output
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_MCLKOutput_Enable SPI_I2SPR_MCKOE
|
||||
#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
|
||||
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
|
||||
((OUTPUT) == I2S_MCLKOutput_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_Audio_Frequency
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_AudioFreq_192k ((uint32_t)192000)
|
||||
#define I2S_AudioFreq_96k ((uint32_t)96000)
|
||||
#define I2S_AudioFreq_48k ((uint32_t)48000)
|
||||
#define I2S_AudioFreq_44k ((uint32_t)44100)
|
||||
#define I2S_AudioFreq_32k ((uint32_t)32000)
|
||||
#define I2S_AudioFreq_22k ((uint32_t)22050)
|
||||
#define I2S_AudioFreq_16k ((uint32_t)16000)
|
||||
#define I2S_AudioFreq_11k ((uint32_t)11025)
|
||||
#define I2S_AudioFreq_8k ((uint32_t)8000)
|
||||
#define I2S_AudioFreq_Default ((uint32_t)2)
|
||||
|
||||
#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
|
||||
((FREQ) <= I2S_AudioFreq_192k)) || \
|
||||
((FREQ) == I2S_AudioFreq_Default))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_CPOL_Low ((uint16_t)0x0000)
|
||||
#define I2S_CPOL_High SPI_I2SCFGR_CKPOL
|
||||
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
|
||||
((CPOL) == I2S_CPOL_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_FIFO_reception_threshold
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000)
|
||||
#define SPI_RxFIFOThreshold_QF SPI_CR2_FRXTH
|
||||
#define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \
|
||||
((THRESHOLD) == SPI_RxFIFOThreshold_QF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_DMA_transfer_requests
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_DMAReq_Tx SPI_CR2_TXDMAEN
|
||||
#define SPI_I2S_DMAReq_Rx SPI_CR2_RXDMAEN
|
||||
#define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_last_DMA_transfers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000)
|
||||
#define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000)
|
||||
#define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000)
|
||||
#define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000)
|
||||
#define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \
|
||||
((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \
|
||||
((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \
|
||||
((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup SPI_NSS_internal_software_management
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_NSSInternalSoft_Set SPI_CR1_SSI
|
||||
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
|
||||
#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
|
||||
((INTERNAL) == SPI_NSSInternalSoft_Reset))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_Transmit_Receive
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CRC_Tx ((uint8_t)0x00)
|
||||
#define SPI_CRC_Rx ((uint8_t)0x01)
|
||||
#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_direction_transmit_receive
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_Direction_Rx ((uint16_t)0xBFFF)
|
||||
#define SPI_Direction_Tx ((uint16_t)0x4000)
|
||||
#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
|
||||
((DIRECTION) == SPI_Direction_Tx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_IT_TXE ((uint8_t)0x71)
|
||||
#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
|
||||
#define SPI_I2S_IT_ERR ((uint8_t)0x50)
|
||||
|
||||
#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
|
||||
((IT) == SPI_I2S_IT_RXNE) || \
|
||||
((IT) == SPI_I2S_IT_ERR))
|
||||
|
||||
#define I2S_IT_UDR ((uint8_t)0x53)
|
||||
#define SPI_IT_MODF ((uint8_t)0x55)
|
||||
#define SPI_I2S_IT_OVR ((uint8_t)0x56)
|
||||
#define SPI_I2S_IT_FRE ((uint8_t)0x58)
|
||||
|
||||
#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
|
||||
((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \
|
||||
((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SPI_transmission_fifo_status_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000)
|
||||
#define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800)
|
||||
#define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000)
|
||||
#define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_reception_fifo_status_level
|
||||
* @{
|
||||
*/
|
||||
#define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000)
|
||||
#define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200)
|
||||
#define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400)
|
||||
#define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SPI_I2S_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_FLAG_RXNE SPI_SR_RXNE
|
||||
#define SPI_I2S_FLAG_TXE SPI_SR_TXE
|
||||
#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
|
||||
#define I2S_FLAG_UDR SPI_SR_UDR
|
||||
#define SPI_FLAG_CRCERR SPI_SR_CRCERR
|
||||
#define SPI_FLAG_MODF SPI_SR_MODF
|
||||
#define SPI_I2S_FLAG_OVR SPI_SR_OVR
|
||||
#define SPI_I2S_FLAG_BSY SPI_SR_BSY
|
||||
#define SPI_I2S_FLAG_FRE SPI_SR_FRE
|
||||
|
||||
|
||||
|
||||
#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
|
||||
#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
|
||||
((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
|
||||
((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
|
||||
((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \
|
||||
((FLAG) == I2S_FLAG_UDR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_polynomial
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
|
||||
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
|
||||
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
|
||||
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
|
||||
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
|
||||
void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
|
||||
void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold);
|
||||
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
|
||||
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
|
||||
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
|
||||
/* Data transfers functions ***************************************************/
|
||||
void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data);
|
||||
void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data);
|
||||
uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx);
|
||||
uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx);
|
||||
|
||||
/* Hardware CRC Calculation functions *****************************************/
|
||||
void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength);
|
||||
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_TransmitCRC(SPI_TypeDef* SPIx);
|
||||
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
|
||||
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
|
||||
|
||||
/* DMA transfers management functions *****************************************/
|
||||
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
|
||||
void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
|
||||
uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx);
|
||||
uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx);
|
||||
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
|
||||
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
|
||||
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F0XX_SPI_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,224 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_syscfg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file contains all the functions prototypes for the SYSCFG firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*!< Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0XX_SYSCFG_H
|
||||
#define __STM32F0XX_SYSCFG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!< Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SYSCFG
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SYSCFG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_EXTI_Port_Sources
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_PortSourceGPIOA ((uint8_t)0x00)
|
||||
#define EXTI_PortSourceGPIOB ((uint8_t)0x01)
|
||||
#define EXTI_PortSourceGPIOC ((uint8_t)0x02)
|
||||
#define EXTI_PortSourceGPIOD ((uint8_t)0x03)
|
||||
#define EXTI_PortSourceGPIOF ((uint8_t)0x05)
|
||||
|
||||
#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_EXTI_Pin_sources
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_PinSource0 ((uint8_t)0x00)
|
||||
#define EXTI_PinSource1 ((uint8_t)0x01)
|
||||
#define EXTI_PinSource2 ((uint8_t)0x02)
|
||||
#define EXTI_PinSource3 ((uint8_t)0x03)
|
||||
#define EXTI_PinSource4 ((uint8_t)0x04)
|
||||
#define EXTI_PinSource5 ((uint8_t)0x05)
|
||||
#define EXTI_PinSource6 ((uint8_t)0x06)
|
||||
#define EXTI_PinSource7 ((uint8_t)0x07)
|
||||
#define EXTI_PinSource8 ((uint8_t)0x08)
|
||||
#define EXTI_PinSource9 ((uint8_t)0x09)
|
||||
#define EXTI_PinSource10 ((uint8_t)0x0A)
|
||||
#define EXTI_PinSource11 ((uint8_t)0x0B)
|
||||
#define EXTI_PinSource12 ((uint8_t)0x0C)
|
||||
#define EXTI_PinSource13 ((uint8_t)0x0D)
|
||||
#define EXTI_PinSource14 ((uint8_t)0x0E)
|
||||
#define EXTI_PinSource15 ((uint8_t)0x0F)
|
||||
|
||||
#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
|
||||
((PINSOURCE) == EXTI_PinSource1) || \
|
||||
((PINSOURCE) == EXTI_PinSource2) || \
|
||||
((PINSOURCE) == EXTI_PinSource3) || \
|
||||
((PINSOURCE) == EXTI_PinSource4) || \
|
||||
((PINSOURCE) == EXTI_PinSource5) || \
|
||||
((PINSOURCE) == EXTI_PinSource6) || \
|
||||
((PINSOURCE) == EXTI_PinSource7) || \
|
||||
((PINSOURCE) == EXTI_PinSource8) || \
|
||||
((PINSOURCE) == EXTI_PinSource9) || \
|
||||
((PINSOURCE) == EXTI_PinSource10) || \
|
||||
((PINSOURCE) == EXTI_PinSource11) || \
|
||||
((PINSOURCE) == EXTI_PinSource12) || \
|
||||
((PINSOURCE) == EXTI_PinSource13) || \
|
||||
((PINSOURCE) == EXTI_PinSource14) || \
|
||||
((PINSOURCE) == EXTI_PinSource15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_Memory_Remap_Config
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
|
||||
#define SYSCFG_MemoryRemap_SystemMemory ((uint8_t)0x01)
|
||||
#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
|
||||
|
||||
|
||||
#define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
|
||||
((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \
|
||||
((REMAP) == SYSCFG_MemoryRemap_SRAM))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_DMA_Remap_Config
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_DMARemap_TIM17 SYSCFG_CFGR1_TIM17_DMA_RMP /* Remap TIM17 DMA requests from channel1 to channel2 */
|
||||
#define SYSCFG_DMARemap_TIM16 SYSCFG_CFGR1_TIM16_DMA_RMP /* Remap TIM16 DMA requests from channel3 to channel4 */
|
||||
#define SYSCFG_DMARemap_USART1Rx SYSCFG_CFGR1_USART1RX_DMA_RMP /* Remap USART1 Rx DMA requests from channel3 to channel5 */
|
||||
#define SYSCFG_DMARemap_USART1Tx SYSCFG_CFGR1_USART1TX_DMA_RMP /* Remap USART1 Tx DMA requests from channel2 to channel4 */
|
||||
#define SYSCFG_DMARemap_ADC1 SYSCFG_CFGR1_ADC_DMA_RMP /* Remap ADC1 DMA requests from channel1 to channel2 */
|
||||
|
||||
#define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17) || \
|
||||
((REMAP) == SYSCFG_DMARemap_TIM16) || \
|
||||
((REMAP) == SYSCFG_DMARemap_USART1Rx) || \
|
||||
((REMAP) == SYSCFG_DMARemap_USART1Tx) || \
|
||||
((REMAP) == SYSCFG_DMARemap_ADC1))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_I2C_FastModePlus_Config
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_I2CFastModePlus_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /* Enable Fast Mode Plus on PB6 */
|
||||
#define SYSCFG_I2CFastModePlus_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /* Enable Fast Mode Plus on PB7 */
|
||||
#define SYSCFG_I2CFastModePlus_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /* Enable Fast Mode Plus on PB8 */
|
||||
#define SYSCFG_I2CFastModePlus_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /* Enable Fast Mode Plus on PB9 */
|
||||
|
||||
#define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6) || \
|
||||
((PIN) == SYSCFG_I2CFastModePlus_PB7) || \
|
||||
((PIN) == SYSCFG_I2CFastModePlus_PB8) || \
|
||||
((PIN) == SYSCFG_I2CFastModePlus_PB9))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_Lock_Config
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_Break_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Connects the PVD event to the Break Input of TIM1 */
|
||||
#define SYSCFG_Break_SRAMParity SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Connects the SRAM_PARITY error signal to the Break Input of TIM1 */
|
||||
#define SYSCFG_Break_Lockup SYSCFG_CFGR2_LOCKUP_LOCK /*!< Connects Lockup output of CortexM0 to the break input of TIM1 */
|
||||
|
||||
#define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD) || \
|
||||
((CONFIG) == SYSCFG_Break_SRAMParity) || \
|
||||
((CONFIG) == SYSCFG_Break_Lockup))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SYSCFG_FLAG_PE SYSCFG_CFGR2_SRAM_PE
|
||||
|
||||
#define IS_SYSCFG_FLAG(FLAG) (((FLAG) == SYSCFG_FLAG_PE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the SYSCFG configuration to the default reset state **/
|
||||
void SYSCFG_DeInit(void);
|
||||
|
||||
/* SYSCFG configuration functions *********************************************/
|
||||
void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap);
|
||||
void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState);
|
||||
void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState);
|
||||
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
|
||||
void SYSCFG_BreakConfig(uint32_t SYSCFG_Break);
|
||||
FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag);
|
||||
void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F0XX_SYSCFG_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,593 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_usart.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file contains all the functions prototypes for the USART
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0XX_USART_H
|
||||
#define __STM32F0XX_USART_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USART
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief USART Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
|
||||
The baud rate is computed using the following formula:
|
||||
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
|
||||
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
|
||||
|
||||
uint32_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref USART_Word_Length */
|
||||
|
||||
uint32_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
|
||||
This parameter can be a value of @ref USART_Stop_Bits */
|
||||
|
||||
uint32_t USART_Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref USART_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint32_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_Mode */
|
||||
|
||||
uint32_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
|
||||
or disabled.
|
||||
This parameter can be a value of @ref USART_Hardware_Flow_Control*/
|
||||
} USART_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief USART Clock Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_Clock */
|
||||
|
||||
uint32_t USART_CPOL; /*!< Specifies the steady state of the serial clock.
|
||||
This parameter can be a value of @ref USART_Clock_Polarity */
|
||||
|
||||
uint32_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
|
||||
This parameter can be a value of @ref USART_Clock_Phase */
|
||||
|
||||
uint32_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
|
||||
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||
This parameter can be a value of @ref USART_Last_Bit */
|
||||
} USART_ClockInitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup USART_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
|
||||
((PERIPH) == USART2))
|
||||
|
||||
#define IS_USART_1_PERIPH(PERIPH) (((PERIPH) == USART1))
|
||||
|
||||
/** @defgroup USART_Word_Length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_WordLength_8b ((uint32_t)0x00000000)
|
||||
#define USART_WordLength_9b USART_CR1_M
|
||||
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
|
||||
((LENGTH) == USART_WordLength_9b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Stop_Bits
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_StopBits_1 ((uint32_t)0x00000000)
|
||||
#define USART_StopBits_2 ((uint32_t)USART_CR2_STOP_1)
|
||||
#define USART_StopBits_1_5 ((uint32_t)USART_CR2_STOP_0 | USART_CR2_STOP_1)
|
||||
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
|
||||
((STOPBITS) == USART_StopBits_2) || \
|
||||
((STOPBITS) == USART_StopBits_1_5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Parity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_Parity_No ((uint32_t)0x00000000)
|
||||
#define USART_Parity_Even ((uint32_t)USART_CR1_PCE)
|
||||
#define USART_Parity_Odd ((uint32_t)USART_CR1_PCE | USART_CR1_PS)
|
||||
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
|
||||
((PARITY) == USART_Parity_Even) || \
|
||||
((PARITY) == USART_Parity_Odd))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_Mode_Rx USART_CR1_RE
|
||||
#define USART_Mode_Tx USART_CR1_TE
|
||||
#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && \
|
||||
((MODE) != (uint32_t)0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Hardware_Flow_Control
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_HardwareFlowControl_None ((uint32_t)0x00000000)
|
||||
#define USART_HardwareFlowControl_RTS ((uint32_t)USART_CR3_RTSE)
|
||||
#define USART_HardwareFlowControl_CTS ((uint32_t)USART_CR3_CTSE)
|
||||
#define USART_HardwareFlowControl_RTS_CTS ((uint32_t)USART_CR3_RTSE | USART_CR3_CTSE)
|
||||
#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
|
||||
(((CONTROL) == USART_HardwareFlowControl_None) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_RTS) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_CTS) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_Clock_Disable ((uint32_t)0x00000000)
|
||||
#define USART_Clock_Enable USART_CR2_CLKEN
|
||||
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
|
||||
((CLOCK) == USART_Clock_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_CPOL_Low ((uint32_t)0x00000000)
|
||||
#define USART_CPOL_High USART_CR2_CPOL
|
||||
#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock_Phase
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_CPHA_1Edge ((uint32_t)0x00000000)
|
||||
#define USART_CPHA_2Edge USART_CR2_CPHA
|
||||
#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Last_Bit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_LastBit_Disable ((uint32_t)0x00000000)
|
||||
#define USART_LastBit_Enable USART_CR2_LBCL
|
||||
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
|
||||
((LASTBIT) == USART_LastBit_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_DMA_Requests
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_DMAReq_Tx USART_CR3_DMAT
|
||||
#define USART_DMAReq_Rx USART_CR3_DMAR
|
||||
#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint32_t)0xFFFFFF3F) == 0x00) && \
|
||||
((DMAREQ) != (uint32_t)0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_DMA_Recception_Error
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_DMAOnError_Enable ((uint32_t)0x00000000)
|
||||
#define USART_DMAOnError_Disable USART_CR3_DDRE
|
||||
#define IS_USART_DMAONERROR(DMAERROR) (((DMAERROR) == USART_DMAOnError_Disable)|| \
|
||||
((DMAERROR) == USART_DMAOnError_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_MuteMode_WakeUp_methods
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_WakeUp_IdleLine ((uint32_t)0x00000000)
|
||||
#define USART_WakeUp_AddressMark USART_CR1_WAKE
|
||||
#define IS_USART_MUTEMODE_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
|
||||
((WAKEUP) == USART_WakeUp_AddressMark))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Address_Detection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_AddressLength_4b ((uint32_t)0x00000000)
|
||||
#define USART_AddressLength_7b USART_CR2_ADDM7
|
||||
#define IS_USART_ADDRESS_DETECTION(ADDRESS) (((ADDRESS) == USART_AddressLength_4b) || \
|
||||
((ADDRESS) == USART_AddressLength_7b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_StopMode_WakeUp_methods
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_WakeUpSource_AddressMatch ((uint32_t)0x00000000)
|
||||
#define USART_WakeUpSource_StartBit ((uint32_t)USART_CR3_WUS_1)
|
||||
#define USART_WakeUpSource_RXNE ((uint32_t)USART_CR3_WUS_0 | USART_CR3_WUS_1)
|
||||
#define IS_USART_STOPMODE_WAKEUPSOURCE(SOURCE) (((SOURCE) == USART_WakeUpSource_AddressMatch) || \
|
||||
((SOURCE) == USART_WakeUpSource_StartBit) || \
|
||||
((SOURCE) == USART_WakeUpSource_RXNE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_LIN_Break_Detection_Length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_LINBreakDetectLength_10b ((uint32_t)0x00000000)
|
||||
#define USART_LINBreakDetectLength_11b USART_CR2_LBDL
|
||||
#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
|
||||
(((LENGTH) == USART_LINBreakDetectLength_10b) || \
|
||||
((LENGTH) == USART_LINBreakDetectLength_11b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_IrDA_Low_Power
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_IrDAMode_LowPower USART_CR3_IRLP
|
||||
#define USART_IrDAMode_Normal ((uint32_t)0x00000000)
|
||||
#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
|
||||
((MODE) == USART_IrDAMode_Normal))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_DE_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_DEPolarity_High ((uint32_t)0x00000000)
|
||||
#define USART_DEPolarity_Low USART_CR3_DEP
|
||||
#define IS_USART_DE_POLARITY(POLARITY) (((POLARITY) == USART_DEPolarity_Low) || \
|
||||
((POLARITY) == USART_DEPolarity_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Inversion_Pins
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_InvPin_Tx USART_CR2_TXINV
|
||||
#define USART_InvPin_Rx USART_CR2_RXINV
|
||||
#define IS_USART_INVERSTION_PIN(PIN) ((((PIN) & (uint32_t)0xFFFCFFFF) == 0x00) && \
|
||||
((PIN) != (uint32_t)0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_AutoBaudRate_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_AutoBaudRate_StartBit ((uint32_t)0x00000000)
|
||||
#define USART_AutoBaudRate_FallingEdge USART_CR2_ABRMODE_0
|
||||
#define IS_USART_AUTOBAUDRATE_MODE(MODE) (((MODE) == USART_AutoBaudRate_StartBit) || \
|
||||
((MODE) == USART_AutoBaudRate_FallingEdge))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_OVR_DETECTION
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_OVRDetection_Enable ((uint32_t)0x00000000)
|
||||
#define USART_OVRDetection_Disable USART_CR3_OVRDIS
|
||||
#define IS_USART_OVRDETECTION(OVR) (((OVR) == USART_OVRDetection_Enable)|| \
|
||||
((OVR) == USART_OVRDetection_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup USART_Request
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_Request_ABRRQ USART_RQR_ABRRQ
|
||||
#define USART_Request_SBKRQ USART_RQR_SBKRQ
|
||||
#define USART_Request_MMRQ USART_RQR_MMRQ
|
||||
#define USART_Request_RXFRQ USART_RQR_RXFRQ
|
||||
#define USART_Request_TXFRQ USART_RQR_TXFRQ
|
||||
|
||||
#define IS_USART_REQUEST(REQUEST) (((REQUEST) == USART_Request_TXFRQ) || \
|
||||
((REQUEST) == USART_Request_RXFRQ) || \
|
||||
((REQUEST) == USART_Request_MMRQ) || \
|
||||
((REQUEST) == USART_Request_SBKRQ) || \
|
||||
((REQUEST) == USART_Request_ABRRQ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Flags
|
||||
* @{
|
||||
*/
|
||||
#define USART_FLAG_REACK USART_ISR_REACK
|
||||
#define USART_FLAG_TEACK USART_ISR_TEACK
|
||||
#define USART_FLAG_WU USART_ISR_WUF
|
||||
#define USART_FLAG_RWU USART_ISR_RWU
|
||||
#define USART_FLAG_SBK USART_ISR_SBKF
|
||||
#define USART_FLAG_CM USART_ISR_CMF
|
||||
#define USART_FLAG_BUSY USART_ISR_BUSY
|
||||
#define USART_FLAG_ABRF USART_ISR_ABRF
|
||||
#define USART_FLAG_ABRE USART_ISR_ABRE
|
||||
#define USART_FLAG_EOB USART_ISR_EOBF
|
||||
#define USART_FLAG_RTO USART_ISR_RTOF
|
||||
#define USART_FLAG_nCTSS USART_ISR_CTS
|
||||
#define USART_FLAG_CTS USART_ISR_CTSIF
|
||||
#define USART_FLAG_LBD USART_ISR_LBD
|
||||
#define USART_FLAG_TXE USART_ISR_TXE
|
||||
#define USART_FLAG_TC USART_ISR_TC
|
||||
#define USART_FLAG_RXNE USART_ISR_RXNE
|
||||
#define USART_FLAG_IDLE USART_ISR_IDLE
|
||||
#define USART_FLAG_ORE USART_ISR_ORE
|
||||
#define USART_FLAG_NE USART_ISR_NE
|
||||
#define USART_FLAG_FE USART_ISR_FE
|
||||
#define USART_FLAG_PE USART_ISR_PE
|
||||
#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
|
||||
((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
|
||||
((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
|
||||
((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
|
||||
((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
|
||||
((FLAG) == USART_FLAG_nCTSS) || ((FLAG) == USART_FLAG_RTO) || \
|
||||
((FLAG) == USART_FLAG_EOB) || ((FLAG) == USART_FLAG_ABRE) || \
|
||||
((FLAG) == USART_FLAG_ABRF) || ((FLAG) == USART_FLAG_BUSY) || \
|
||||
((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_SBK) || \
|
||||
((FLAG) == USART_FLAG_RWU) || ((FLAG) == USART_FLAG_WU) || \
|
||||
((FLAG) == USART_FLAG_TEACK)|| ((FLAG) == USART_FLAG_REACK))
|
||||
|
||||
#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG) == USART_FLAG_WU) || ((FLAG) == USART_FLAG_TC) || \
|
||||
((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_ORE) || \
|
||||
((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
|
||||
((FLAG) == USART_FLAG_LBD) || ((FLAG) == USART_FLAG_CTS) || \
|
||||
((FLAG) == USART_FLAG_RTO) || ((FLAG) == USART_FLAG_EOB) || \
|
||||
((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_PE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Interrupt_definition
|
||||
* @brief USART Interrupt definition
|
||||
* USART_IT possible values
|
||||
* Elements values convention: 0xZZZZYYXX
|
||||
* XX: Position of the corresponding Interrupt
|
||||
* YY: Register index
|
||||
* ZZZZ: Flag position
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_IT_WU ((uint32_t)0x00140316)
|
||||
#define USART_IT_CM ((uint32_t)0x0011010E)
|
||||
#define USART_IT_EOB ((uint32_t)0x000C011B)
|
||||
#define USART_IT_RTO ((uint32_t)0x000B011A)
|
||||
#define USART_IT_PE ((uint32_t)0x00000108)
|
||||
#define USART_IT_TXE ((uint32_t)0x00070107)
|
||||
#define USART_IT_TC ((uint32_t)0x00060106)
|
||||
#define USART_IT_RXNE ((uint32_t)0x00050105)
|
||||
#define USART_IT_IDLE ((uint32_t)0x00040104)
|
||||
#define USART_IT_LBD ((uint32_t)0x00080206)
|
||||
#define USART_IT_CTS ((uint32_t)0x0009030A)
|
||||
#define USART_IT_ERR ((uint32_t)0x00000300)
|
||||
#define USART_IT_ORE ((uint32_t)0x00030300)
|
||||
#define USART_IT_NE ((uint32_t)0x00020300)
|
||||
#define USART_IT_FE ((uint32_t)0x00010300)
|
||||
|
||||
#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
|
||||
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
|
||||
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
|
||||
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR) || \
|
||||
((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
|
||||
((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
|
||||
|
||||
#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
|
||||
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
|
||||
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
|
||||
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
|
||||
((IT) == USART_IT_NE) || ((IT) == USART_IT_FE) || \
|
||||
((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
|
||||
((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
|
||||
|
||||
#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_PE) || \
|
||||
((IT) == USART_IT_FE) || ((IT) == USART_IT_NE) || \
|
||||
((IT) == USART_IT_ORE) || ((IT) == USART_IT_IDLE) || \
|
||||
((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || \
|
||||
((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
|
||||
((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Global_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x005B8D81))
|
||||
#define IS_USART_DE_ASSERTION_DEASSERTION_TIME(TIME) ((TIME) <= 0x1F)
|
||||
#define IS_USART_AUTO_RETRY_COUNTER(COUNTER) ((COUNTER) <= 0x7)
|
||||
#define IS_USART_TIMEOUT(TIMEOUT) ((TIMEOUT) <= 0x00FFFFFF)
|
||||
#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void USART_DeInit(USART_TypeDef* USARTx);
|
||||
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
|
||||
void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
|
||||
void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
|
||||
void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
|
||||
void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState);
|
||||
void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
|
||||
void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState);
|
||||
void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut);
|
||||
|
||||
/* STOP Mode functions ********************************************************/
|
||||
void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource);
|
||||
|
||||
/* AutoBaudRate functions *****************************************************/
|
||||
void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate);
|
||||
void USART_AutoBaudRateNewRequest(USART_TypeDef* USARTx);
|
||||
|
||||
/* Data transfers functions ***************************************************/
|
||||
void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
|
||||
uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
|
||||
|
||||
/* Multi-Processor Communication functions ************************************/
|
||||
void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
|
||||
void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp);
|
||||
void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength);
|
||||
/* LIN mode functions *********************************************************/
|
||||
void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength);
|
||||
void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
|
||||
/* Half-duplex mode function **************************************************/
|
||||
void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
|
||||
/* Smartcard mode functions ***************************************************/
|
||||
void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
|
||||
void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount);
|
||||
void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength);
|
||||
|
||||
/* IrDA mode functions ********************************************************/
|
||||
void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode);
|
||||
void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
|
||||
/* RS485 mode functions *******************************************************/
|
||||
void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity);
|
||||
void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime);
|
||||
void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime);
|
||||
|
||||
/* DMA transfers management functions *****************************************/
|
||||
void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState);
|
||||
void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState);
|
||||
void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState);
|
||||
void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection);
|
||||
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG);
|
||||
void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG);
|
||||
ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT);
|
||||
void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0XX_USART_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_wwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file contains all the functions prototypes for the WWDG
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0XX_WWDG_H
|
||||
#define __STM32F0XX_WWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
|
||||
#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
|
||||
#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
|
||||
#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
|
||||
#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
|
||||
((PRESCALER) == WWDG_Prescaler_2) || \
|
||||
((PRESCALER) == WWDG_Prescaler_4) || \
|
||||
((PRESCALER) == WWDG_Prescaler_8))
|
||||
#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
|
||||
#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Function used to set the WWDG configuration to the default reset state ****/
|
||||
void WWDG_DeInit(void);
|
||||
|
||||
/* Prescaler, Refresh window and Counter configuration functions **************/
|
||||
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
|
||||
void WWDG_SetWindowValue(uint8_t WindowValue);
|
||||
void WWDG_EnableIT(void);
|
||||
void WWDG_SetCounter(uint8_t Counter);
|
||||
|
||||
/* WWDG activation functions **************************************************/
|
||||
void WWDG_Enable(uint8_t Counter);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
FlagStatus WWDG_GetFlagStatus(void);
|
||||
void WWDG_ClearFlag(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0XX_WWDG_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,156 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0_discovery.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file contains definitions for STM32F0-Discovery's Leds, push-
|
||||
* buttons hardware resources.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0_DISCOVERY_H
|
||||
#define __STM32F0_DISCOVERY_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/** @addtogroup Utilities
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F0_DISCOVERY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F0_DISCOVERY_LOW_LEVEL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F0_DISCOVERY_LOW_LEVEL_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
LED3 = 0,
|
||||
LED4 = 1
|
||||
} Led_TypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
BUTTON_USER = 0,
|
||||
} Button_TypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
BUTTON_MODE_GPIO = 0,
|
||||
BUTTON_MODE_EXTI = 1
|
||||
} ButtonMode_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F0_DISCOVERY_LOW_LEVEL_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F0_DISCOVERY_LOW_LEVEL_LED
|
||||
* @{
|
||||
*/
|
||||
#define LEDn 2
|
||||
|
||||
#define LED3_PIN GPIO_Pin_9
|
||||
#define LED3_GPIO_PORT GPIOC
|
||||
#define LED3_GPIO_CLK RCC_AHBPeriph_GPIOC
|
||||
|
||||
#define LED4_PIN GPIO_Pin_8
|
||||
#define LED4_GPIO_PORT GPIOC
|
||||
#define LED4_GPIO_CLK RCC_AHBPeriph_GPIOC
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SSTM32F0_DISCOVERY_LOW_LEVEL_BUTTON
|
||||
* @{
|
||||
*/
|
||||
#define BUTTONn 1
|
||||
|
||||
/**
|
||||
* @brief USER push-button
|
||||
*/
|
||||
#define USER_BUTTON_PIN GPIO_Pin_0
|
||||
#define USER_BUTTON_GPIO_PORT GPIOA
|
||||
#define USER_BUTTON_GPIO_CLK RCC_AHBPeriph_GPIOA
|
||||
#define USER_BUTTON_EXTI_LINE EXTI_Line0
|
||||
#define USER_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOA
|
||||
#define USER_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource0
|
||||
#define USER_BUTTON_EXTI_IRQn EXTI0_1_IRQn
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup STM32F0_DISCOVERY_LOW_LEVEL_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F0_DISCOVERY_LOW_LEVEL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
void STM_EVAL_LEDInit(Led_TypeDef Led);
|
||||
void STM_EVAL_LEDOn(Led_TypeDef Led);
|
||||
void STM_EVAL_LEDOff(Led_TypeDef Led);
|
||||
void STM_EVAL_LEDToggle(Led_TypeDef Led);
|
||||
void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode);
|
||||
uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F0_DISCOVERY_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,81 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file IO_Toggle/stm32f0xx_conf.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief Library configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F0XX_CONF_H
|
||||
#define __STM32F0XX_CONF_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Comment the line below to disable peripheral header file inclusion */
|
||||
#include "stm32f0xx_adc.h"
|
||||
#include "stm32f0xx_cec.h"
|
||||
#include "stm32f0xx_crc.h"
|
||||
#include "stm32f0xx_comp.h"
|
||||
#include "stm32f0xx_dac.h"
|
||||
#include "stm32f0xx_dbgmcu.h"
|
||||
#include "stm32f0xx_dma.h"
|
||||
#include "stm32f0xx_exti.h"
|
||||
#include "stm32f0xx_flash.h"
|
||||
#include "stm32f0xx_gpio.h"
|
||||
#include "stm32f0xx_syscfg.h"
|
||||
#include "stm32f0xx_i2c.h"
|
||||
#include "stm32f0xx_iwdg.h"
|
||||
#include "stm32f0xx_pwr.h"
|
||||
#include "stm32f0xx_rcc.h"
|
||||
#include "stm32f0xx_rtc.h"
|
||||
#include "stm32f0xx_spi.h"
|
||||
#include "stm32f0xx_tim.h"
|
||||
#include "stm32f0xx_usart.h"
|
||||
#include "stm32f0xx_wwdg.h"
|
||||
#include "stm32f0xx_misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Uncomment the line below to expanse the "assert_param" macro in the
|
||||
Standard Peripheral Library drivers code */
|
||||
/* #define USE_FULL_ASSERT 1 */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function which reports
|
||||
* the name of the source file and the source line number of the call
|
||||
* that failed. If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#endif /* __STM32F0XX_CONF_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f0xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Header File.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f0xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Define to prevent recursive inclusion
|
||||
*/
|
||||
#ifndef __SYSTEM_STM32F0XX_H
|
||||
#define __SYSTEM_STM32F0XX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F0xx_System_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup STM32F0xx_System_Exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F0xx_System_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F0xx_System_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F0xx_System_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SYSTEM_STM32F0XX_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,606 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_cec.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Consumer Electronics Control (CEC) peripheral:
|
||||
* + Initialization and Configuration
|
||||
* + Data transfers functions
|
||||
* + Interrupts and flags management
|
||||
*
|
||||
* @verbatim
|
||||
==============================================================================
|
||||
##### CEC features #####
|
||||
==============================================================================
|
||||
[..] This device provides some features:
|
||||
(#) Supports HDMI-CEC specification 1.4.
|
||||
(#) Supports two source clocks(HSI/244 or LSE).
|
||||
(#) Works in stop mode(without APB clock, but with CEC clock 32KHz).
|
||||
It can genarate an interrupt in the CEC clock domain that the CPU
|
||||
wakes up from the low power mode.
|
||||
(#) Configurable Signal Free Time before of transmission start. The
|
||||
number of nominal data bit periods waited before transmission can be
|
||||
ruled by Hardware or Software.
|
||||
(#) Configurable Peripheral Address (multi-addressing configuration).
|
||||
(#) Supports listen mode.The CEC Messages addressed to different destination
|
||||
can be received without interfering with CEC bus when Listen mode option is enabled.
|
||||
(#) Configurable Rx-Tolerance(Standard and Extended tolerance margin).
|
||||
(#) Error detection with configurable error bit generation.
|
||||
(#) Arbitration lost error in the case of two CEC devices starting at the same time.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..] This driver provides functions to configure and program the CEC device,
|
||||
follow steps below:
|
||||
(#) The source clock can be configured using:
|
||||
(++) RCC_CECCLKConfig(RCC_CECCLK_HSI_Div244) for HSI(Default)
|
||||
(++) RCC_CECCLKConfig(RCC_CECCLK_LSE) for LSE.
|
||||
(#) Enable CEC peripheral clock using RCC_APBPeriphClockCmd(RCC_APBPeriph_CEC, ENABLE).
|
||||
(#) Peripherals alternate function.
|
||||
(++) Connect the pin to the desired peripherals' Alternate Function (AF) using
|
||||
GPIO_PinAFConfig() function.
|
||||
(++) Configure the desired pin in alternate function by:
|
||||
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
|
||||
(++) Select the type open-drain and output speed via GPIO_OType
|
||||
and GPIO_Speed members.
|
||||
(++) Call GPIO_Init() function.
|
||||
(#) Configure the Signal Free Time, Rx Tolerance, Stop reception generation
|
||||
and Bit error generation using the CEC_Init() function.
|
||||
The function CEC_Init() must be called when the CEC peripheral is disabled.
|
||||
(#) Configure the CEC own address by calling the fuction CEC_OwnAddressConfig().
|
||||
(#) Optionally, you can configure the Listen mode using the function CEC_ListenModeCmd().
|
||||
(#) Enable the NVIC and the corresponding interrupt using the function
|
||||
CEC_ITConfig() if you need to use interrupt mode.
|
||||
CEC_ITConfig() must be called before enabling the CEC peripheral.
|
||||
(#) Enable the CEC using the CEC_Cmd() function.
|
||||
(#) Charge the first data byte in the TXDR register using CEC_SendDataByte().
|
||||
(#) Enable the transmission of the Byte of a CEC message using CEC_StartOfMessage()
|
||||
(#) Transmit single data through the CEC peripheral using CEC_SendDataByte()
|
||||
and Receive the last transmitted byte using CEC_ReceiveDataByte().
|
||||
(#) Enable the CEC_EndOfMessage() in order to indicate the last byte of the message.
|
||||
[..]
|
||||
(@) If the listen mode is enabled, Stop reception generation and Bit error generation
|
||||
must be in reset state.
|
||||
(@) If the CEC message consists of only 1 byte, the function CEC_EndOfMessage()
|
||||
must be called before CEC_StartOfMessage().
|
||||
|
||||
@endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_cec.h"
|
||||
#include "stm32f0xx_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CEC
|
||||
* @brief CEC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define BROADCAST_ADDRESS ((uint32_t)0x0000F)
|
||||
#define CFGR_CLEAR_MASK ((uint32_t)0x7000FE00) /* CFGR register Mask */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CEC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to initialize:
|
||||
(+) CEC own addresses
|
||||
(+) CEC Signal Free Time
|
||||
(+) CEC Rx Tolerance
|
||||
(+) CEC Stop Reception
|
||||
(+) CEC Bit Rising Error
|
||||
(+) CEC Long Bit Period Error
|
||||
[..] This section provides also a function to configure the CEC peripheral in Listen Mode.
|
||||
Messages addressed to different destination can be received when Listen mode is
|
||||
enabled without interfering with CEC bus.
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the CEC peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_DeInit(void)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the CEC peripheral according to the specified parameters
|
||||
* in the CEC_InitStruct.
|
||||
* @note The CEC parameters must be configured before enabling the CEC peripheral.
|
||||
* @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that contains
|
||||
* the configuration information for the specified CEC peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_SIGNAL_FREE_TIME(CEC_InitStruct->CEC_SignalFreeTime));
|
||||
assert_param(IS_CEC_RX_TOLERANCE(CEC_InitStruct->CEC_RxTolerance));
|
||||
assert_param(IS_CEC_STOP_RECEPTION(CEC_InitStruct->CEC_StopReception));
|
||||
assert_param(IS_CEC_BIT_RISING_ERROR(CEC_InitStruct->CEC_BitRisingError));
|
||||
assert_param(IS_CEC_LONG_BIT_PERIOD_ERROR(CEC_InitStruct->CEC_LongBitPeriodError));
|
||||
assert_param(IS_CEC_BDR_NO_GEN_ERROR(CEC_InitStruct->CEC_BRDNoGen));
|
||||
assert_param(IS_CEC_SFT_OPTION(CEC_InitStruct->CEC_SFTOption));
|
||||
|
||||
/* Get the CEC CFGR value */
|
||||
tmpreg = CEC->CFGR;
|
||||
|
||||
/* Clear CFGR bits */
|
||||
tmpreg &= CFGR_CLEAR_MASK;
|
||||
|
||||
/* Configure the CEC peripheral */
|
||||
tmpreg |= (CEC_InitStruct->CEC_SignalFreeTime | CEC_InitStruct->CEC_RxTolerance |
|
||||
CEC_InitStruct->CEC_StopReception | CEC_InitStruct->CEC_BitRisingError |
|
||||
CEC_InitStruct->CEC_LongBitPeriodError| CEC_InitStruct->CEC_BRDNoGen |
|
||||
CEC_InitStruct->CEC_SFTOption);
|
||||
|
||||
/* Write to CEC CFGR register */
|
||||
CEC->CFGR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each CEC_InitStruct member with its default value.
|
||||
* @param CEC_InitStruct: pointer to a CEC_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct)
|
||||
{
|
||||
CEC_InitStruct->CEC_SignalFreeTime = CEC_SignalFreeTime_Standard;
|
||||
CEC_InitStruct->CEC_RxTolerance = CEC_RxTolerance_Standard;
|
||||
CEC_InitStruct->CEC_StopReception = CEC_StopReception_Off;
|
||||
CEC_InitStruct->CEC_BitRisingError = CEC_BitRisingError_Off;
|
||||
CEC_InitStruct->CEC_LongBitPeriodError = CEC_LongBitPeriodError_Off;
|
||||
CEC_InitStruct->CEC_BRDNoGen = CEC_BRDNoGen_Off;
|
||||
CEC_InitStruct->CEC_SFTOption = CEC_SFTOption_Off;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the CEC peripheral.
|
||||
* @param NewState: new state of the CEC peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_Cmd(FunctionalState NewState)
|
||||
{
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the CEC peripheral */
|
||||
CEC->CR |= CEC_CR_CECEN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the CEC peripheral */
|
||||
CEC->CR &= ~CEC_CR_CECEN;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the CEC Listen Mode.
|
||||
* @param NewState: new state of the Listen Mode.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_ListenModeCmd(FunctionalState NewState)
|
||||
{
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the Listen Mode */
|
||||
CEC->CFGR |= CEC_CFGR_LSTN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the Listen Mode */
|
||||
CEC->CFGR &= ~CEC_CFGR_LSTN;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Defines the Own Address of the CEC device.
|
||||
* @param CEC_OwnAddress: The CEC own address.
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
|
||||
{
|
||||
uint32_t tmp =0x00;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
|
||||
tmp = 1 <<(CEC_OwnAddress + 16);
|
||||
/* Set the CEC own address */
|
||||
CEC->CFGR |= tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the Own Address of the CEC device.
|
||||
* @param CEC_OwnAddress: The CEC own address.
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_OwnAddressClear(void)
|
||||
{
|
||||
/* Set the CEC own address */
|
||||
CEC->CFGR = 0x0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Group2 Data transfers functions
|
||||
* @brief Data transfers functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Data transfers functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing the CEC data transfers.The read
|
||||
access of the CEC_RXDR register can be done using the CEC_ReceiveData()function
|
||||
and returns the Rx buffered value. Whereas a write access to the CEC_TXDR can be
|
||||
done using CEC_SendData() function.
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Transmits single data through the CEC peripheral.
|
||||
* @param Data: the data to transmit.
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_SendData(uint8_t Data)
|
||||
{
|
||||
/* Transmit Data */
|
||||
CEC->TXDR = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the most recent received data by the CEC peripheral.
|
||||
* @param None
|
||||
* @retval The received data.
|
||||
*/
|
||||
uint8_t CEC_ReceiveData(void)
|
||||
{
|
||||
/* Receive Data */
|
||||
return (uint8_t)(CEC->RXDR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Starts a new message.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_StartOfMessage(void)
|
||||
{
|
||||
/* Starts of new message */
|
||||
CEC->CR |= CEC_CR_TXSOM;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Transmits message with an EOM bit.
|
||||
* @param None.
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_EndOfMessage(void)
|
||||
{
|
||||
/* The data byte will be transmitted with an EOM bit */
|
||||
CEC->CR |= CEC_CR_TXEOM;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Group3 Interrupts and flags management functions
|
||||
* @brief Interrupts and flags management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Interrupts and flags management functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to configure the CEC Interrupts
|
||||
sources and check or clear the flags or pending bits status.
|
||||
[..] The user should identify which mode will be used in his application to manage
|
||||
the communication: Polling mode or Interrupt mode.
|
||||
|
||||
[..] In polling mode, the CEC can be managed by the following flags:
|
||||
(+) CEC_FLAG_TXACKE : to indicate a missing acknowledge in transmission mode.
|
||||
(+) CEC_FLAG_TXERR : to indicate an error occurs during transmission mode.
|
||||
The initiator detects low impedance in the CEC line.
|
||||
(+) CEC_FLAG_TXUDR : to indicate if an underrun error occurs in transmission mode.
|
||||
The transmission is enabled while the software has not yet
|
||||
loaded any value into the TXDR register.
|
||||
(+) CEC_FLAG_TXEND : to indicate the end of successful transmission.
|
||||
(+) CEC_FLAG_TXBR : to indicate the next transmission data has to be written to TXDR.
|
||||
(+) CEC_FLAG_ARBLST : to indicate arbitration lost in the case of two CEC devices
|
||||
starting at the same time.
|
||||
(+) CEC_FLAG_RXACKE : to indicate a missing acknowledge in receive mode.
|
||||
(+) CEC_FLAG_LBPE : to indicate a long bit period error generated during receive mode.
|
||||
(+) CEC_FLAG_SBPE : to indicate a short bit period error generated during receive mode.
|
||||
(+) CEC_FLAG_BRE : to indicate a bit rising error generated during receive mode.
|
||||
(+) CEC_FLAG_RXOVR : to indicate if an overrun error occur while receiving a CEC message.
|
||||
A byte is not yet received while a new byte is stored in the RXDR register.
|
||||
(+) CEC_FLAG_RXEND : to indicate the end Of reception
|
||||
(+) CEC_FLAG_RXBR : to indicate a new byte has been received from the CEC line and
|
||||
stored into the RXDR buffer.
|
||||
[..]
|
||||
(@)In this Mode, it is advised to use the following functions:
|
||||
FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG);
|
||||
void CEC_ClearFlag(uint16_t CEC_FLAG);
|
||||
|
||||
[..] In Interrupt mode, the CEC can be managed by the following interrupt sources:
|
||||
(+) CEC_IT_TXACKE : to indicate a TX Missing acknowledge
|
||||
(+) CEC_IT_TXACKE : to indicate a missing acknowledge in transmission mode.
|
||||
(+) CEC_IT_TXERR : to indicate an error occurs during transmission mode.
|
||||
The initiator detects low impedance in the CEC line.
|
||||
(+) CEC_IT_TXUDR : to indicate if an underrun error occurs in transmission mode.
|
||||
The transmission is enabled while the software has not yet
|
||||
loaded any value into the TXDR register.
|
||||
(+) CEC_IT_TXEND : to indicate the end of successful transmission.
|
||||
(+) CEC_IT_TXBR : to indicate the next transmission data has to be written to TXDR register.
|
||||
(+) CEC_IT_ARBLST : to indicate arbitration lost in the case of two CEC devices
|
||||
starting at the same time.
|
||||
(+) CEC_IT_RXACKE : to indicate a missing acknowledge in receive mode.
|
||||
(+) CEC_IT_LBPE : to indicate a long bit period error generated during receive mode.
|
||||
(+) CEC_IT_SBPE : to indicate a short bit period error generated during receive mode.
|
||||
(+) CEC_IT_BRE : to indicate a bit rising error generated during receive mode.
|
||||
(+) CEC_IT_RXOVR : to indicate if an overrun error occur while receiving a CEC message.
|
||||
A byte is not yet received while a new byte is stored in the RXDR register.
|
||||
(+) CEC_IT_RXEND : to indicate the end Of reception
|
||||
(+) CEC_IT_RXBR : to indicate a new byte has been received from the CEC line and
|
||||
stored into the RXDR buffer.
|
||||
[..]
|
||||
(@)In this Mode it is advised to use the following functions:
|
||||
void CEC_ITConfig( uint16_t CEC_IT, FunctionalState NewState);
|
||||
ITStatus CEC_GetITStatus(uint16_t CEC_IT);
|
||||
void CEC_ClearITPendingBit(uint16_t CEC_IT);
|
||||
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected CEC interrupts.
|
||||
* @param CEC_IT: specifies the CEC interrupt source to be enabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
|
||||
* @arg CEC_IT_TXERR: Tx Error.
|
||||
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun.
|
||||
* @arg CEC_IT_TXEND: End of Transmission (successful transmission of the last byte).
|
||||
* @arg CEC_IT_TXBR: Tx-Byte Request.
|
||||
* @arg CEC_IT_ARBLST: Arbitration Lost
|
||||
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge
|
||||
* @arg CEC_IT_LBPE: Rx Long period Error
|
||||
* @arg CEC_IT_SBPE: Rx Short period Error
|
||||
* @arg CEC_IT_BRE: Rx Bit Rising Error
|
||||
* @arg CEC_IT_RXOVR: Rx Overrun.
|
||||
* @arg CEC_IT_RXEND: End Of Reception
|
||||
* @arg CEC_IT_RXBR: Rx-Byte Received
|
||||
* @param NewState: new state of the selected CEC interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState)
|
||||
{
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
assert_param(IS_CEC_IT(CEC_IT));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected CEC interrupt */
|
||||
CEC->IER |= CEC_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
CEC_IT =~CEC_IT;
|
||||
/* Disable the selected CEC interrupt */
|
||||
CEC->IER &= CEC_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the CEC flag status.
|
||||
* @param CEC_FLAG: specifies the CEC flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
|
||||
* @arg CEC_FLAG_TXERR: Tx Error.
|
||||
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
|
||||
* @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
|
||||
* @arg CEC_FLAG_TXBR: Tx-Byte Request.
|
||||
* @arg CEC_FLAG_ARBLST: Arbitration Lost
|
||||
* @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
|
||||
* @arg CEC_FLAG_LBPE: Rx Long period Error
|
||||
* @arg CEC_FLAG_SBPE: Rx Short period Error
|
||||
* @arg CEC_FLAG_BRE: Rx Bit Rissing Error
|
||||
* @arg CEC_FLAG_RXOVR: Rx Overrun.
|
||||
* @arg CEC_FLAG_RXEND: End Of Reception.
|
||||
* @arg CEC_FLAG_RXBR: Rx-Byte Received.
|
||||
* @retval The new state of CEC_FLAG (SET or RESET)
|
||||
*/
|
||||
FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
|
||||
|
||||
/* Check the status of the specified CEC flag */
|
||||
if ((CEC->ISR & CEC_FLAG) != (uint16_t)RESET)
|
||||
{
|
||||
/* CEC flag is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* CEC flag is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
/* Return the CEC flag status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the CEC's pending flags.
|
||||
* @param CEC_FLAG: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
|
||||
* @arg CEC_FLAG_TXERR: Tx Error
|
||||
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun
|
||||
* @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
|
||||
* @arg CEC_FLAG_TXBR: Tx-Byte Request
|
||||
* @arg CEC_FLAG_ARBLST: Arbitration Lost
|
||||
* @arg CEC_FLAG_RXACKE: Rx Missing Acknowledge
|
||||
* @arg CEC_FLAG_LBPE: Rx Long period Error
|
||||
* @arg CEC_FLAG_SBPE: Rx Short period Error
|
||||
* @arg CEC_FLAG_BRE: Rx Bit Rising Error
|
||||
* @arg CEC_FLAG_RXOVR: Rx Overrun
|
||||
* @arg CEC_FLAG_RXEND: End Of Reception
|
||||
* @arg CEC_FLAG_RXBR: Rx-Byte Received
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_ClearFlag(uint32_t CEC_FLAG)
|
||||
{
|
||||
assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
|
||||
|
||||
/* Clear the selected CEC flag */
|
||||
CEC->ISR = CEC_FLAG;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified CEC interrupt has occurred or not.
|
||||
* @param CEC_IT: specifies the CEC interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
|
||||
* @arg CEC_IT_TXERR: Tx Error.
|
||||
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun.
|
||||
* @arg CEC_IT_TXEND: End of transmission (successful transmission of the last byte).
|
||||
* @arg CEC_IT_TXBR: Tx-Byte Request.
|
||||
* @arg CEC_IT_ARBLST: Arbitration Lost.
|
||||
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge.
|
||||
* @arg CEC_IT_LBPE: Rx Long period Error.
|
||||
* @arg CEC_IT_SBPE: Rx Short period Error.
|
||||
* @arg CEC_IT_BRE: Rx Bit Rising Error.
|
||||
* @arg CEC_IT_RXOVR: Rx Overrun.
|
||||
* @arg CEC_IT_RXEND: End Of Reception.
|
||||
* @arg CEC_IT_RXBR: Rx-Byte Received
|
||||
* @retval The new state of CEC_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus CEC_GetITStatus(uint16_t CEC_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t enablestatus = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CEC_GET_IT(CEC_IT));
|
||||
|
||||
/* Get the CEC IT enable bit status */
|
||||
enablestatus = (CEC->IER & CEC_IT);
|
||||
|
||||
/* Check the status of the specified CEC interrupt */
|
||||
if (((CEC->ISR & CEC_IT) != (uint32_t)RESET) && enablestatus)
|
||||
{
|
||||
/* CEC interrupt is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* CEC interrupt is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
/* Return the CEC interrupt status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the CEC's interrupt pending bits.
|
||||
* @param CEC_IT: specifies the CEC interrupt pending bit to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
|
||||
* @arg CEC_IT_TXERR: Tx Error
|
||||
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun
|
||||
* @arg CEC_IT_TXEND: End of Transmission
|
||||
* @arg CEC_IT_TXBR: Tx-Byte Request
|
||||
* @arg CEC_IT_ARBLST: Arbitration Lost
|
||||
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge
|
||||
* @arg CEC_IT_LBPE: Rx Long period Error
|
||||
* @arg CEC_IT_SBPE: Rx Short period Error
|
||||
* @arg CEC_IT_BRE: Rx Bit Rising Error
|
||||
* @arg CEC_IT_RXOVR: Rx Overrun
|
||||
* @arg CEC_IT_RXEND: End Of Reception
|
||||
* @arg CEC_IT_RXBR: Rx-Byte Received
|
||||
* @retval None
|
||||
*/
|
||||
void CEC_ClearITPendingBit(uint16_t CEC_IT)
|
||||
{
|
||||
assert_param(IS_CEC_IT(CEC_IT));
|
||||
|
||||
/* Clear the selected CEC interrupt pending bits */
|
||||
CEC->ISR = CEC_IT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,409 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_comp.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the comparators (COMP1 and COMP2) peripheral:
|
||||
* + Comparators configuration
|
||||
* + Window mode control
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
|
||||
The device integrates two analog comparators COMP1 and COMP2:
|
||||
(+) The non inverting input is set to PA1 for COMP1 and to PA3
|
||||
for COMP2.
|
||||
|
||||
(+) The inverting input can be selected among: DAC_OUT1,
|
||||
1/4 VREFINT, 1/2 VERFINT, 3/4 VREFINT, VREFINT,
|
||||
I/O (PA0 for COMP1 and PA2 for COMP2)
|
||||
|
||||
(+) The COMP output is internally is available using COMP_GetOutputLevel()
|
||||
and can be set on GPIO pins: PA0, PA6, PA11 for COMP1
|
||||
and PA2, PA7, PA12 for COMP2
|
||||
|
||||
(+) The COMP output can be redirected to embedded timers (TIM1, TIM2
|
||||
and TIM3)
|
||||
|
||||
(+) The two comparators COMP1 and COMP2 can be combined in window
|
||||
mode and only COMP1 non inverting (PA1) can be used as non-
|
||||
inverting input.
|
||||
|
||||
(+) The two comparators COMP1 and COMP2 have interrupt capability
|
||||
with wake-up from Sleep and Stop modes (through the EXTI controller).
|
||||
COMP1 and COMP2 outputs are internally connected to EXTI Line 21
|
||||
and EXTI Line 22 respectively.
|
||||
|
||||
|
||||
##### How to configure the comparator #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This driver provides functions to configure and program the Comparators
|
||||
of all STM32F0xx devices.
|
||||
|
||||
[..] To use the comparator, perform the following steps:
|
||||
|
||||
(#) Enable the SYSCFG APB clock to get write access to comparator
|
||||
register using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
|
||||
|
||||
(#) Configure the comparator input in analog mode using GPIO_Init()
|
||||
|
||||
(#) Configure the comparator output in alternate function mode
|
||||
using GPIO_Init() and use GPIO_PinAFConfig() function to map the
|
||||
comparator output to the GPIO pin
|
||||
|
||||
(#) Configure the comparator using COMP_Init() function:
|
||||
(++) Select the inverting input
|
||||
(++) Select the output polarity
|
||||
(++) Select the output redirection
|
||||
(++) Select the hysteresis level
|
||||
(++) Select the power mode
|
||||
|
||||
(#) Enable the comparator using COMP_Cmd() function
|
||||
|
||||
(#) If required enable the COMP interrupt by configuring and enabling
|
||||
EXTI line in Interrupt mode and selecting the desired sensitivity
|
||||
level using EXTI_Init() function. After that enable the comparator
|
||||
interrupt vector using NVIC_Init() function.
|
||||
|
||||
@endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_comp.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP
|
||||
* @brief COMP driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* CSR register Mask */
|
||||
#define COMP_CSR_CLEAR_MASK ((uint32_t)0x00003FFE)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup COMP_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes COMP peripheral registers to their default reset values.
|
||||
* @note Deinitialization can't be performed if the COMP configuration is locked.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_DeInit(void)
|
||||
{
|
||||
COMP->CSR = ((uint32_t)0x00000000); /*!< Set COMP_CSR register to reset value */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the COMP peripheral according to the specified parameters
|
||||
* in COMP_InitStruct
|
||||
* @note If the selected comparator is locked, initialization can't be performed.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @note By default, PA1 is selected as COMP1 non inverting input.
|
||||
* To use PA4 as COMP1 non inverting input call COMP_SwitchCmd() after COMP_Init()
|
||||
* @param COMP_Selection: the selected comparator.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg COMP_Selection_COMP1: COMP1 selected
|
||||
* @arg COMP_Selection_COMP2: COMP2 selected
|
||||
* @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains
|
||||
* the configuration information for the specified COMP peripheral.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
|
||||
assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput));
|
||||
assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_Output));
|
||||
assert_param(IS_COMP_OUTPUT_POL(COMP_InitStruct->COMP_OutputPol));
|
||||
assert_param(IS_COMP_HYSTERESIS(COMP_InitStruct->COMP_Hysteresis));
|
||||
assert_param(IS_COMP_MODE(COMP_InitStruct->COMP_Mode));
|
||||
|
||||
/*!< Get the COMP_CSR register value */
|
||||
tmpreg = COMP->CSR;
|
||||
|
||||
/*!< Clear the COMP1SW1, COMPx_IN_SEL, COMPx_OUT_TIM_SEL, COMPx_POL, COMPx_HYST and COMPx_PWR_MODE bits */
|
||||
tmpreg &= (uint32_t) ~(COMP_CSR_CLEAR_MASK<<COMP_Selection);
|
||||
|
||||
/*!< Configure COMP: inverting input, output redirection, hysteresis value and power mode */
|
||||
/*!< Set COMPxINSEL bits according to COMP_InitStruct->COMP_InvertingInput value */
|
||||
/*!< Set COMPxOUTSEL bits according to COMP_InitStruct->COMP_Output value */
|
||||
/*!< Set COMPxPOL bit according to COMP_InitStruct->COMP_OutputPol value */
|
||||
/*!< Set COMPxHYST bits according to COMP_InitStruct->COMP_Hysteresis value */
|
||||
/*!< Set COMPxMODE bits according to COMP_InitStruct->COMP_Mode value */
|
||||
tmpreg |= (uint32_t)((COMP_InitStruct->COMP_InvertingInput | COMP_InitStruct->COMP_Output |
|
||||
COMP_InitStruct->COMP_OutputPol | COMP_InitStruct->COMP_Hysteresis |
|
||||
COMP_InitStruct->COMP_Mode)<<COMP_Selection);
|
||||
|
||||
/*!< Write to COMP_CSR register */
|
||||
COMP->CSR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each COMP_InitStruct member with its default value.
|
||||
* @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct)
|
||||
{
|
||||
COMP_InitStruct->COMP_InvertingInput = COMP_InvertingInput_1_4VREFINT;
|
||||
COMP_InitStruct->COMP_Output = COMP_Output_None;
|
||||
COMP_InitStruct->COMP_OutputPol = COMP_OutputPol_NonInverted;
|
||||
COMP_InitStruct->COMP_Hysteresis = COMP_Hysteresis_No;
|
||||
COMP_InitStruct->COMP_Mode = COMP_Mode_UltraLowPower;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the COMP peripheral.
|
||||
* @note If the selected comparator is locked, enable/disable can't be performed.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param COMP_Selection: the selected comparator.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg COMP_Selection_COMP1: COMP1 selected
|
||||
* @arg COMP_Selection_COMP2: COMP2 selected
|
||||
* @param NewState: new state of the COMP peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @note When enabled, the comparator compares the non inverting input with
|
||||
* the inverting input and the comparison result is available
|
||||
* on comparator output.
|
||||
* @note When disabled, the comparator doesn't perform comparison and the
|
||||
* output level is low.
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected COMP peripheral */
|
||||
COMP->CSR |= (uint32_t) (1<<COMP_Selection);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected COMP peripheral */
|
||||
COMP->CSR &= (uint32_t)(~((uint32_t)1<<COMP_Selection));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Close or Open the SW1 switch.
|
||||
* @note This switch is solely intended to redirect signals onto high
|
||||
* impedance input, such as COMP1 non-inverting input (highly resistive switch)
|
||||
* @param NewState: New state of the analog switch.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @note When enabled, the SW1 is closed; PA1 is connected to PA4
|
||||
* @note When disabled, the SW1 switch is open; PA1 is disconnected from PA4
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_SwitchCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Close SW1 switch */
|
||||
COMP->CSR |= (uint32_t) (COMP_CSR_COMP1SW1);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Open SW1 switch */
|
||||
COMP->CSR &= (uint32_t)(~COMP_CSR_COMP1SW1);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the output level (high or low) of the selected comparator.
|
||||
* @note The output level depends on the selected polarity.
|
||||
* If the polarity is not inverted:
|
||||
* @note -Comparator output is low when the non-inverting input is at a lower
|
||||
* voltage than the inverting input
|
||||
* @note -Comparator output is high when the non-inverting input is at a higher
|
||||
* voltage than the inverting input
|
||||
* @note If the polarity is inverted:
|
||||
* @note -Comparator output is high when the non-inverting input is at a lower
|
||||
* voltage than the inverting input
|
||||
* @note -Comparator output is low when the non-inverting input is at a higher
|
||||
* voltage than the inverting input
|
||||
* @param COMP_Selection: the selected comparator.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg COMP_Selection_COMP1: COMP1 selected
|
||||
* @arg COMP_Selection_COMP2: COMP2 selected
|
||||
* @retval Returns the selected comparator output level: low or high.
|
||||
*
|
||||
*/
|
||||
uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection)
|
||||
{
|
||||
uint32_t compout = 0x0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
|
||||
|
||||
/* Check if selected comparator output is high */
|
||||
if ((COMP->CSR & (COMP_CSR_COMP1OUT<<COMP_Selection)) != 0)
|
||||
{
|
||||
compout = COMP_OutputLevel_High;
|
||||
}
|
||||
else
|
||||
{
|
||||
compout = COMP_OutputLevel_Low;
|
||||
}
|
||||
|
||||
/* Return the comparator output level */
|
||||
return (uint32_t)(compout);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Group2 Window mode control function
|
||||
* @brief Window mode control function
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Window mode control function #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the window mode.
|
||||
* In window mode, COMP1 and COMP2 non inverting inputs are connected
|
||||
* together and only COMP1 non inverting input (PA1) can be used.
|
||||
* param NewState: new state of the window mode.
|
||||
* This parameter can be :
|
||||
* @arg ENABLE: COMP1 and COMP2 non inverting inputs are connected together.
|
||||
* @arg DISABLE: OMP1 and COMP2 non inverting inputs are disconnected.
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_WindowCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the window mode */
|
||||
COMP->CSR |= (uint32_t) COMP_CSR_WNDWEN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the window mode */
|
||||
COMP->CSR &= (uint32_t)(~COMP_CSR_WNDWEN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Group3 COMP configuration locking function
|
||||
* @brief COMP1 and COMP2 configuration locking function
|
||||
* COMP1 and COMP2 configuration can be locked each separately.
|
||||
* Unlocking is performed by system reset.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Configuration Lock function #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Lock the selected comparator (COMP1/COMP2) configuration.
|
||||
* @note Locking the configuration means that all control bits are read-only.
|
||||
* To unlock the comparator configuration, perform a system reset.
|
||||
* @param COMP_Selection: selects the comparator to be locked
|
||||
* This parameter can be a value of the following values:
|
||||
* @arg COMP_Selection_COMP1: COMP1 configuration is locked.
|
||||
* @arg COMP_Selection_COMP2: COMP2 configuration is locked.
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_LockConfig(uint32_t COMP_Selection)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
|
||||
|
||||
/* Set the lock bit corresponding to selected comparator */
|
||||
COMP->CSR |= (uint32_t) (COMP_CSR_COMP1LOCK<<COMP_Selection);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,288 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_crc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of CRC computation unit peripheral:
|
||||
* + Configuration of the CRC computation unit
|
||||
* + CRC computation of one/many 32-bit data
|
||||
* + CRC Independent register (IDR) access
|
||||
*
|
||||
* @verbatim
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
|
||||
(+) Enable CRC AHB clock using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_CRC, ENABLE)
|
||||
function
|
||||
(+) If required, select the reverse operation on input data
|
||||
using CRC_ReverseInputDataSelect()
|
||||
(+) If required, enable the reverse operation on output data
|
||||
using CRC_ReverseOutputDataCmd(Enable)
|
||||
(+) use CRC_CalcCRC() function to compute the CRC of a 32-bit data
|
||||
or use CRC_CalcBlockCRC() function to compute the CRC if a 32-bit
|
||||
data buffer
|
||||
(@) To compute the CRC of a new data use CRC_ResetDR() to reset
|
||||
the CRC computation unit before starting the computation
|
||||
otherwise you can get wrong CRC values.
|
||||
|
||||
@endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_crc.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC
|
||||
* @brief CRC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Group1 Configuration of the CRC computation unit functions
|
||||
* @brief Configuration of the CRC computation unit functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### CRC configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes CRC peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_DeInit(void)
|
||||
{
|
||||
/* Set DR register to reset value */
|
||||
CRC->DR = 0xFFFFFFFF;
|
||||
/* Reset IDR register */
|
||||
CRC->IDR = 0x00;
|
||||
/* Set INIT register to reset value */
|
||||
CRC->INIT = 0xFFFFFFFF;
|
||||
/* Reset the CRC calculation unit */
|
||||
CRC->CR = CRC_CR_RESET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resets the CRC calculation unit and sets INIT register content in DR register.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_ResetDR(void)
|
||||
{
|
||||
/* Reset CRC generator */
|
||||
CRC->CR = CRC_CR_RESET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the reverse operation to be performed on input data.
|
||||
* @param CRC_ReverseInputData: Specifies the reverse operation on input data.
|
||||
* This parameter can be:
|
||||
* @arg CRC_ReverseInputData_No: No reverse operation is performed
|
||||
* @arg CRC_ReverseInputData_8bits: reverse operation performed on 8 bits
|
||||
* @arg CRC_ReverseInputData_16bits: reverse operation performed on 16 bits
|
||||
* @arg CRC_ReverseInputData_32bits: reverse operation performed on 32 bits
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData)
|
||||
{
|
||||
uint32_t tmpcr = 0;
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_CRC_REVERSE_INPUT_DATA(CRC_ReverseInputData));
|
||||
|
||||
/* Get CR register value */
|
||||
tmpcr = CRC->CR;
|
||||
|
||||
/* Reset REV_IN bits */
|
||||
tmpcr &= (uint32_t)~((uint32_t)CRC_CR_REV_IN);
|
||||
/* Set the reverse operation */
|
||||
tmpcr |= (uint32_t)CRC_ReverseInputData;
|
||||
|
||||
/* Write to CR register */
|
||||
CRC->CR = (uint32_t)tmpcr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disable the reverse operation on output data.
|
||||
* The reverse operation on output data is performed on 32-bit.
|
||||
* @param NewState: new state of the reverse operation on output data.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_ReverseOutputDataCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable reverse operation on output data */
|
||||
CRC->CR |= CRC_CR_REV_OUT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable reverse operation on output data */
|
||||
CRC->CR &= (uint32_t)~((uint32_t)CRC_CR_REV_OUT);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the INIT register.
|
||||
* @note After resetting CRC calculation unit, CRC_InitValue is stored in DR register
|
||||
* @param CRC_InitValue: Programmable initial CRC value
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_SetInitRegister(uint32_t CRC_InitValue)
|
||||
{
|
||||
CRC->INIT = CRC_InitValue;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Group2 CRC computation of one/many 32-bit data functions
|
||||
* @brief CRC computation of one/many 32-bit data functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### CRC computation functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Computes the 32-bit CRC of a given data word(32-bit).
|
||||
* @param CRC_Data: data word(32-bit) to compute its CRC
|
||||
* @retval 32-bit CRC
|
||||
*/
|
||||
uint32_t CRC_CalcCRC(uint32_t CRC_Data)
|
||||
{
|
||||
CRC->DR = CRC_Data;
|
||||
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
|
||||
* @param pBuffer: pointer to the buffer containing the data to be computed
|
||||
* @param BufferLength: length of the buffer to be computed
|
||||
* @retval 32-bit CRC
|
||||
*/
|
||||
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t index = 0;
|
||||
|
||||
for(index = 0; index < BufferLength; index++)
|
||||
{
|
||||
CRC->DR = pBuffer[index];
|
||||
}
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the current CRC value.
|
||||
* @param None
|
||||
* @retval 32-bit CRC
|
||||
*/
|
||||
uint32_t CRC_GetCRC(void)
|
||||
{
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Group3 CRC Independent Register (IDR) access functions
|
||||
* @brief CRC Independent Register (IDR) access (write/read) functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### CRC Independent Register (IDR) access functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Stores an 8-bit data in the Independent Data(ID) register.
|
||||
* @param CRC_IDValue: 8-bit value to be stored in the ID register
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_SetIDRegister(uint8_t CRC_IDValue)
|
||||
{
|
||||
CRC->IDR = CRC_IDValue;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the 8-bit data stored in the Independent Data(ID) register
|
||||
* @param None
|
||||
* @retval 8-bit value of the ID register
|
||||
*/
|
||||
uint8_t CRC_GetIDRegister(void)
|
||||
{
|
||||
return (CRC->IDR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,537 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_dac.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Digital-to-Analog Converter (DAC) peripheral:
|
||||
* + DAC channel configuration: trigger, output buffer, data format
|
||||
* + DMA management
|
||||
* + Interrupts and flags management
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
===============================================================================
|
||||
##### DAC Peripheral features #####
|
||||
===============================================================================
|
||||
[..] The device integrates one 12-bit Digital Analog Converters refered as
|
||||
DAC channel1 with DAC_OUT1 (PA4) as output
|
||||
|
||||
[..] Digital to Analog conversion can be non-triggered using DAC_Trigger_None
|
||||
and DAC_OUT1 is available once writing to DHRx register using
|
||||
DAC_SetChannel1Data().
|
||||
|
||||
[..] Digital to Analog conversion can be triggered by:
|
||||
(#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
|
||||
The used pin (GPIOx_Pin9) must be configured in input mode.
|
||||
|
||||
(#) Timers TRGO: TIM2, TIM3, TIM6 and TIM15
|
||||
(DAC_Trigger_T2_TRGO, DAC_Trigger_T3_TRGO...)
|
||||
The timer TRGO event should be selected using TIM_SelectOutputTrigger()
|
||||
|
||||
(#) Software using DAC_Trigger_Software
|
||||
|
||||
[..] The DAC channel 1 integrates an output buffer that can be used to
|
||||
reduce the output impedance, and to drive external loads directly
|
||||
without having to add an external operational amplifier.
|
||||
To enable the output buffer use
|
||||
DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
|
||||
|
||||
[..] Refer to the device datasheet for more details about output impedance
|
||||
value with and without output buffer.
|
||||
|
||||
[..] The DAC data format can be:
|
||||
(#) 8-bit right alignment using DAC_Align_8b_R
|
||||
(#) 12-bit left alignment using DAC_Align_12b_L
|
||||
(#) 12-bit right alignment using DAC_Align_12b_R
|
||||
|
||||
[..] The analog output voltage on each DAC channel pin is determined
|
||||
by the following equation: DAC_OUTx = VREF+ * DOR / 4095
|
||||
with DOR is the Data Output Register
|
||||
VEF+ is the input voltage reference (refer to the device datasheet)
|
||||
e.g. To set DAC_OUT1 to 0.7V, use
|
||||
DAC_SetChannel1Data(DAC_Align_12b_R, 868);
|
||||
Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
|
||||
|
||||
[..] A DMA1 request can be generated when an external trigger (but not
|
||||
a software trigger) occurs if DMA1 requests are enabled using
|
||||
DAC_DMACmd()
|
||||
DMA1 requests are mapped as following:
|
||||
(+) DAC channel1 is mapped on DMA1 channel3 which must be already
|
||||
configured
|
||||
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
(+) Enable DAC APB1 clock to get write access to DAC registers
|
||||
using RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
|
||||
|
||||
(+) Configure DAC_OUT1 (DAC_OUT1: PA4) in analog mode
|
||||
using GPIO_Init() function
|
||||
|
||||
(+) Configure the DAC channel using DAC_Init()
|
||||
|
||||
(+) Enable the DAC channel using DAC_Cmd()
|
||||
|
||||
@endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_dac.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC
|
||||
* @brief DAC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* CR register Mask */
|
||||
#define CR_CLEAR_MASK ((uint32_t)0x0000003E)
|
||||
|
||||
/* DHR registers offsets */
|
||||
#define DHR12R1_OFFSET ((uint32_t)0x00000008)
|
||||
|
||||
/* DOR register offset */
|
||||
#define DOR_OFFSET ((uint32_t)0x0000002C)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group1 DAC channels configuration
|
||||
* @brief DAC channels configuration: trigger, output buffer, data format
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### DAC channels configuration: trigger, output buffer, data format #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the DAC peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DeInit(void)
|
||||
{
|
||||
/* Enable DAC reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
|
||||
/* Release DAC from reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the DAC peripheral according to the specified
|
||||
* parameters in the DAC_InitStruct.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
|
||||
* contains the configuration information for the specified DAC channel.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg1 = 0, tmpreg2 = 0;
|
||||
|
||||
/* Check the DAC parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
|
||||
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
|
||||
|
||||
/*---------------------------- DAC CR Configuration ------------------------*/
|
||||
/* Get the DAC CR value */
|
||||
tmpreg1 = DAC->CR;
|
||||
|
||||
/* Clear BOFFx, TENx, TSELx bits */
|
||||
tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
|
||||
|
||||
/* Configure for the selected DAC channel: buffer output, trigger */
|
||||
/* Set TSELx and TENx bits according to DAC_Trigger value */
|
||||
/* Set BOFFx bit according to DAC_OutputBuffer value */
|
||||
tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_OutputBuffer);
|
||||
|
||||
/* Calculate CR register value depending on DAC_Channel */
|
||||
tmpreg1 |= tmpreg2 << DAC_Channel;
|
||||
|
||||
/* Write to DAC CR */
|
||||
DAC->CR = tmpreg1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each DAC_InitStruct member with its default value.
|
||||
* @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
|
||||
{
|
||||
/*--------------- Reset DAC init structure parameters values -----------------*/
|
||||
/* Initialize the DAC_Trigger member */
|
||||
DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
|
||||
/* Initialize the DAC_OutputBuffer member */
|
||||
DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DAC channel.
|
||||
* @param DAC_Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @param NewState: new state of the DAC channel.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @note When the DAC channel is enabled the trigger source can no more
|
||||
* be modified.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DAC channel */
|
||||
DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DAC channel */
|
||||
DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel software trigger.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @param NewState: new state of the selected DAC channel software trigger.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable software trigger for the selected DAC channel */
|
||||
DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable software trigger for the selected DAC channel */
|
||||
DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for DAC channel1.
|
||||
* @param DAC_Align: Specifies the data alignment for DAC channel1.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @param Data : Data to be loaded in the selected data holding register.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||
assert_param(IS_DAC_DATA(Data));
|
||||
|
||||
tmp = (uint32_t)DAC_BASE;
|
||||
tmp += DHR12R1_OFFSET + DAC_Align;
|
||||
|
||||
/* Set the DAC channel1 selected data holding register */
|
||||
*(__IO uint32_t *) tmp = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the last data output value of the selected DAC channel.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
|
||||
tmp = (uint32_t) DAC_BASE ;
|
||||
tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
|
||||
|
||||
/* Returns the DAC channel data output register value */
|
||||
return (uint16_t) (*(__IO uint32_t*) tmp);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group2 DMA management functions
|
||||
* @brief DMA management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### DMA management functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DAC channel DMA request.
|
||||
* When enabled DMA1 is generated when an external trigger (EXTI Line9,
|
||||
* TIM2, TIM3, TIM6 or TIM15 but not a software trigger) occurs
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @param NewState: new state of the selected DAC channel DMA request.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* The DAC channel1 is mapped on DMA1 channel3 which must be already configured.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DAC channel DMA request */
|
||||
DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DAC channel DMA request */
|
||||
DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group3 Interrupts and flags management functions
|
||||
* @brief Interrupts and flags management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Interrupts and flags management functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DAC interrupts.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
|
||||
* This parameter can be the following values:
|
||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||
* @note The DMA underrun occurs when a second external trigger arrives before
|
||||
* the acknowledgement for the first external trigger is received (first request).
|
||||
* @param NewState: new state of the specified DAC interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
assert_param(IS_DAC_IT(DAC_IT));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DAC interrupts */
|
||||
DAC->CR |= (DAC_IT << DAC_Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DAC interrupts */
|
||||
DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DAC flag is set or not.
|
||||
* @param DAC_Channel: thee selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @param DAC_FLAG: specifies the flag to check.
|
||||
* This parameter can be only of the following value:
|
||||
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
|
||||
* @note The DMA underrun occurs when a second external trigger arrives before
|
||||
* the acknowledgement for the first external trigger is received (first request).
|
||||
* @retval The new state of DAC_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_FLAG(DAC_FLAG));
|
||||
|
||||
/* Check the status of the specified DAC flag */
|
||||
if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
|
||||
{
|
||||
/* DAC_FLAG is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DAC_FLAG is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the DAC_FLAG status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DAC channel's pending flags.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @param DAC_FLAG: specifies the flag to clear.
|
||||
* This parameter can be of the following value:
|
||||
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_FLAG(DAC_FLAG));
|
||||
|
||||
/* Clear the selected DAC flags */
|
||||
DAC->SR = (DAC_FLAG << DAC_Channel);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DAC interrupt has occurred or not.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @param DAC_IT: specifies the DAC interrupt source to check.
|
||||
* This parameter can be the following values:
|
||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||
* @note The DMA underrun occurs when a second external trigger arrives before
|
||||
* the acknowledgement for the first external trigger is received (first request).
|
||||
* @retval The new state of DAC_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t enablestatus = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_IT(DAC_IT));
|
||||
|
||||
/* Get the DAC_IT enable bit status */
|
||||
enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
|
||||
|
||||
/* Check the status of the specified DAC interrupt */
|
||||
if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
|
||||
{
|
||||
/* DAC_IT is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DAC_IT is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the DAC_IT status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DAC channel's interrupt pending bits.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @param DAC_IT: specifies the DAC interrupt pending bit to clear.
|
||||
* This parameter can be the following values:
|
||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_IT(DAC_IT));
|
||||
|
||||
/* Clear the selected DAC interrupt pending bits */
|
||||
DAC->SR = (DAC_IT << DAC_Channel);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,213 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_dbgmcu.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Debug MCU (DBGMCU) peripheral:
|
||||
* + Device and Revision ID management
|
||||
* + Peripherals Configuration
|
||||
* @verbatim
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_dbgmcu.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU
|
||||
* @brief DBGMCU driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DBGMCU_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DBGMCU_Group1 Device and Revision ID management functions
|
||||
* @brief Device and Revision ID management functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Device and Revision ID management functions #####
|
||||
==============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the device revision identifier.
|
||||
* @param None
|
||||
* @retval Device revision identifier
|
||||
*/
|
||||
uint32_t DBGMCU_GetREVID(void)
|
||||
{
|
||||
return(DBGMCU->IDCODE >> 16);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device identifier.
|
||||
* @param None
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t DBGMCU_GetDEVID(void)
|
||||
{
|
||||
return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Group2 Peripherals Configuration functions
|
||||
* @brief Peripherals Configuration
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripherals Configuration functions #####
|
||||
==============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures low power mode behavior when the MCU is in Debug mode.
|
||||
* @param DBGMCU_Periph: specifies the low power mode.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DBGMCU_STOP: Keep debugger connection during STOP mode
|
||||
* @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
|
||||
* @param NewState: new state of the specified low power mode in Debug mode.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
DBGMCU->CR |= DBGMCU_Periph;
|
||||
}
|
||||
else
|
||||
{
|
||||
DBGMCU->CR &= ~DBGMCU_Periph;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.
|
||||
* @param DBGMCU_Periph: specifies the APB1 peripheral.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
|
||||
* @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped
|
||||
* when Core is halted.
|
||||
* @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
|
||||
* @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
|
||||
* @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped
|
||||
* when Core is halted
|
||||
* @param NewState: new state of the specified APB1 peripheral in Debug mode.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
DBGMCU->APB1FZ |= DBGMCU_Periph;
|
||||
}
|
||||
else
|
||||
{
|
||||
DBGMCU->APB1FZ &= ~DBGMCU_Periph;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.
|
||||
* @param DBGMCU_Periph: specifies the APB2 peripheral.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted
|
||||
* @param NewState: new state of the specified APB2 peripheral in Debug mode.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
DBGMCU->APB2FZ |= DBGMCU_Periph;
|
||||
}
|
||||
else
|
||||
{
|
||||
DBGMCU->APB2FZ &= ~DBGMCU_Periph;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,660 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_dma.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Direct Memory Access controller (DMA):
|
||||
* + Initialization and Configuration
|
||||
* + Data Counter
|
||||
* + Interrupts and flags management
|
||||
*
|
||||
* @verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Enable The DMA controller clock using
|
||||
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1.
|
||||
(#) Enable and configure the peripheral to be connected to the DMA channel
|
||||
(except for internal SRAM / FLASH memories: no initialization is necessary).
|
||||
(#) For a given Channel, program the Source and Destination addresses,
|
||||
the transfer Direction, the Buffer Size, the Peripheral and Memory
|
||||
Incrementation mode and Data Size, the Circular or Normal mode,
|
||||
the channel transfer Priority and the Memory-to-Memory transfer
|
||||
mode (if needed) using the DMA_Init() function.
|
||||
(#) Enable the NVIC and the corresponding interrupt(s) using the function
|
||||
DMA_ITConfig() if you need to use DMA interrupts.
|
||||
(#) Enable the DMA channel using the DMA_Cmd() function.
|
||||
(#) Activate the needed channel Request using PPP_DMACmd() function for
|
||||
any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
|
||||
The function allowing this operation is provided in each PPP peripheral
|
||||
driver (ie. SPI_DMACmd for SPI peripheral).
|
||||
(#) Optionally, you can configure the number of data to be transferred
|
||||
when the channel is disabled (ie. after each Transfer Complete event
|
||||
or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
|
||||
And you can get the number of remaining data to be transferred using
|
||||
the function DMA_GetCurrDataCounter() at run time (when the DMA channel is
|
||||
enabled and running).
|
||||
(#) To control DMA events you can use one of the following two methods:
|
||||
(##) Check on DMA channel flags using the function DMA_GetFlagStatus().
|
||||
(##) Use DMA interrupts through the function DMA_ITConfig() at initialization
|
||||
phase and DMA_GetITStatus() function into interrupt routines in
|
||||
communication phase.
|
||||
After checking on a flag you should clear it using DMA_ClearFlag()
|
||||
function. And after checking on an interrupt event you should
|
||||
clear it using DMA_ClearITPendingBit() function.
|
||||
@endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_dma.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA
|
||||
* @brief DMA driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F) /* DMA Channel config registers Masks */
|
||||
|
||||
/* DMA1 Channelx interrupt pending bit masks */
|
||||
#define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
|
||||
#define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
|
||||
#define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
|
||||
#define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
|
||||
#define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
[..] This subsection provides functions allowing to initialize the DMA channel
|
||||
source and destination addresses, incrementation and data sizes, transfer
|
||||
direction, buffer size, circular/normal mode selection, memory-to-memory
|
||||
mode selection and channel priority value.
|
||||
[..] The DMA_Init() function follows the DMA configuration procedures as described
|
||||
in reference manual (RM0091).
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the DMAy Channelx registers to their default reset
|
||||
* values.
|
||||
* @param DMAy_Channelx: where y can be 1 to select the DMA and
|
||||
* x can be 1 to 5 for DMA1 to select the DMA Channel.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
|
||||
/* Disable the selected DMAy Channelx */
|
||||
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
|
||||
|
||||
/* Reset DMAy Channelx control register */
|
||||
DMAy_Channelx->CCR = 0;
|
||||
|
||||
/* Reset DMAy Channelx remaining bytes register */
|
||||
DMAy_Channelx->CNDTR = 0;
|
||||
|
||||
/* Reset DMAy Channelx peripheral address register */
|
||||
DMAy_Channelx->CPAR = 0;
|
||||
|
||||
/* Reset DMAy Channelx memory address register */
|
||||
DMAy_Channelx->CMAR = 0;
|
||||
|
||||
if (DMAy_Channelx == DMA1_Channel1)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel1 */
|
||||
DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel2)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel2 */
|
||||
DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel3)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel3 */
|
||||
DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel4)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel4 */
|
||||
DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (DMAy_Channelx == DMA1_Channel5)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel5 */
|
||||
DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the DMAy Channelx according to the specified parameters
|
||||
* in the DMA_InitStruct.
|
||||
* @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 5
|
||||
* for DMA1 to select the DMA Channel.
|
||||
* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
|
||||
assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
|
||||
assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
|
||||
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
|
||||
assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
|
||||
assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
|
||||
assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
|
||||
assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
|
||||
|
||||
/*--------------------------- DMAy Channelx CCR Configuration ----------------*/
|
||||
/* Get the DMAy_Channelx CCR value */
|
||||
tmpreg = DMAy_Channelx->CCR;
|
||||
|
||||
/* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
|
||||
tmpreg &= CCR_CLEAR_MASK;
|
||||
|
||||
/* Configure DMAy Channelx: data transfer, data size, priority level and mode */
|
||||
/* Set DIR bit according to DMA_DIR value */
|
||||
/* Set CIRC bit according to DMA_Mode value */
|
||||
/* Set PINC bit according to DMA_PeripheralInc value */
|
||||
/* Set MINC bit according to DMA_MemoryInc value */
|
||||
/* Set PSIZE bits according to DMA_PeripheralDataSize value */
|
||||
/* Set MSIZE bits according to DMA_MemoryDataSize value */
|
||||
/* Set PL bits according to DMA_Priority value */
|
||||
/* Set the MEM2MEM bit according to DMA_M2M value */
|
||||
tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
|
||||
DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
|
||||
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
|
||||
DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
|
||||
|
||||
/* Write to DMAy Channelx CCR */
|
||||
DMAy_Channelx->CCR = tmpreg;
|
||||
|
||||
/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
|
||||
/* Write to DMAy Channelx CNDTR */
|
||||
DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
|
||||
|
||||
/*--------------------------- DMAy Channelx CPAR Configuration ---------------*/
|
||||
/* Write to DMAy Channelx CPAR */
|
||||
DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
|
||||
|
||||
/*--------------------------- DMAy Channelx CMAR Configuration ---------------*/
|
||||
/* Write to DMAy Channelx CMAR */
|
||||
DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each DMA_InitStruct member with its default value.
|
||||
* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
|
||||
{
|
||||
/*-------------- Reset DMA init structure parameters values ------------------*/
|
||||
/* Initialize the DMA_PeripheralBaseAddr member */
|
||||
DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
|
||||
/* Initialize the DMA_MemoryBaseAddr member */
|
||||
DMA_InitStruct->DMA_MemoryBaseAddr = 0;
|
||||
/* Initialize the DMA_DIR member */
|
||||
DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
|
||||
/* Initialize the DMA_BufferSize member */
|
||||
DMA_InitStruct->DMA_BufferSize = 0;
|
||||
/* Initialize the DMA_PeripheralInc member */
|
||||
DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
||||
/* Initialize the DMA_MemoryInc member */
|
||||
DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
|
||||
/* Initialize the DMA_PeripheralDataSize member */
|
||||
DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
||||
/* Initialize the DMA_MemoryDataSize member */
|
||||
DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
|
||||
/* Initialize the DMA_Mode member */
|
||||
DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
|
||||
/* Initialize the DMA_Priority member */
|
||||
DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
|
||||
/* Initialize the DMA_M2M member */
|
||||
DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DMAy Channelx.
|
||||
* @param DMAy_Channelx: where y can be 1 to select the DMA and
|
||||
* x can be 1 to 5 for DMA1 to select the DMA Channel.
|
||||
* @param NewState: new state of the DMAy Channelx.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DMAy Channelx */
|
||||
DMAy_Channelx->CCR |= DMA_CCR_EN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DMAy Channelx */
|
||||
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Group2 Data Counter functions
|
||||
* @brief Data Counter functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Data Counter functions #####
|
||||
===============================================================================
|
||||
[..] This subsection provides function allowing to configure and read the buffer
|
||||
size (number of data to be transferred).The DMA data counter can be written
|
||||
only when the DMA channel is disabled (ie. after transfer complete event).
|
||||
[..] The following function can be used to write the Channel data counter value:
|
||||
(+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t
|
||||
DataNumber).
|
||||
-@- It is advised to use this function rather than DMA_Init() in situations
|
||||
where only the Data buffer needs to be reloaded.
|
||||
[..] The DMA data counter can be read to indicate the number of remaining transfers
|
||||
for the relative DMA channel. This counter is decremented at the end of each
|
||||
data transfer and when the transfer is complete:
|
||||
(+) If Normal mode is selected: the counter is set to 0.
|
||||
(+) If Circular mode is selected: the counter is reloaded with the initial
|
||||
value(configured before enabling the DMA channel).
|
||||
[..] The following function can be used to read the Channel data counter value:
|
||||
(+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx).
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Sets the number of data units in the current DMAy Channelx transfer.
|
||||
* @param DMAy_Channelx: where y can be 1 to select the DMA and x can be
|
||||
* 1 to 5 for DMA1 to select the DMA Channel.
|
||||
* @param DataNumber: The number of data units in the current DMAy Channelx
|
||||
* transfer.
|
||||
* @note This function can only be used when the DMAy_Channelx is disabled.
|
||||
* @retval None.
|
||||
*/
|
||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
|
||||
/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
|
||||
/* Write to DMAy Channelx CNDTR */
|
||||
DMAy_Channelx->CNDTR = DataNumber;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the number of remaining data units in the current
|
||||
* DMAy Channelx transfer.
|
||||
* @param DMAy_Channelx: where y can be 1 to select the DMA and
|
||||
* x can be 1 to 5 for DMA1 to select the DMA Channel.
|
||||
* @retval The number of remaining data units in the current DMAy Channelx
|
||||
* transfer.
|
||||
*/
|
||||
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
/* Return the number of remaining data units for DMAy Channelx */
|
||||
return ((uint16_t)(DMAy_Channelx->CNDTR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Group3 Interrupts and flags management functions
|
||||
* @brief Interrupts and flags management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Interrupts and flags management functions #####
|
||||
===============================================================================
|
||||
[..] This subsection provides functions allowing to configure the DMA Interrupts
|
||||
sources and check or clear the flags or pending bits status.
|
||||
The user should identify which mode will be used in his application to manage
|
||||
the DMA controller events: Polling mode or Interrupt mode.
|
||||
*** Polling Mode ***
|
||||
====================
|
||||
[..] Each DMA channel can be managed through 4 event Flags:(y : DMA Controller
|
||||
number x : DMA channel number ).
|
||||
(#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred.
|
||||
(#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred.
|
||||
(#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred.
|
||||
(#) DMAy_FLAG_GLx : to indicate that at least one of the events described
|
||||
above occurred.
|
||||
-@- Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the
|
||||
same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
|
||||
[..]In this Mode it is advised to use the following functions:
|
||||
(+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
|
||||
(+) void DMA_ClearFlag(uint32_t DMA_FLAG);
|
||||
|
||||
*** Interrupt Mode ***
|
||||
======================
|
||||
[..] Each DMA channel can be managed through 4 Interrupts:
|
||||
(+) Interrupt Source
|
||||
(##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete
|
||||
event.
|
||||
(##) DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete
|
||||
event.
|
||||
(##) DMA_IT_TE : specifies the interrupt source for the transfer errors event.
|
||||
(##) DMA_IT_GL : to indicate that at least one of the interrupts described
|
||||
above occurred.
|
||||
-@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of
|
||||
the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).
|
||||
[..]In this Mode it is advised to use the following functions:
|
||||
(+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT,
|
||||
FunctionalState NewState);
|
||||
(+) ITStatus DMA_GetITStatus(uint32_t DMA_IT);
|
||||
(+) void DMA_ClearITPendingBit(uint32_t DMA_IT);
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DMAy Channelx interrupts.
|
||||
* @param DMAy_Channelx: where y can be 1 to select the DMA and
|
||||
* x can be 1 to 5 for DMA1 to select the DMA Channel.
|
||||
* @param DMA_IT: specifies the DMA interrupts sources to be enabled
|
||||
* or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @param NewState: new state of the specified DMA interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
assert_param(IS_DMA_CONFIG_IT(DMA_IT));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DMA interrupts */
|
||||
DMAy_Channelx->CCR |= DMA_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DMA interrupts */
|
||||
DMAy_Channelx->CCR &= ~DMA_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DMAy Channelx flag is set or not.
|
||||
* @param DMA_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
|
||||
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
|
||||
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
|
||||
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
|
||||
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
|
||||
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
|
||||
*
|
||||
* @note
|
||||
* The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags
|
||||
* relative to the same channel is set (Transfer Complete, Half-transfer
|
||||
* Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or
|
||||
* DMAy_FLAG_TEx).
|
||||
*
|
||||
* @retval The new state of DMA_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
|
||||
|
||||
/* Check the status of the specified DMA flag */
|
||||
if ((DMA1->ISR & DMA_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
/* DMA_FLAG is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DMA_FLAG is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
/* Return the DMA_FLAG status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DMAy Channelx's pending flags.
|
||||
* @param DMA_FLAG: specifies the flag to clear.
|
||||
* This parameter can be any combination (for the same DMA) of the following values:
|
||||
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
|
||||
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
|
||||
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
|
||||
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
|
||||
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
|
||||
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
|
||||
*
|
||||
* @note
|
||||
* Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags
|
||||
* relative to the same channel (Transfer Complete, Half-transfer Complete and
|
||||
* Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_ClearFlag(uint32_t DMA_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
|
||||
|
||||
/* Clear the selected DMA flags */
|
||||
DMA1->IFCR = DMA_FLAG;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
|
||||
* @param DMA_IT: specifies the DMA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
|
||||
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
|
||||
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
|
||||
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
|
||||
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
|
||||
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
|
||||
*
|
||||
* @note
|
||||
* The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other
|
||||
* interrupts relative to the same channel is set (Transfer Complete,
|
||||
* Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx,
|
||||
* DMAy_IT_HTx or DMAy_IT_TEx).
|
||||
*
|
||||
* @retval The new state of DMA_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus DMA_GetITStatus(uint32_t DMA_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_GET_IT(DMA_IT));
|
||||
|
||||
/* Check the status of the specified DMA interrupt */
|
||||
if ((DMA1->ISR & DMA_IT) != (uint32_t)RESET)
|
||||
{
|
||||
/* DMA_IT is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DMA_IT is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the DMA_IT status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DMAy Channelx's interrupt pending bits.
|
||||
* @param DMA_IT: specifies the DMA interrupt pending bit to clear.
|
||||
* This parameter can be any combination (for the same DMA) of the following values:
|
||||
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
|
||||
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
|
||||
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
|
||||
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
|
||||
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
|
||||
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
|
||||
*
|
||||
* @note
|
||||
* Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other
|
||||
* interrupts relative to the same channel (Transfer Complete, Half-transfer
|
||||
* Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and
|
||||
* DMAy_IT_TEx).
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_ClearITPendingBit(uint32_t DMA_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_CLEAR_IT(DMA_IT));
|
||||
|
||||
/* Clear the selected DMA interrupt pending bits */
|
||||
DMA1->IFCR = DMA_IT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,319 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_exti.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the EXTI peripheral:
|
||||
* + Initialization and Configuration
|
||||
* + Interrupts and flags management
|
||||
*
|
||||
* @verbatim
|
||||
==============================================================================
|
||||
##### EXTI features #####
|
||||
==============================================================================
|
||||
[..] External interrupt/event lines are mapped as following:
|
||||
(#) All available GPIO pins are connected to the 16 external
|
||||
interrupt/event lines from EXTI0 to EXTI15.
|
||||
(#) EXTI line 16 is connected to the PVD output.
|
||||
(#) EXTI line 17 is connected to the RTC Alarm event.
|
||||
(#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events
|
||||
(#) EXTI line 21 is connected to the Comparator 1 wakeup event
|
||||
(#) EXTI line 22 is connected to the Comparator 2 wakeup event
|
||||
(#) EXTI line 23 is connected to the I2C1 wakeup event
|
||||
(#) EXTI line 25 is connected to the USART1 wakeup event
|
||||
(#) EXTI line 27 is connected to the CEC wakeup event
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..] In order to use an I/O pin as an external interrupt source, follow
|
||||
steps below:
|
||||
(#) Configure the I/O in input mode using GPIO_Init()
|
||||
(#) Select the input source pin for the EXTI line using
|
||||
SYSCFG_EXTILineConfig().
|
||||
(#) Select the mode(interrupt, event) and configure the trigger selection
|
||||
(Rising, falling or both) using EXTI_Init(). For the internal interrupt,
|
||||
the trigger selection is not needed( the active edge is always the rising one).
|
||||
(#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init().
|
||||
(#) Optionally, you can generate a software interrupt using the function EXTI_GenerateSWInterrupt().
|
||||
[..]
|
||||
(@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
|
||||
registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
|
||||
@endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_exti.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI
|
||||
* @brief EXTI driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup EXTI_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
==============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the EXTI peripheral registers to their default reset
|
||||
* values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_DeInit(void)
|
||||
{
|
||||
EXTI->IMR = 0x0F940000;
|
||||
EXTI->EMR = 0x00000000;
|
||||
EXTI->RTSR = 0x00000000;
|
||||
EXTI->FTSR = 0x00000000;
|
||||
EXTI->PR = 0x006BFFFF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the EXTI peripheral according to the specified
|
||||
* parameters in the EXTI_InitStruct.
|
||||
* EXTI_Line specifies the EXTI line (EXTI0....EXTI27).
|
||||
* EXTI_Mode specifies which EXTI line is used as interrupt or an event.
|
||||
* EXTI_Trigger selects the trigger. When the trigger occurs, interrupt
|
||||
* pending bit will be set.
|
||||
* EXTI_LineCmd controls (Enable/Disable) the EXTI line.
|
||||
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure that
|
||||
* contains the configuration information for the EXTI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
|
||||
assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
|
||||
assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
|
||||
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
|
||||
|
||||
tmp = (uint32_t)EXTI_BASE;
|
||||
|
||||
if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
|
||||
{
|
||||
/* Clear EXTI line configuration */
|
||||
EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
|
||||
tmp += EXTI_InitStruct->EXTI_Mode;
|
||||
|
||||
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
|
||||
/* Select the trigger for the selected interrupts */
|
||||
if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
|
||||
{
|
||||
/* Rising Falling edge */
|
||||
EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp = (uint32_t)EXTI_BASE;
|
||||
tmp += EXTI_InitStruct->EXTI_Trigger;
|
||||
|
||||
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp += EXTI_InitStruct->EXTI_Mode;
|
||||
|
||||
/* Disable the selected external lines */
|
||||
*(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each EXTI_InitStruct member with its reset value.
|
||||
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
|
||||
{
|
||||
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
|
||||
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
|
||||
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
|
||||
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Generates a Software interrupt on selected EXTI line.
|
||||
* @param EXTI_Line: specifies the EXTI line on which the software interrupt
|
||||
* will be generated.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..19)
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||
|
||||
EXTI->SWIER |= EXTI_Line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Group2 Interrupts and flags management functions
|
||||
* @brief Interrupts and flags management functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Interrupts and flags management functions #####
|
||||
==============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line flag is set or not.
|
||||
* @param EXTI_Line: specifies the EXTI line flag to check.
|
||||
* This parameter can be:
|
||||
* EXTI_Linex: External interrupt line x where x(0..19).
|
||||
* @retval The new state of EXTI_Line (SET or RESET).
|
||||
*/
|
||||
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
|
||||
|
||||
if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending flags.
|
||||
* @param EXTI_Line: specifies the EXTI lines flags to clear.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..19)
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_ClearFlag(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||
|
||||
EXTI->PR = EXTI_Line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line is asserted or not.
|
||||
* @param EXTI_Line: specifies the EXTI line to check.
|
||||
* This parameter can be:
|
||||
* EXTI_Linex: External interrupt line x where x(0..19).
|
||||
* @retval The new state of EXTI_Line (SET or RESET).
|
||||
*/
|
||||
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t enablestatus = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
|
||||
|
||||
enablestatus = EXTI->IMR & EXTI_Line;
|
||||
if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending bits.
|
||||
* @param EXTI_Line: specifies the EXTI lines to clear.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..19).
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||
|
||||
EXTI->PR = EXTI_Line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,504 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the GPIO peripheral:
|
||||
* + Initialization and Configuration functions
|
||||
* + GPIO Read and Write functions
|
||||
* + GPIO Alternate functions configuration functions
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
*
|
||||
===========================================================================
|
||||
##### How to use this driver #####
|
||||
===========================================================================
|
||||
[..]
|
||||
(#) Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd()
|
||||
(#) Configure the GPIO pin(s) using GPIO_Init()
|
||||
Four possible configuration are available for each pin:
|
||||
(++) Input: Floating, Pull-up, Pull-down.
|
||||
(++) Output: Push-Pull (Pull-up, Pull-down or no Pull)
|
||||
Open Drain (Pull-up, Pull-down or no Pull).
|
||||
In output mode, the speed is configurable: Low, Medium, Fast or High.
|
||||
(++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull)
|
||||
Open Drain (Pull-up, Pull-down or no Pull).
|
||||
(++) Analog: required mode when a pin is to be used as ADC channel,
|
||||
DAC output or comparator input.
|
||||
(#) Peripherals alternate function:
|
||||
(++) For ADC, DAC and comparators, configure the desired pin in analog
|
||||
mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN
|
||||
(++) For other peripherals (TIM, USART...):
|
||||
(+++) Connect the pin to the desired peripherals' Alternate
|
||||
Function (AF) using GPIO_PinAFConfig() function. For PortC,
|
||||
PortD and PortF, no configuration is needed.
|
||||
(+++) Configure the desired pin in alternate function mode using
|
||||
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
|
||||
(+++) Select the type, pull-up/pull-down and output speed via
|
||||
GPIO_PuPd, GPIO_OType and GPIO_Speed members
|
||||
(+++) Call GPIO_Init() function
|
||||
(#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
|
||||
(#) To set/reset the level of a pin configured in output mode use
|
||||
GPIO_SetBits()/GPIO_ResetBits()
|
||||
(#) During and just after reset, the alternate functions are not active and
|
||||
the GPIO pins are configured in input floating mode (except JTAG pins).
|
||||
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as
|
||||
general-purpose (PC14 and PC15, respectively) when the LSE oscillator
|
||||
is off. The LSE has priority over the GPIO function.
|
||||
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose
|
||||
PD0 and PD1, respectively, when the HSE oscillator is off. The HSE has
|
||||
priority over the GPIO function.
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_gpio.h"
|
||||
#include "stm32f0xx_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO
|
||||
* @brief GPIO driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Group1 Initialization and Configuration
|
||||
* @brief Initialization and Configuration
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the GPIOx peripheral registers to their default reset
|
||||
* values.
|
||||
* @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
if(GPIOx == GPIOA)
|
||||
{
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);
|
||||
}
|
||||
else if(GPIOx == GPIOB)
|
||||
{
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);
|
||||
}
|
||||
else if(GPIOx == GPIOC)
|
||||
{
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);
|
||||
}
|
||||
else if(GPIOx == GPIOD)
|
||||
{
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);
|
||||
}
|
||||
else
|
||||
{
|
||||
if(GPIOx == GPIOF)
|
||||
{
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE);
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the GPIOx peripheral according to the specified
|
||||
* parameters in the GPIO_InitStruct.
|
||||
* @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.
|
||||
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
|
||||
* the configuration information for the specified GPIO peripheral.
|
||||
* @note The configured pins can be: GPIO_Pin_0 -> GPIO_Pin_15 for GPIOA, GPIOB and GPIOC,
|
||||
* GPIO_Pin_0 -> GPIO_Pin_2 for GPIOD, GPIO_Pin_0 -> GPIO_Pin_3 for GPIOF.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
|
||||
{
|
||||
uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
|
||||
assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
|
||||
assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
|
||||
|
||||
/*-------------------------- Configure the port pins -----------------------*/
|
||||
/*-- GPIO Mode Configuration --*/
|
||||
for (pinpos = 0x00; pinpos < 0x10; pinpos++)
|
||||
{
|
||||
pos = ((uint32_t)0x01) << pinpos;
|
||||
|
||||
/* Get the port pins position */
|
||||
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
|
||||
|
||||
if (currentpin == pos)
|
||||
{
|
||||
if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
|
||||
{
|
||||
/* Check Speed mode parameters */
|
||||
assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
|
||||
|
||||
/* Speed mode configuration */
|
||||
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
|
||||
GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
|
||||
|
||||
/* Check Output mode parameters */
|
||||
assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
|
||||
|
||||
/* Output mode configuration */
|
||||
GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos));
|
||||
GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
|
||||
}
|
||||
|
||||
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
|
||||
|
||||
GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
|
||||
|
||||
/* Pull-up Pull down resistor configuration */
|
||||
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
|
||||
GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each GPIO_InitStruct member with its default value.
|
||||
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
|
||||
{
|
||||
/* Reset GPIO init structure parameters values */
|
||||
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
|
||||
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
|
||||
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_Level_2;
|
||||
GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
|
||||
GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks GPIO Pins configuration registers.
|
||||
* The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
|
||||
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
|
||||
* @note The configuration of the locked GPIO pins can no longer be modified
|
||||
* until the next reset.
|
||||
* @param GPIOx: where x can be (A or B) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
__IO uint32_t tmp = 0x00010000;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_LIST_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
tmp |= GPIO_Pin;
|
||||
/* Set LCKK bit */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Reset LCKK bit */
|
||||
GPIOx->LCKR = GPIO_Pin;
|
||||
/* Set LCKK bit */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Read LCKK bit */
|
||||
tmp = GPIOx->LCKR;
|
||||
/* Read LCKK bit */
|
||||
tmp = GPIOx->LCKR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Group2 GPIO Read and Write
|
||||
* @brief GPIO Read and Write
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### GPIO Read and Write #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Reads the specified input port pin.
|
||||
* @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to read.
|
||||
* @note This parameter can be GPIO_Pin_x where x can be:(0..15) for GPIOA,
|
||||
* GPIOB or GPIOC,(0..2) for GPIOD and(0..3) for GPIOF.
|
||||
* @retval The input port pin value.
|
||||
*/
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified input port pin.
|
||||
* @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.
|
||||
* @retval The input port pin value.
|
||||
*/
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
return ((uint16_t)GPIOx->IDR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified output data port bit.
|
||||
* @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: Specifies the port bit to read.
|
||||
* @note This parameter can be GPIO_Pin_x where x can be:(0..15) for GPIOA,
|
||||
* GPIOB or GPIOC,(0..2) for GPIOD and(0..3) for GPIOF.
|
||||
* @retval The output port pin value.
|
||||
*/
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified GPIO output data port.
|
||||
* @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.
|
||||
* @retval GPIO output data port value.
|
||||
*/
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
return ((uint16_t)GPIOx->ODR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the selected data port bits.
|
||||
* @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bits to be written.
|
||||
* @note This parameter can be GPIO_Pin_x where x can be:(0..15) for GPIOA,
|
||||
* GPIOB or GPIOC,(0..2) for GPIOD and(0..3) for GPIOF.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
GPIOx->BSRR = GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the selected data port bits.
|
||||
* @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bits to be written.
|
||||
* @note This parameter can be GPIO_Pin_x where x can be: (0..15) for GPIOA,
|
||||
* GPIOB or GPIOC,(0..2) for GPIOD and(0..3) for GPIOF.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
GPIOx->BRR = GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets or clears the selected data port bit.
|
||||
* @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to be written.
|
||||
* @param BitVal: specifies the value to be written to the selected bit.
|
||||
* This parameter can be one of the BitAction enumeration values:
|
||||
* @arg Bit_RESET: to clear the port pin
|
||||
* @arg Bit_SET: to set the port pin
|
||||
* @note The GPIO_Pin parameter can be GPIO_Pin_x where x can be: (0..15) for GPIOA,
|
||||
* GPIOB or GPIOC,(0..2) for GPIOD and(0..3) for GPIOF.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
assert_param(IS_GPIO_BIT_ACTION(BitVal));
|
||||
|
||||
if (BitVal != Bit_RESET)
|
||||
{
|
||||
GPIOx->BSRR = GPIO_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BRR = GPIO_Pin ;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes data to the specified GPIO data port.
|
||||
* @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.
|
||||
* @param PortVal: specifies the value to be written to the port output data
|
||||
* register.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
GPIOx->ODR = PortVal;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions
|
||||
* @brief GPIO Alternate functions configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### GPIO Alternate functions configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Writes data to the specified GPIO data port.
|
||||
* @param GPIOx: where x can be (A or B) to select the GPIO peripheral.
|
||||
* @param GPIO_PinSource: specifies the pin for the Alternate function.
|
||||
* This parameter can be GPIO_PinSourcex where x can be (0..15).
|
||||
* @param GPIO_AF: selects the pin to used as Alternate function.
|
||||
* This parameter can be one of the following value:
|
||||
* @arg GPIO_AF_0:WKUP, EVENTOUT, TIM15, SPI1, TIM17,MCO, SWDAT, SWCLK, TIM14,
|
||||
* BOOT,USART1, CEC, IR_OUT, SPI2
|
||||
* @arg GPIO_AF_1:USART2, CEC, Tim3, USART1, USART2,EVENTOUT, I2C1, I2C2, TIM15
|
||||
* @arg GPIO_AF_2:TIM2, TIM1, EVENTOUT, TIM16, TIM17.
|
||||
* @arg GPIO_AF_3:TS, I2C1, TIM15, EVENTOUT
|
||||
* @arg GPIO_AF_4:TIM14.
|
||||
* @arg GPIO_AF_5:TIM16, TIM17.
|
||||
* @arg GPIO_AF_6:EVENTOUT.
|
||||
* @arg GPIO_AF_7:COMP1 OUT, COMP2 OUT
|
||||
* @note The pin should already been configured in Alternate Function mode(AF)
|
||||
* using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
|
||||
* @note Refer to the Alternate function mapping table in the device datasheet
|
||||
* for the detailed mapping of the system and peripherals'alternate
|
||||
* function I/O pins.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
|
||||
{
|
||||
uint32_t temp = 0x00;
|
||||
uint32_t temp_2 = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_LIST_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
|
||||
assert_param(IS_GPIO_AF(GPIO_AF));
|
||||
|
||||
temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
|
||||
GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
|
||||
temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
|
||||
GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,293 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_iwdg.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Independent watchdog (IWDG) peripheral:
|
||||
* + Prescaler and Counter configuration
|
||||
* + IWDG activation
|
||||
* + Flag management
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
==============================================================================
|
||||
##### IWDG features #####
|
||||
==============================================================================
|
||||
[..] The IWDG can be started by either software or hardware (configurable
|
||||
through option byte).
|
||||
|
||||
[..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and
|
||||
thus stays active even if the main clock fails.
|
||||
Once the IWDG is started, the LSI is forced ON and cannot be disabled
|
||||
(LSI cannot be disabled too), and the counter starts counting down from
|
||||
the reset value of 0xFFF. When it reaches the end of count value (0x000)
|
||||
a system reset is generated.
|
||||
The IWDG counter should be reloaded at regular intervals to prevent
|
||||
an MCU reset.
|
||||
|
||||
[..] The IWDG is implemented in the VDD voltage domain that is still functional
|
||||
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
|
||||
|
||||
[..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
|
||||
reset occurs.
|
||||
|
||||
[..] Min-max timeout value @40KHz (LSI): ~0.1ms / ~28.3s
|
||||
The IWDG timeout may vary due to LSI frequency dispersion. STM32F0xx
|
||||
devices provide the capability to measure the LSI frequency (LSI clock
|
||||
should be seleted as RTC clock which is internally connected to TIM10 CH1
|
||||
input capture). The measured value can be used to have an IWDG timeout with
|
||||
an acceptable accuracy.
|
||||
For more information, please refer to the STM32F0xx Reference manual.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..] This driver allows to use IWDG peripheral with either window option enabled
|
||||
or disabled. To do so follow one of the two procedures below.
|
||||
(#) Window option is enabled:
|
||||
(++) Start the IWDG using IWDG_Enable() function, when the IWDG is used
|
||||
in software mode (no need to enable the LSI, it will be enabled
|
||||
by hardware).
|
||||
(++) Enable write access to IWDG_PR and IWDG_RLR registers using
|
||||
IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
|
||||
(++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
|
||||
(++) Configure the IWDG counter value using IWDG_SetReload() function.
|
||||
This value will be loaded in the IWDG counter each time the counter
|
||||
is reloaded, then the IWDG will start counting down from this value.
|
||||
(++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.
|
||||
(++) Configure the IWDG refresh window using IWDG_SetWindowValue() function.
|
||||
|
||||
(#) Window option is disabled:
|
||||
(++) Enable write access to IWDG_PR and IWDG_RLR registers using
|
||||
IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
|
||||
(++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
|
||||
(++) Configure the IWDG counter value using IWDG_SetReload() function.
|
||||
This value will be loaded in the IWDG counter each time the counter
|
||||
is reloaded, then the IWDG will start counting down from this value.
|
||||
(++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.
|
||||
(++) reload the IWDG counter at regular intervals during normal operation
|
||||
to prevent an MCU reset, using IWDG_ReloadCounter() function.
|
||||
(++) Start the IWDG using IWDG_Enable() function, when the IWDG is used
|
||||
in software mode (no need to enable the LSI, it will be enabled
|
||||
by hardware).
|
||||
|
||||
@endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_iwdg.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG
|
||||
* @brief IWDG driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* ---------------------- IWDG registers bit mask ----------------------------*/
|
||||
/* KR register bit mask */
|
||||
#define KR_KEY_RELOAD ((uint16_t)0xAAAA)
|
||||
#define KR_KEY_ENABLE ((uint16_t)0xCCCC)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup IWDG_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
|
||||
* @brief Prescaler and Counter configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Prescaler and Counter configuration functions #####
|
||||
==============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
|
||||
* @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
|
||||
* @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
|
||||
IWDG->KR = IWDG_WriteAccess;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets IWDG Prescaler value.
|
||||
* @param IWDG_Prescaler: specifies the IWDG Prescaler value.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IWDG_Prescaler_4: IWDG prescaler set to 4
|
||||
* @arg IWDG_Prescaler_8: IWDG prescaler set to 8
|
||||
* @arg IWDG_Prescaler_16: IWDG prescaler set to 16
|
||||
* @arg IWDG_Prescaler_32: IWDG prescaler set to 32
|
||||
* @arg IWDG_Prescaler_64: IWDG prescaler set to 64
|
||||
* @arg IWDG_Prescaler_128: IWDG prescaler set to 128
|
||||
* @arg IWDG_Prescaler_256: IWDG prescaler set to 256
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
|
||||
IWDG->PR = IWDG_Prescaler;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets IWDG Reload value.
|
||||
* @param Reload: specifies the IWDG Reload value.
|
||||
* This parameter must be a number between 0 and 0x0FFF.
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_SetReload(uint16_t Reload)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_RELOAD(Reload));
|
||||
IWDG->RLR = Reload;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reloads IWDG counter with value defined in the reload register
|
||||
* (write access to IWDG_PR and IWDG_RLR registers disabled).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_ReloadCounter(void)
|
||||
{
|
||||
IWDG->KR = KR_KEY_RELOAD;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Sets the IWDG window value.
|
||||
* @param WindowValue: specifies the window value to be compared to the downcounter.
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_SetWindowValue(uint16_t WindowValue)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_WINDOW_VALUE(WindowValue));
|
||||
IWDG->WINR = WindowValue;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Group2 IWDG activation function
|
||||
* @brief IWDG activation function
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### IWDG activation function #####
|
||||
==============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
|
||||
* @param None.
|
||||
* @retval None.
|
||||
*/
|
||||
void IWDG_Enable(void)
|
||||
{
|
||||
IWDG->KR = KR_KEY_ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Group3 Flag management function
|
||||
* @brief Flag management function
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Flag management function #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified IWDG flag is set or not.
|
||||
* @param IWDG_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IWDG_FLAG_PVU: Prescaler Value Update on going
|
||||
* @arg IWDG_FLAG_RVU: Reload Value Update on going
|
||||
* @arg IWDG_FLAG_WVU: Counter Window Value Update on going
|
||||
* @retval The new state of IWDG_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_FLAG(IWDG_FLAG));
|
||||
if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the flag status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,169 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_misc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file provides all the miscellaneous firmware functions (add-on
|
||||
* to CMSIS functions).
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_misc.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC
|
||||
* @brief MISC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup MISC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
*
|
||||
@verbatim
|
||||
*******************************************************************************
|
||||
##### Interrupts configuration functions #####
|
||||
*******************************************************************************
|
||||
[..] This section provide functions allowing to configure the NVIC interrupts
|
||||
(IRQ). The Cortex-M0 exceptions are managed by CMSIS functions.
|
||||
(#) Enable and Configure the priority of the selected IRQ Channels.
|
||||
The priority can be 0..3.
|
||||
|
||||
-@- Lower priority values gives higher priority.
|
||||
-@- Priority Order:
|
||||
(#@) Lowest priority.
|
||||
(#@) Lowest hardware priority (IRQn position).
|
||||
|
||||
@endverbatim
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the NVIC peripheral according to the specified
|
||||
* parameters in the NVIC_InitStruct.
|
||||
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
|
||||
* function should be called before.
|
||||
* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
|
||||
* the configuration information for the specified NVIC peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
|
||||
{
|
||||
uint32_t tmppriority = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
|
||||
assert_param(IS_NVIC_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPriority));
|
||||
|
||||
if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
|
||||
{
|
||||
/* Compute the Corresponding IRQ Priority --------------------------------*/
|
||||
tmppriority = NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02];
|
||||
tmppriority &= (uint32_t)(~(((uint32_t)0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8)));
|
||||
tmppriority |= (uint32_t)((((uint32_t)NVIC_InitStruct->NVIC_IRQChannelPriority << 6) & 0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8));
|
||||
|
||||
NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02] = tmppriority;
|
||||
|
||||
/* Enable the Selected IRQ Channels --------------------------------------*/
|
||||
NVIC->ISER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the Selected IRQ Channels -------------------------------------*/
|
||||
NVIC->ICER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the condition for the system to enter low power mode.
|
||||
* @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
|
||||
* @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
|
||||
* @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
|
||||
* @param NewState: new state of LP condition.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_LP(LowPowerMode));
|
||||
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
SCB->SCR |= LowPowerMode;
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the SysTick clock source.
|
||||
* @param SysTick_CLKSource: specifies the SysTick clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
|
||||
* @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
|
||||
* @retval None
|
||||
*/
|
||||
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
|
||||
|
||||
if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
|
||||
{
|
||||
SysTick->CTRL |= SysTick_CLKSource_HCLK;
|
||||
}
|
||||
else
|
||||
{
|
||||
SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,542 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_pwr.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (PWR) peripheral:
|
||||
* + Backup Domain Access
|
||||
* + PVD configuration
|
||||
* + WakeUp pins configuration
|
||||
* + Low Power modes configuration
|
||||
* + Flags management
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_pwr.h"
|
||||
#include "stm32f0xx_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR
|
||||
* @brief PWR driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
/* ------------------ PWR registers bit mask ------------------------ */
|
||||
|
||||
/* CR register bit mask */
|
||||
#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
|
||||
#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Group1 Backup Domain Access function
|
||||
* @brief Backup Domain Access function
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Backup Domain Access function #####
|
||||
==============================================================================
|
||||
|
||||
[..] After reset, the Backup Domain Registers (RCC BDCR Register, RTC registers
|
||||
and RTC backup registers) are protected against possible stray write accesses.
|
||||
[..] To enable access to Backup domain use the PWR_BackupAccessCmd(ENABLE) function.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the PWR peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_DeInit(void)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables access to the Backup domain registers.
|
||||
* @note If the HSE divided by 32 is used as the RTC clock, the
|
||||
* Backup Domain Access should be kept enabled.
|
||||
* @param NewState: new state of the access to the Backup domain registers.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_BackupAccessCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the Backup Domain Access */
|
||||
PWR->CR |= PWR_CR_DBP;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the Backup Domain Access */
|
||||
PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_DBP);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Group2 PVD configuration functions
|
||||
* @brief PVD configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### PVD configuration functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) The PVD is used to monitor the VDD power supply by comparing it to a threshold
|
||||
selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
|
||||
(+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the
|
||||
PVD threshold. This event is internally connected to the EXTI line16
|
||||
and can generate an interrupt if enabled through the EXTI registers.
|
||||
(+) The PVD is stopped in Standby mode.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
|
||||
* @param PWR_PVDLevel: specifies the PVD detection level
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_PVDLevel_0: PVD detection level set to 1.9V
|
||||
* @arg PWR_PVDLevel_1: PVD detection level set to 2.1V
|
||||
* @arg PWR_PVDLevel_2: PVD detection level set to 2.3V
|
||||
* @arg PWR_PVDLevel_3: PVD detection level set to 2.5V
|
||||
* @arg PWR_PVDLevel_4: PVD detection level set to 2.7V
|
||||
* @arg PWR_PVDLevel_5: PVD detection level set to 2.9V
|
||||
* @arg PWR_PVDLevel_6: PVD detection level set to 3.1V
|
||||
* @arg PWR_PVDLevel_7: PVD detection level set to 3.3V
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
|
||||
|
||||
tmpreg = PWR->CR;
|
||||
|
||||
/* Clear PLS[7:5] bits */
|
||||
tmpreg &= CR_PLS_MASK;
|
||||
|
||||
/* Set PLS[7:5] bits according to PWR_PVDLevel value */
|
||||
tmpreg |= PWR_PVDLevel;
|
||||
|
||||
/* Store the new value */
|
||||
PWR->CR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Power Voltage Detector(PVD).
|
||||
* @param NewState: new state of the PVD.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_PVDCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the PVD */
|
||||
PWR->CR |= PWR_CR_PVDE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the PVD */
|
||||
PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_PVDE);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Group3 WakeUp pins configuration functions
|
||||
* @brief WakeUp pins configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### WakeUp pin configuration functions #####
|
||||
==============================================================================
|
||||
|
||||
(+) WakeUp pins are used to wakeup the system from Standby mode. These pins are
|
||||
forced in input pull down configuration and are active on rising edges.
|
||||
(+) There are three WakeUp pins: WakeUp Pin 1 on PA.00 and WakeUp Pin 2 on PC.13.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the WakeUp Pin functionality.
|
||||
* @param PWR_WakeUpPin: specifies the WakeUpPin.
|
||||
* This parameter can be: PWR_WakeUpPin_1 or PWR_WakeUpPin_2.
|
||||
* @param NewState: new state of the WakeUp Pin functionality.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the EWUPx pin */
|
||||
PWR->CSR |= PWR_WakeUpPin;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the EWUPx pin */
|
||||
PWR->CSR &= ~PWR_WakeUpPin;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PWR_Group4 Low Power modes configuration functions
|
||||
* @brief Low Power modes configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Low Power modes configuration functions #####
|
||||
==============================================================================
|
||||
|
||||
[..] The devices feature three low-power modes:
|
||||
(+) Sleep mode: Cortex-M0 core stopped, peripherals kept running.
|
||||
(+) Stop mode: all clocks are stopped, regulator running, regulator in low power mode
|
||||
(+) Standby mode: VCORE domain powered off
|
||||
|
||||
*** Sleep mode ***
|
||||
==================
|
||||
[..]
|
||||
(+) Entry:
|
||||
(++) The Sleep mode is entered by executing the WFE() or WFI() instructions.
|
||||
(+) Exit:
|
||||
(++) Any peripheral interrupt acknowledged by the nested vectored interrupt
|
||||
controller (NVIC) can wake up the device from Sleep mode.
|
||||
|
||||
*** Stop mode ***
|
||||
=================
|
||||
[..] In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the HSI,
|
||||
the HSI14 and the HSE RC oscillators are disabled. Internal SRAM and register
|
||||
contents are preserved.
|
||||
The voltage regulator can be configured either in normal or low-power mode.
|
||||
|
||||
(+) Entry:
|
||||
(++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,)
|
||||
function with regulator in LowPower or with Regulator ON.
|
||||
(+) Exit:
|
||||
(++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode
|
||||
or any internal IPs (I2C, UASRT or CEC) wakeup event.
|
||||
|
||||
*** Standby mode ***
|
||||
====================
|
||||
[..] The Standby mode allows to achieve the lowest power consumption. It is based
|
||||
on the Cortex-M0 deepsleep mode, with the voltage regulator disabled.
|
||||
The VCORE domain is consequently powered off. The PLL, the HSI, the HSI14
|
||||
oscillator and the HSE oscillator are also switched off. SRAM and register
|
||||
contents are lost except for the Backup domain (RTC registers, RTC backup
|
||||
registers and Standby circuitry).
|
||||
|
||||
[..] The voltage regulator is OFF.
|
||||
|
||||
(+) Entry:
|
||||
(++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
|
||||
(+) Exit:
|
||||
(++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
|
||||
tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
|
||||
|
||||
*** Auto-wakeup (AWU) from low-power mode ***
|
||||
=============================================
|
||||
[..] The MCU can be woken up from low-power mode by an RTC Alarm event, a tamper
|
||||
event, a time-stamp event, or a comparator event, without depending on an
|
||||
external interrupt (Auto-wakeup mode).
|
||||
|
||||
(+) RTC auto-wakeup (AWU) from the Stop mode
|
||||
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
|
||||
(+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
|
||||
or Event modes) using the EXTI_Init() function.
|
||||
(+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
|
||||
(+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
|
||||
and RTC_AlarmCmd() functions.
|
||||
(++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
|
||||
is necessary to:
|
||||
(+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt
|
||||
or Event modes) using the EXTI_Init() function.
|
||||
(+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
|
||||
function.
|
||||
(+++) Configure the RTC to detect the tamper or time stamp event using the
|
||||
RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
|
||||
functions.
|
||||
|
||||
(+) RTC auto-wakeup (AWU) from the Standby mode
|
||||
(++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
|
||||
(+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function.
|
||||
(+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
|
||||
and RTC_AlarmCmd() functions.
|
||||
(++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
|
||||
is necessary to:
|
||||
(+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
|
||||
function.
|
||||
(+++) Configure the RTC to detect the tamper or time stamp event using the
|
||||
RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
|
||||
functions.
|
||||
|
||||
(+) Comparator auto-wakeup (AWU) from the Stop mode
|
||||
(++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup
|
||||
event, it is necessary to:
|
||||
(+++) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2
|
||||
to be sensitive to to the selected edges (falling, rising or falling
|
||||
and rising) (Interrupt or Event modes) using the EXTI_Init() function.
|
||||
(+++) Configure the comparator to generate the event.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enters Sleep mode.
|
||||
* @note In Sleep mode, all I/O pins keep the same state as in Run mode.
|
||||
* @param PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
|
||||
* @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
|
||||
|
||||
/* Clear SLEEPDEEP bit of Cortex-M0 System Control Register */
|
||||
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||||
|
||||
/* Select SLEEP mode entry -------------------------------------------------*/
|
||||
if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__WFE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters STOP mode.
|
||||
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
|
||||
* @note When exiting Stop mode by issuing an interrupt or a wakeup event,
|
||||
* the HSI RC oscillator is selected as system clock.
|
||||
* @note When the voltage regulator operates in low power mode, an additional
|
||||
* startup delay is incurred when waking up from Stop mode.
|
||||
* By keeping the internal regulator ON during Stop mode, the consumption
|
||||
* is higher although the startup time is reduced.
|
||||
* @param PWR_Regulator: specifies the regulator state in STOP mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_Regulator_ON: STOP mode with regulator ON
|
||||
* @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
|
||||
* @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
|
||||
* @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(PWR_Regulator));
|
||||
assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
|
||||
|
||||
/* Select the regulator state in STOP mode ---------------------------------*/
|
||||
tmpreg = PWR->CR;
|
||||
/* Clear PDDS and LPDSR bits */
|
||||
tmpreg &= CR_DS_MASK;
|
||||
|
||||
/* Set LPDSR bit according to PWR_Regulator value */
|
||||
tmpreg |= PWR_Regulator;
|
||||
|
||||
/* Store the new value */
|
||||
PWR->CR = tmpreg;
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex-M0 System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* Select STOP mode entry --------------------------------------------------*/
|
||||
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__WFE();
|
||||
}
|
||||
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters STANDBY mode.
|
||||
* @note In Standby mode, all I/O pins are high impedance except for:
|
||||
* Reset pad (still available)
|
||||
* RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper,
|
||||
* time-stamp, RTC Alarm out, or RTC clock calibration out.
|
||||
* WKUP pin 1 (PA0) if enabled.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_EnterSTANDBYMode(void)
|
||||
{
|
||||
/* Clear Wakeup flag */
|
||||
PWR->CR |= PWR_CR_CWUF;
|
||||
|
||||
/* Select STANDBY mode */
|
||||
PWR->CR |= PWR_CR_PDDS;
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex-M0 System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Group5 Flags management functions
|
||||
* @brief Flags management functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Flags management functions #####
|
||||
==============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified PWR flag is set or not.
|
||||
* @param PWR_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup
|
||||
* event was received from the WKUP pin or from the RTC alarm
|
||||
* (Alarm A or Alarm B), RTC Tamper event or RTC TimeStamp event.
|
||||
* @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the
|
||||
* system was resumed from StandBy mode.
|
||||
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD
|
||||
* is enabled by the PWR_PVDCmd() function.
|
||||
* @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag.
|
||||
* This flag indicates the state of the internal voltage
|
||||
* reference, VREFINT.
|
||||
* @retval The new state of PWR_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
|
||||
|
||||
if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the flag status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the PWR's pending flags.
|
||||
* @param PWR_FLAG: specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_WU: Wake Up flag
|
||||
* @arg PWR_FLAG_SB: StandBy flag
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_ClearFlag(uint32_t PWR_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
|
||||
|
||||
PWR->CR |= PWR_FLAG << 2;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,304 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_syscfg.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the SYSCFG peripheral:
|
||||
* + Remapping the memory mapped at 0x00000000
|
||||
* + Remapping the DMA channels
|
||||
* + Enabling I2C fast mode plus driving capability for I2C pins
|
||||
* + Configuring the EXTI lines connection to the GPIO port
|
||||
* + Configuring the CFGR2 features (Connecting some internal signal
|
||||
* to the break input of TIM1)
|
||||
*
|
||||
* @verbatim
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
The SYSCFG registers can be accessed only when the SYSCFG
|
||||
interface APB clock is enabled.
|
||||
To enable SYSCFG APB clock use:
|
||||
RCC_APBPeriphClockCmd(RCC_APBPeriph_SYSCFG, ENABLE).
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_syscfg.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG
|
||||
* @brief SYSCFG driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SYSCFG_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions
|
||||
* @brief SYSCFG Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### SYSCFG Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the SYSCFG registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
* @note MEM_MODE bits are not affected by APB reset.
|
||||
* MEM_MODE bits took the value from the user option bytes.
|
||||
* @note CFGR2 register is not affected by APB reset.
|
||||
* CLABBB configuration bits are locked when set.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
*/
|
||||
void SYSCFG_DeInit(void)
|
||||
{
|
||||
/* Set SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */
|
||||
SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE;
|
||||
/* Set EXTICRx registers to reset value */
|
||||
SYSCFG->EXTICR[0] = 0;
|
||||
SYSCFG->EXTICR[1] = 0;
|
||||
SYSCFG->EXTICR[2] = 0;
|
||||
SYSCFG->EXTICR[3] = 0;
|
||||
/* Set CFGR2 register to reset value: clear SRAM parity error flag */
|
||||
SYSCFG->CFGR2 |= (uint32_t) SYSCFG_CFGR2_SRAM_PE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the memory mapping at address 0x00000000.
|
||||
* @param SYSCFG_MemoryRemap: selects the memory remapping.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
|
||||
* @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000
|
||||
* @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)
|
||||
{
|
||||
uint32_t tmpctrl = 0;
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap));
|
||||
|
||||
/* Get CFGR1 register value */
|
||||
tmpctrl = SYSCFG->CFGR1;
|
||||
|
||||
/* Clear MEM_MODE bits */
|
||||
tmpctrl &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE);
|
||||
|
||||
/* Set the new MEM_MODE bits value */
|
||||
tmpctrl |= (uint32_t) SYSCFG_MemoryRemap;
|
||||
|
||||
/* Set CFGR1 register with the new memory remap configuration */
|
||||
SYSCFG->CFGR1 = tmpctrl;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the DMA channels remapping.
|
||||
* @param SYSCFG_DMARemap: selects the DMA channels remap.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from channel1 to channel2
|
||||
* @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from channel3 to channel4
|
||||
* @arg SYSCFG_DMARemap_USART1Rx: Remap USART1 Rx DMA requests from channel3 to channel5
|
||||
* @arg SYSCFG_DMARemap_USART1Tx: Remap USART1 Tx DMA requests from channel2 to channel4
|
||||
* @arg SYSCFG_DMARemap_ADC1: Remap ADC1 DMA requests from channel1 to channel2
|
||||
* @param NewState: new state of the DMA channel remapping.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @note When enabled, DMA channel of the selected peripheral is remapped
|
||||
* @note When disabled, Default DMA channel is mapped to the selected peripheral
|
||||
* @note
|
||||
* By default TIM17 DMA requests is mapped to channel 1
|
||||
* use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable)
|
||||
* to remap TIM17 DMA requests to channel 2
|
||||
* use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable)
|
||||
* to map TIM17 DMA requests to channel 1 (default mapping)
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Remap the DMA channel */
|
||||
SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* use the default DMA channel mapping */
|
||||
SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the I2C fast mode plus driving capability.
|
||||
* @param SYSCFG_I2CFastModePlus: selects the pin.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6
|
||||
* @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7
|
||||
* @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8
|
||||
* @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9
|
||||
* @param NewState: new state of the DMA channel remapping.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @note ENABLE: Enable fast mode plus driving capability for selected pin
|
||||
* @note DISABLE: Disable fast mode plus driving capability for selected pin
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable fast mode plus driving capability for selected pin */
|
||||
SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable fast mode plus driving capability for selected pin */
|
||||
SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the GPIO pin used as EXTI Line.
|
||||
* @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source
|
||||
* for EXTI lines where x can be (A, B, C, D or F).
|
||||
* @param EXTI_PinSourcex: specifies the EXTI line to be configured.
|
||||
* This parameter can be EXTI_PinSourcex where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
|
||||
{
|
||||
uint32_t tmp = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
|
||||
assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
|
||||
|
||||
tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
|
||||
SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
|
||||
SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Connect the selected parameter to the break input of TIM1.
|
||||
* @note The selected configuration is locked and can be unlocked by system reset
|
||||
* @param SYSCFG_Break: selects the configuration to be connected to break
|
||||
* input of TIM1
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg SYSCFG_Break_PVD: Connects the PVD event to the Break Input of TIM1.
|
||||
* @arg SYSCFG_Break_SRAMParity: Connects the SRAM_PARITY error signal to the Break Input of TIM1 .
|
||||
* @arg SYSCFG_Break_Lockup: Connects Lockup output of CortexM0 to the break input of TIM1.
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_BreakConfig(uint32_t SYSCFG_Break)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break));
|
||||
|
||||
SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified SYSCFG flag is set or not.
|
||||
* @param SYSCFG_Flag: specifies the SYSCFG flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSCFG_FLAG_PE: SRAM parity error flag.
|
||||
* @retval The new state of SYSCFG_Flag (SET or RESET).
|
||||
*/
|
||||
FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
|
||||
|
||||
/* Check the status of the specified SPI flag */
|
||||
if ((SYSCFG->CFGR2 & SYSCFG_CFGR2_SRAM_PE) != (uint32_t)RESET)
|
||||
{
|
||||
/* SYSCFG_Flag is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* SYSCFG_Flag is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the SYSCFG_Flag status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the selected SYSCFG flag.
|
||||
* @param SYSCFG_Flag: selects the flag to be cleared.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg SYSCFG_FLAG_PE: SRAM parity error flag.
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
|
||||
|
||||
SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Flag;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,303 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx_wwdg.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Window watchdog (WWDG) peripheral:
|
||||
* + Prescaler, Refresh window and Counter configuration
|
||||
* + WWDG activation
|
||||
* + Interrupts and flags management
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
==============================================================================
|
||||
##### WWDG features #####
|
||||
==============================================================================
|
||||
[..] Once enabled the WWDG generates a system reset on expiry of a programmed
|
||||
time period, unless the program refreshes the counter (downcounter)
|
||||
before to reach 0x3F value (i.e. a reset is generated when the counter
|
||||
value rolls over from 0x40 to 0x3F).
|
||||
[..] An MCU reset is also generated if the counter value is refreshed
|
||||
before the counter has reached the refresh window value. This
|
||||
implies that the counter must be refreshed in a limited window.
|
||||
|
||||
[..] Once enabled the WWDG cannot be disabled except by a system reset.
|
||||
|
||||
[..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
|
||||
reset occurs.
|
||||
|
||||
[..] The WWDG counter input clock is derived from the APB clock divided
|
||||
by a programmable prescaler.
|
||||
|
||||
[..] WWDG counter clock = PCLK1 / Prescaler.
|
||||
[..] WWDG timeout = (WWDG counter clock) * (counter value).
|
||||
|
||||
[..] Min-max timeout value @32MHz (PCLK1): ~85us / ~43ms.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE)
|
||||
function.
|
||||
|
||||
(#) Configure the WWDG prescaler using WWDG_SetPrescaler() function.
|
||||
|
||||
(#) Configure the WWDG refresh window using WWDG_SetWindowValue() function.
|
||||
|
||||
(#) Set the WWDG counter value and start it using WWDG_Enable() function.
|
||||
When the WWDG is enabled the counter value should be configured to
|
||||
a value greater than 0x40 to prevent generating an immediate reset.
|
||||
|
||||
(#) Optionally you can enable the Early wakeup interrupt which is
|
||||
generated when the counter reach 0x40.
|
||||
Once enabled this interrupt cannot be disabled except by a system reset.
|
||||
|
||||
(#) Then the application program must refresh the WWDG counter at regular
|
||||
intervals during normal operation to prevent an MCU reset, using
|
||||
WWDG_SetCounter() function. This operation must occur only when
|
||||
the counter value is lower than the refresh window value,
|
||||
programmed using WWDG_SetWindowValue().
|
||||
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx_wwdg.h"
|
||||
#include "stm32f0xx_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F0xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG
|
||||
* @brief WWDG driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* --------------------- WWDG registers bit mask ---------------------------- */
|
||||
/* CFR register bit mask */
|
||||
#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)
|
||||
#define CFR_W_MASK ((uint32_t)0xFFFFFF80)
|
||||
#define BIT_MASK ((uint8_t)0x7F)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WWDG_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions
|
||||
* @brief Prescaler, Refresh window and Counter configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Prescaler, Refresh window and Counter configuration functions #####
|
||||
==============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the WWDG peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_DeInit(void)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the WWDG Prescaler.
|
||||
* @param WWDG_Prescaler: specifies the WWDG Prescaler.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
|
||||
* @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
|
||||
* @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
|
||||
* @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
|
||||
/* Clear WDGTB[1:0] bits */
|
||||
tmpreg = WWDG->CFR & CFR_WDGTB_MASK;
|
||||
/* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
|
||||
tmpreg |= WWDG_Prescaler;
|
||||
/* Store the new value */
|
||||
WWDG->CFR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the WWDG window value.
|
||||
* @param WindowValue: specifies the window value to be compared to the downcounter.
|
||||
* This parameter value must be lower than 0x80.
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_SetWindowValue(uint8_t WindowValue)
|
||||
{
|
||||
__IO uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
|
||||
/* Clear W[6:0] bits */
|
||||
|
||||
tmpreg = WWDG->CFR & CFR_W_MASK;
|
||||
|
||||
/* Set W[6:0] bits according to WindowValue value */
|
||||
tmpreg |= WindowValue & (uint32_t) BIT_MASK;
|
||||
|
||||
/* Store the new value */
|
||||
WWDG->CFR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the WWDG Early Wakeup interrupt(EWI).
|
||||
* @note Once enabled this interrupt cannot be disabled except by a system reset.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_EnableIT(void)
|
||||
{
|
||||
WWDG->CFR |= WWDG_CFR_EWI;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the WWDG counter value.
|
||||
* @param Counter: specifies the watchdog counter value.
|
||||
* This parameter must be a number between 0x40 and 0x7F (to prevent generating
|
||||
* an immediate reset).
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_SetCounter(uint8_t Counter)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_COUNTER(Counter));
|
||||
/* Write to T[6:0] bits to configure the counter value, no need to do
|
||||
a read-modify-write; writing a 0 to WDGA bit does nothing */
|
||||
WWDG->CR = Counter & BIT_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Group2 WWDG activation functions
|
||||
* @brief WWDG activation functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### WWDG activation function #####
|
||||
==============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables WWDG and load the counter value.
|
||||
* @param Counter: specifies the watchdog counter value.
|
||||
* This parameter must be a number between 0x40 and 0x7F (to prevent generating
|
||||
* an immediate reset).
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_Enable(uint8_t Counter)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_COUNTER(Counter));
|
||||
WWDG->CR = WWDG_CR_WDGA | Counter;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Group3 Interrupts and flags management functions
|
||||
* @brief Interrupts and flags management functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Interrupts and flags management functions #####
|
||||
==============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Checks whether the Early Wakeup interrupt flag is set or not.
|
||||
* @param None
|
||||
* @retval The new state of the Early Wakeup interrupt flag (SET or RESET).
|
||||
*/
|
||||
FlagStatus WWDG_GetFlagStatus(void)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
if ((WWDG->SR) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears Early Wakeup interrupt flag.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_ClearFlag(void)
|
||||
{
|
||||
WWDG->SR = (uint32_t)RESET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,256 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f0_discovery.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief This file provides set of firmware functions to manage Leds and
|
||||
* push-button available on STM32F0-DISCOVERY Kit from STMicroelectronics.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0_discovery.h"
|
||||
|
||||
/** @addtogroup Utilities
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F0_DISCOVERY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F0_DISCOVERY_LOW_LEVEL
|
||||
* @brief This file provides firmware functions to manage Leds and push-buttons,
|
||||
* available on STM32F0_DISCOVERY evaluation board from STMicroelectronics.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F0_DISCOVERY_LOW_LEVEL_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup STM32F0_DISCOVERY_LOW_LEVEL_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup STM32F0_DISCOVERY_LOW_LEVEL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup STM32F0_DISCOVERY_LOW_LEVEL_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
GPIO_TypeDef* GPIO_PORT[LEDn] = {LED3_GPIO_PORT, LED4_GPIO_PORT};
|
||||
const uint16_t GPIO_PIN[LEDn] = {LED3_PIN, LED4_PIN};
|
||||
const uint32_t GPIO_CLK[LEDn] = {LED3_GPIO_CLK, LED4_GPIO_CLK};
|
||||
|
||||
GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {USER_BUTTON_GPIO_PORT};
|
||||
|
||||
const uint16_t BUTTON_PIN[BUTTONn] = {USER_BUTTON_PIN};
|
||||
|
||||
const uint32_t BUTTON_CLK[BUTTONn] = {USER_BUTTON_GPIO_CLK};
|
||||
|
||||
const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {USER_BUTTON_EXTI_LINE};
|
||||
|
||||
const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {USER_BUTTON_EXTI_PORT_SOURCE};
|
||||
|
||||
const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {USER_BUTTON_EXTI_PIN_SOURCE};
|
||||
|
||||
const uint16_t BUTTON_IRQn[BUTTONn] = {USER_BUTTON_EXTI_IRQn};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup STM32F0_DISCOVERY_LOW_LEVEL_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F0_DISCOVERY_LOW_LEVEL_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures LED GPIO.
|
||||
* @param Led: Specifies the Led to be configured.
|
||||
* This parameter can be one of following parameters:
|
||||
* @arg LED3
|
||||
* @arg LED4
|
||||
* @retval None
|
||||
*/
|
||||
void STM_EVAL_LEDInit(Led_TypeDef Led)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
|
||||
/* Enable the GPIO_LED Clock */
|
||||
RCC_AHBPeriphClockCmd(GPIO_CLK[Led], ENABLE);
|
||||
|
||||
/* Configure the GPIO_LED pin */
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
|
||||
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
||||
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Turns selected LED On.
|
||||
* @param Led: Specifies the Led to be set on.
|
||||
* This parameter can be one of following parameters:
|
||||
* @arg LED3
|
||||
* @arg LED4
|
||||
* @retval None
|
||||
*/
|
||||
void STM_EVAL_LEDOn(Led_TypeDef Led)
|
||||
{
|
||||
GPIO_PORT[Led]->BSRR = GPIO_PIN[Led];
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Turns selected LED Off.
|
||||
* @param Led: Specifies the Led to be set off.
|
||||
* This parameter can be one of following parameters:
|
||||
* @arg LED3
|
||||
* @arg LED4
|
||||
* @retval None
|
||||
*/
|
||||
void STM_EVAL_LEDOff(Led_TypeDef Led)
|
||||
{
|
||||
GPIO_PORT[Led]->BRR = GPIO_PIN[Led];
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggles the selected LED.
|
||||
* @param Led: Specifies the Led to be toggled.
|
||||
* This parameter can be one of following parameters:
|
||||
* @arg LED3
|
||||
* @arg LED4
|
||||
* @retval None
|
||||
*/
|
||||
void STM_EVAL_LEDToggle(Led_TypeDef Led)
|
||||
{
|
||||
GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures Button GPIO and EXTI Line.
|
||||
* @param Button: Specifies the Button to be configured.
|
||||
* This parameter can be:
|
||||
* @arg BUTTON_USER: User Push Button
|
||||
* @param Button_Mode: Specifies Button mode.
|
||||
* This parameter can be one of following parameters:
|
||||
* @arg BUTTON_MODE_GPIO: Button will be used as simple IO
|
||||
* @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt
|
||||
* generation capability
|
||||
* @retval None
|
||||
*/
|
||||
void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
EXTI_InitTypeDef EXTI_InitStructure;
|
||||
NVIC_InitTypeDef NVIC_InitStructure;
|
||||
|
||||
/* Enable the BUTTON Clock */
|
||||
RCC_AHBPeriphClockCmd(BUTTON_CLK[Button], ENABLE);
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
|
||||
|
||||
/* Configure Button pin as input */
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
|
||||
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
|
||||
GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];
|
||||
GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);
|
||||
|
||||
if (Button_Mode == BUTTON_MODE_EXTI)
|
||||
{
|
||||
/* Connect Button EXTI Line to Button GPIO Pin */
|
||||
SYSCFG_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);
|
||||
|
||||
/* Configure Button EXTI line */
|
||||
EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];
|
||||
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
|
||||
if (Button != BUTTON_USER)
|
||||
{
|
||||
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
|
||||
}
|
||||
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
|
||||
EXTI_Init(&EXTI_InitStructure);
|
||||
|
||||
/* Enable and set Button EXTI Interrupt to the lowest priority */
|
||||
NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];
|
||||
NVIC_InitStructure.NVIC_IRQChannelPriority = 0x03;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the selected Button state.
|
||||
* @param Button: Specifies the Button to be checked.
|
||||
* This parameter can be one of following parameters:
|
||||
* @arg BUTTON_USER: User Push Button
|
||||
* @retval The Button GPIO pin value.
|
||||
*/
|
||||
uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)
|
||||
{
|
||||
/* There is no Wakeup button on STM32f0-Discovery Kit */
|
||||
return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,292 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32f0xx.s
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief STM32F0xx Devices vector table for RIDE7 toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M0 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m0
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
.equ BootRAM, 0xF108F85F
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
movs r1, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyDataInit
|
||||
ldr r2, =_sbss
|
||||
b LoopFillZerobss
|
||||
/* Zero fill the bss segment. */
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2], #4
|
||||
|
||||
LoopFillZerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/*******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex M0. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word WWDG_IRQHandler
|
||||
.word PVD_IRQHandler
|
||||
.word RTC_IRQHandler
|
||||
.word FLASH_IRQHandler
|
||||
.word RCC_IRQHandler
|
||||
.word EXTI0_1_IRQHandler
|
||||
.word EXTI2_3_IRQHandler
|
||||
.word EXTI4_15_IRQHandler
|
||||
.word TS_IRQHandler
|
||||
.word DMA1_Channel1_IRQHandler
|
||||
.word DMA1_Channel2_3_IRQHandler
|
||||
.word DMA1_Channel4_5_IRQHandler
|
||||
.word ADC1_COMP_IRQHandler
|
||||
.word TIM1_BRK_UP_TRG_COM_IRQHandler
|
||||
.word TIM1_CC_IRQHandler
|
||||
.word TIM2_IRQHandler
|
||||
.word TIM3_IRQHandler
|
||||
.word TIM6_DAC_IRQHandler
|
||||
.word 0
|
||||
.word TIM14_IRQHandler
|
||||
.word TIM15_IRQHandler
|
||||
.word TIM16_IRQHandler
|
||||
.word TIM17_IRQHandler
|
||||
.word I2C1_IRQHandler
|
||||
.word I2C2_IRQHandler
|
||||
.word SPI1_IRQHandler
|
||||
.word SPI2_IRQHandler
|
||||
.word USART1_IRQHandler
|
||||
.word USART2_IRQHandler
|
||||
.word 0
|
||||
.word CEC_IRQHandler
|
||||
.word 0
|
||||
.word BootRAM /* @0x108. This is for boot in RAM mode for
|
||||
STM32F0xx devices. */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_IRQHandler
|
||||
.thumb_set PVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_IRQHandler
|
||||
.thumb_set RTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_1_IRQHandler
|
||||
.thumb_set EXTI0_1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_3_IRQHandler
|
||||
.thumb_set EXTI2_3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_15_IRQHandler
|
||||
.thumb_set EXTI4_15_IRQHandler,Default_Handler
|
||||
|
||||
.weak TS_IRQHandler
|
||||
.thumb_set TS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_3_IRQHandler
|
||||
.thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_5_IRQHandler
|
||||
.thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_COMP_IRQHandler
|
||||
.thumb_set ADC1_COMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_UP_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_DAC_IRQHandler
|
||||
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM14_IRQHandler
|
||||
.thumb_set TIM14_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM15_IRQHandler
|
||||
.thumb_set TIM15_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM16_IRQHandler
|
||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM17_IRQHandler
|
||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_IRQHandler
|
||||
.thumb_set I2C1_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_IRQHandler
|
||||
.thumb_set I2C2_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak CEC_IRQHandler
|
||||
.thumb_set CEC_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
#include "stm32f4xx_conf.h"
|
||||
|
||||
int main(void)
|
||||
{
|
||||
|
||||
//#elif CONFIG_STM32F0_DISCOVERY
|
||||
//
|
||||
//#define GPIOC 0x48000800 /* port C */
|
||||
//#define GPIOC_MODER (GPIOC + 0x00) /* port mode register */
|
||||
//#define LED_PORT_ODR (GPIOC + 0x14) /* port output data register */
|
||||
//
|
||||
//#define LED_BLUE (1 << 8) /* port C, pin 8 */
|
||||
//#define LED_GREEN (1 << 9) /* port C, pin 9 */
|
||||
//#define LED_ORANGE 0
|
||||
//#define LED_RED 0
|
||||
|
||||
GPIOC->MODER = (1 << 16);
|
||||
|
||||
while(1) GPIOC->ODR ^= (1 << 16);
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,353 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f0xx.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 23-March-2012
|
||||
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
|
||||
* This file contains the system clock configuration for STM32F0xx devices,
|
||||
* and is generated by the clock configuration tool
|
||||
* STM32F0xx_Clock_Configuration_V1.0.0.xls
|
||||
*
|
||||
* 1. This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
|
||||
* and Divider factors, AHB/APBx prescalers and Flash settings),
|
||||
* depending on the configuration made in the clock xls tool.
|
||||
* This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32f0xx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* 2. After each device reset the HSI (8 MHz Range) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
|
||||
* configure the system clock before to branch to main program.
|
||||
*
|
||||
* 3. If the system clock source selected by user fails to startup, the SystemInit()
|
||||
* function will do nothing and HSI still used as system clock source. User can
|
||||
* add some code to deal with this issue inside the SetSysClock() function.
|
||||
*
|
||||
* 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
|
||||
* in "stm32f0xx.h" file. When HSE is used as system clock source, directly or
|
||||
* through PLL, and you are using different crystal you have to adapt the HSE
|
||||
* value to your own configuration.
|
||||
*
|
||||
* 5. This file configures the system clock as follows:
|
||||
*=============================================================================
|
||||
* System Clock Configuration
|
||||
*=============================================================================
|
||||
* System Clock source | PLL(HSE)
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK | 48000000 Hz
|
||||
*-----------------------------------------------------------------------------
|
||||
* HCLK | 48000000 Hz
|
||||
*-----------------------------------------------------------------------------
|
||||
* AHB Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB1 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB2 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* HSE Frequency | 8000000 Hz
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL MUL | 6
|
||||
*-----------------------------------------------------------------------------
|
||||
* VDD | 3.3 V
|
||||
*-----------------------------------------------------------------------------
|
||||
* Flash Latency | 1 WS
|
||||
*-----------------------------------------------------------------------------
|
||||
*=============================================================================
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f0xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F0xx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32f0xx.h"
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F0xx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F0xx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F0xx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
uint32_t SystemCoreClock = 48000000;
|
||||
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
static void SetSysClock(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F0xx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the Embedded Flash Interface, the PLL and update the
|
||||
* SystemCoreClock variable.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
/* Set HSION bit */
|
||||
RCC->CR |= (uint32_t)0x00000001;
|
||||
|
||||
/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
|
||||
RCC->CFGR &= (uint32_t)0xF8FFB80C;
|
||||
|
||||
/* Reset HSEON, CSSON and PLLON bits */
|
||||
RCC->CR &= (uint32_t)0xFEF6FFFF;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||
|
||||
/* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
|
||||
RCC->CFGR &= (uint32_t)0xFFC0FFFF;
|
||||
|
||||
/* Reset PREDIV1[3:0] bits */
|
||||
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
|
||||
|
||||
/* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
|
||||
RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
|
||||
|
||||
/* Reset HSI14 bit */
|
||||
RCC->CR2 &= (uint32_t)0xFFFFFFFE;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIR = 0x00000000;
|
||||
|
||||
/* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
|
||||
SetSysClock();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock according to Clock Register Values
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value
|
||||
* 8 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value
|
||||
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
||||
|
||||
switch (tmp)
|
||||
{
|
||||
case 0x00: /* HSI used as system clock */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x04: /* HSE used as system clock */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x08: /* PLL used as system clock */
|
||||
/* Get PLL clock source and multiplication factor ----------------------*/
|
||||
pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
|
||||
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
|
||||
pllmull = ( pllmull >> 18) + 2;
|
||||
|
||||
if (pllsource == 0x00)
|
||||
{
|
||||
/* HSI oscillator clock divided by 2 selected as PLL clock entry */
|
||||
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
|
||||
}
|
||||
else
|
||||
{
|
||||
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
|
||||
/* HSE oscillator clock selected as PREDIV1 clock entry */
|
||||
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
|
||||
}
|
||||
break;
|
||||
default: /* HSI used as system clock */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK clock frequency ----------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
||||
/* HCLK clock frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock frequency, AHB/APBx prescalers and Flash
|
||||
* settings.
|
||||
* @note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
static void SetSysClock(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
/* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
|
||||
/* Enable HSE */
|
||||
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* Enable Prefetch Buffer and set Flash Latency */
|
||||
FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
||||
|
||||
/* PCLK = HCLK */
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
|
||||
|
||||
/* PLL configuration = HSE * 6 = 48 MHz */
|
||||
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
|
||||
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
|
||||
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{ /* If HSE fails to start-up, the application will have wrong clock
|
||||
configuration. User can add here some code to deal with this error */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
Loading…
Reference in New Issue