|
|
|
@ -1,4 +1,11 @@ |
|
|
|
|
//#include "stm32f0xx_conf.h"
|
|
|
|
|
#include "stm32f0xx_conf.h" |
|
|
|
|
|
|
|
|
|
void TIM2_IRQHandler(void) { |
|
|
|
|
// flash on update event
|
|
|
|
|
if (TIM2->SR & TIM_SR_UIF) GPIOC->ODR ^= (1 << 8); |
|
|
|
|
|
|
|
|
|
TIM2->SR = 0x0; // reset the status register
|
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
int main(void) |
|
|
|
|
{ |
|
|
|
@ -14,10 +21,20 @@ int main(void) |
|
|
|
|
//#define LED_ORANGE 0
|
|
|
|
|
//#define LED_RED 0
|
|
|
|
|
|
|
|
|
|
RCC->AHBENR |= RCC_AHBENR_IOPCEN; // enable the clock to GPIOC
|
|
|
|
|
RCC->AHBENR |= RCC_AHBENR_GPIOCEN; // enable the clock to GPIOC
|
|
|
|
|
//(RM0091 lists this as IOPCEN, not GPIOCEN)
|
|
|
|
|
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; // enable TIM2 clock
|
|
|
|
|
|
|
|
|
|
GPIOC->MODER = (1 << 16); |
|
|
|
|
|
|
|
|
|
while(1) GPIOC->ODR ^= (1 << 16); |
|
|
|
|
NVIC->ISER[0] |= 1<< (TIM2_IRQn); // enable the TIM2 IRQ
|
|
|
|
|
|
|
|
|
|
TIM2->PSC = 0x0; // no prescaler, timer counts up in sync with the peripheral clock
|
|
|
|
|
TIM2->DIER |= TIM_DIER_UIE; // enable update interrupt
|
|
|
|
|
TIM2->ARR = 0x01; // count to 1 (autoreload value 1)
|
|
|
|
|
TIM2->CR1 |= TIM_CR1_ARPE | TIM_CR1_CEN; // autoreload on, counter enabled
|
|
|
|
|
TIM2->EGR = 1; // trigger update event to reload timer registers
|
|
|
|
|
|
|
|
|
|
while(1); |
|
|
|
|
|
|
|
|
|
} |
|
|
|
|