/*
 * Copyright (C) 2009 by Sascha Hauer <s.hauer@pengutronix.de>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option, NO_PAD_CTRL) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */

#ifndef __MACH_IOMUX_MX51_H__
#define __MACH_IOMUX_MX51_H__

#include <mach/iomux-v3.h>

#define MX51_FEC_PAD_CTRL      (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)

#define MX51_SDHCI_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
		PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \
		PAD_CTL_SRE_FAST | PAD_CTL_DVS)

/*
 * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
 * If <padname> or <padmode> refers to a GPIO, it is named
 * GPIO_<unit>_<num> see also iomux-v3.h
 */

/*								  PAD    MUX   ALT INPSE PATH */
#define MX51_PAD_EIM_DA0__EIM_DA0			IOMUX_PAD(0x7A8, 0x1C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA1__EIM_DA1			IOMUX_PAD(0x7A8, 0x20, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA2__EIM_DA2			IOMUX_PAD(0x7A8, 0x24, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA3__EIM_DA3			IOMUX_PAD(0x7A8, 0x28, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA4__EIM_DA4			IOMUX_PAD(0x7AC, 0x2C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA5__EIM_DA5			IOMUX_PAD(0x7AC, 0x30, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA6__EIM_DA6			IOMUX_PAD(0x7AC, 0x34, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA7__EIM_DA7			IOMUX_PAD(0x7AC, 0x38, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA8__EIM_DA8			IOMUX_PAD(0x7B0, 0x3C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA9__EIM_DA9			IOMUX_PAD(0x7B0, 0x40, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA10__EIM_DA10			IOMUX_PAD(0x7B0, 0x44, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA11__EIM_DA11			IOMUX_PAD(0x7B0, 0x48, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA12__EIM_DA12			IOMUX_PAD(0x7BC, 0x4C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA13__EIM_DA13			IOMUX_PAD(0x7BC, 0x50, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA14__EIM_DA14			IOMUX_PAD(0x7BC, 0x54, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DA15__EIM_DA15			IOMUX_PAD(0x7BC, 0x58, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D16__EIM_D16			IOMUX_PAD(0x3F0, 0x5C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D17__EIM_D17			IOMUX_PAD(0x3F4, 0x60, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D18__EIM_D18			IOMUX_PAD(0x3F8, 0x64, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D19__EIM_D19			IOMUX_PAD(0x3FC, 0x68, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D20__EIM_D20			IOMUX_PAD(0x400, 0x6C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D21__EIM_D21			IOMUX_PAD(0x404, 0x70, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D22__EIM_D22			IOMUX_PAD(0x408, 0x74, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D23__EIM_D23			IOMUX_PAD(0x40C, 0x78, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D24__EIM_D24			IOMUX_PAD(0x410, 0x7C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D25__EIM_D25			IOMUX_PAD(0x414, 0x80, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D26__EIM_D26			IOMUX_PAD(0x418, 0x84, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D27__EIM_D27			IOMUX_PAD(0x41C, 0x88, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D28__EIM_D28			IOMUX_PAD(0x420, 0x8C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D29__EIM_D29			IOMUX_PAD(0x424, 0x90, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D30__EIM_D30			IOMUX_PAD(0x428, 0x94, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D31__EIM_D31			IOMUX_PAD(0x42C, 0x98, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A16__EIM_A16			IOMUX_PAD(0x430, 0x9C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A17__EIM_A17			IOMUX_PAD(0x434, 0xA0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A18__EIM_A18			IOMUX_PAD(0x438, 0xA4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A19__EIM_A19			IOMUX_PAD(0x43C, 0xA8, 0, 0x0, 0, NO_PAD_CTRL)

#define MX51_PAD_EIM_A20__EIM_A20			IOMUX_PAD(0x440, 0xAC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A20__GPIO2_14			IOMUX_PAD(0x440, 0xAC, 1, 0x0, 0, NO_PAD_CTRL)

#define MX51_PAD_EIM_A21__EIM_A21			IOMUX_PAD(0x444, 0xB0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A22__EIM_A22			IOMUX_PAD(0x448, 0xB4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A23__EIM_A23			IOMUX_PAD(0x44C, 0xB8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A24__EIM_A24			IOMUX_PAD(0x450, 0xBC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A25__EIM_A25			IOMUX_PAD(0x454, 0xC0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A26__EIM_A26			IOMUX_PAD(0x458, 0xC4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A27__EIM_A27			IOMUX_PAD(0x45C, 0xC8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_EB0__EIM_EB0			IOMUX_PAD(0x460, 0xCC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_EB1__EIM_EB1			IOMUX_PAD(0x464, 0xD0, 0, 0x0, 0, NO_PAD_CTRL)

#define MX51_PAD_EIM_EB2__EIM_EB2			IOMUX_PAD(0x468, 0xD4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_EB2__FEC_MDIO			IOMUX_PAD(0x468, 0x0d4, 3, 0x954,   0, MX51_FEC_PAD_CTRL)

#define MX51_PAD_EIM_EB3__EIM_EB3			IOMUX_PAD(0x46C, 0xD8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_EB3__FEC_RDATA1			IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c,   0, MX51_FEC_PAD_CTRL)

#define MX51_PAD_EIM_OE__EIM_OE				IOMUX_PAD(0x470, 0xDC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS0__EIM_CS0			IOMUX_PAD(0x474, 0xE0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS1__EIM_CS1			IOMUX_PAD(0x478, 0xE4, 0, 0x0, 0, NO_PAD_CTRL)

#define MX51_PAD_EIM_CS2__EIM_CS2			IOMUX_PAD(0x47C, 0xE8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS2__FEC_RDATA2			IOMUX_PAD(0x47c, 0x0e8, 3, 0x960,   0, MX51_FEC_PAD_CTRL)

#define MX51_PAD_EIM_CS3__EIM_CS3			IOMUX_PAD(0x480, 0xEC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS3__FEC_RDATA3			IOMUX_PAD(0x480, 0x0ec, 3, 0x964,   0, MX51_FEC_PAD_CTRL)

#define MX51_PAD_EIM_CS4__EIM_CS4			IOMUX_PAD(0x484, 0xF0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS4__FEC_RX_ER			IOMUX_PAD(0x484, 0x0f0, 3, 0x970,   0, MX51_FEC_PAD_CTRL)

#define MX51_PAD_EIM_CS5__EIM_CS5			IOMUX_PAD(0x488, 0xF4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS5__FEC_CRS			IOMUX_PAD(0x52C, 0xF4, 3, 0x950, 0, MX51_FEC_PAD_CTRL)

#define MX51_PAD_EIM_DTACK__EIM_DTACK			IOMUX_PAD(0x48C, 0xF8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DTACK__GPIO2_31			IOMUX_PAD(0x48c, 0xf8, 1, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_LBA__EIM_LBA			IOMUX_PAD(0x494, 0xFC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CRE__EIM_CRE			IOMUX_PAD(0x4A0, 0x100, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DRAM_CS1__DRAM_CS1			IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_WE_B__NANDF_WE_B			IOMUX_PAD(0x4E4, 0x108, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RE_B__NANDF_RE_B			IOMUX_PAD(0x4E8, 0x10C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_ALE__NANDF_ALE			IOMUX_PAD(0x4EC, 0x110, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CLE__NANDF_CLE			IOMUX_PAD(0x4F0, 0x114, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_WP_B__NANDF_WP_B			IOMUX_PAD(0x4F4, 0x118, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB0__NANDF_RB0			IOMUX_PAD(0x4F8, 0x11C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB1__NANDF_RB1			IOMUX_PAD(0x4FC, 0x120, 0, 0x0, 0, NO_PAD_CTRL)

#define MX51_PAD_NANDF_RB2__NANDF_RB2			IOMUX_PAD(0x500, 0x124, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB2__FEC_COL			IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_FEC_PAD_CTRL)

#define MX51_PAD_NANDF_RB3__NANDF_RB3			IOMUX_PAD(0x504, 0x128, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB3__FEC_RX_CLK			IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_FEC_PAD_CTRL)

#define MX51_PAD_NANDF_RB4__NANDF_RB4			IOMUX_PAD(0x514, 0x12C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB5__NANDF_RB5			IOMUX_PAD(0x5D8, 0x130, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB6__FEC_RDATA0			IOMUX_PAD(0x5DC, 0x16C, 2, 0x958, 0, MX51_FEC_PAD_CTRL)

#define MX51_PAD_NANDF_RB7__NANDF_RB7			IOMUX_PAD(0x5E0, 0x138, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB7__FEC_TX_ER			IOMUX_PAD(0x5E0, 0x138, 2, 0x0, 0, NO_PAD_CTRL)

#define MX51_PAD_NANDF_CS0__NANDF_CS0			IOMUX_PAD(0x518, 0x130, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS1__NANDF_CS1			IOMUX_PAD(0x51C, 0x134, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS2__NANDF_CS2			IOMUX_PAD(0x520, 0x138, 0, 0x0, 0, NO_PAD_CTRL)

#define MX51_PAD_NANDF_CS3__NANDF_CS3			IOMUX_PAD(0x524, 0x13C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS3__FEC_MDC			IOMUX_PAD(0x524, 0x13C, 2, 0x0, 0,MX51_FEC_PAD_CTRL)

#define MX51_PAD_NANDF_CS4__NANDF_CS4			IOMUX_PAD(0x528, 0x140, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS4__FEC_TDATA1			IOMUX_PAD(0x528, 0x140, 2, 0x0, 0, MX51_FEC_PAD_CTRL)

#define MX51_PAD_NANDF_CS5__NANDF_CS5			IOMUX_PAD(0x52C, 0x144, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS5__FEC_TDATA2			IOMUX_PAD(0x52C, 0x144, 2, 0x0, 0, MX51_FEC_PAD_CTRL)

#define MX51_PAD_NANDF_CS6__NANDF_CS6			IOMUX_PAD(0x530, 0x148, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS6__FEC_TDATA3			IOMUX_PAD(0x530, 0x148, 2, 0x0, 0, MX51_FEC_PAD_CTRL)

#define MX51_PAD_NANDF_CS7__NANDF_CS7			IOMUX_PAD(0x534, 0x14C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS7__FEC_TX_EN			IOMUX_PAD(0x534, 0x14C, 1, 0x0, 0, MX51_FEC_PAD_CTRL)

#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT		IOMUX_PAD(0x538, 0x150, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK		IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_FEC_PAD_CTRL)

#define MX51_PAD_NANDF_D15__NANDF_D15			IOMUX_PAD(0x53C, 0x154, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D14__NANDF_D14			IOMUX_PAD(0x540, 0x158, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D13__NANDF_D13			IOMUX_PAD(0x544, 0x15C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D12__NANDF_D12			IOMUX_PAD(0x548, 0x160, 0, 0x0, 0, NO_PAD_CTRL)

#define MX51_PAD_NANDF_D11__NANDF_D11			IOMUX_PAD(0x54C, 0x164, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D11__FEC_RX_DV			IOMUX_PAD(0x54C, 0x164, 2, 0x96c, 0, MX51_FEC_PAD_CTRL)

#define MX51_PAD_NANDF_D10__NANDF_D10			IOMUX_PAD(0x550, 0x168, 0, 0x0, 0, NO_PAD_CTRL)

#define MX51_PAD_NANDF_D9__NANDF_D9			IOMUX_PAD(0x554, 0x16C, 0, 0x0, 0, NO_PAD_CTRL)

#define MX51_PAD_NANDF_D8__NANDF_D8			IOMUX_PAD(0x558, 0x170, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D8__FEC_TDATA0			IOMUX_PAD(0x558, 0x170, 2, 0x0, 0, MX51_FEC_PAD_CTRL)

#define MX51_PAD_NANDF_D7__NANDF_D7			IOMUX_PAD(0x55C, 0x174, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D6__NANDF_D6			IOMUX_PAD(0x560, 0x178, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D5__NANDF_D5			IOMUX_PAD(0x564, 0x17C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D4__NANDF_D4			IOMUX_PAD(0x568, 0x180, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D3__NANDF_D3			IOMUX_PAD(0x56C, 0x184, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D2__NANDF_D2			IOMUX_PAD(0x570, 0x188, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D1__NANDF_D1			IOMUX_PAD(0x574, 0x18C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D0__NANDF_D0			IOMUX_PAD(0x578, 0x190, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D8__CSI1_D8			IOMUX_PAD(0x57C, 0x194, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D9__CSI1_D9			IOMUX_PAD(0x580, 0x198, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D10__CSI1_D10			IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D11__CSI1_D11			IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D12__CSI1_D12			IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D13__CSI1_D13			IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D14__CSI1_D14			IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D15__CSI1_D15			IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D16__CSI1_D16			IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D17__CSI1_D17			IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D18__CSI1_D18			IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D19__CSI1_D19			IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC			IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC			IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK		IOMUX_PAD(0x5B4, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_MCLK__CSI1_MCLK			IOMUX_PAD(0x5B8, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_PKE0__CSI1_PKE0			IOMUX_PAD(0x860, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_D12__CSI2_D12			IOMUX_PAD(0x5BC, 0x1CC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_D13__CSI2_D13			IOMUX_PAD(0x5C0, 0x1D0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_D14__CSI2_D14			IOMUX_PAD(0x5C4, 0x1D4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_D15__CSI2_D15			IOMUX_PAD(0x5C8, 0x1D8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_D16__CSI2_D16			IOMUX_PAD(0x5CC, 0x1DC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_D17__CSI2_D17			IOMUX_PAD(0x5D0, 0x1E0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_D18__CSI2_D18			IOMUX_PAD(0x5D4, 0x1E4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_D19__CSI2_D19			IOMUX_PAD(0x5D8, 0x1E8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC			IOMUX_PAD(0x5DC, 0x1EC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC			IOMUX_PAD(0x5E0, 0x1F0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK		IOMUX_PAD(0x5E4, 0x1F4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_PKE0__CSI2_PKE0			IOMUX_PAD(0x81C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_I2C1_CLK__I2C1_CLK			IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_I2C1_DAT__I2C1_DAT			IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_AUD3_BB_TXD__AUD3_BB_TXD		IOMUX_PAD(0x5F0, 0x200, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_AUD3_BB_RXD__AUD3_BB_RXD		IOMUX_PAD(0x5F4, 0x204, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_AUD3_BB_CK__AUD3_BB_CK			IOMUX_PAD(0x5F8, 0x208, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_AUD3_BB_FS__AUD3_BB_FS			IOMUX_PAD(0x5FC, 0x20C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_MOSI__CSPI1_MOSI			IOMUX_PAD(0x600, 0x210, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_MISO__CSPI1_MISO			IOMUX_PAD(0x604, 0x214, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_SS0__CSPI1_SS0			IOMUX_PAD(0x608, 0x218, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_SS1__CSPI1_SS1			IOMUX_PAD(0x60C, 0x21C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_RDY__CSPI1_RDY			IOMUX_PAD(0x610, 0x220, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_SCLK__CSPI1_SCLK			IOMUX_PAD(0x614, 0x224, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_UART1_RXD__UART1_RXD			IOMUX_PAD(0x618, 0x228, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_UART1_TXD__UART1_TXD			IOMUX_PAD(0x61C, 0x22C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_UART1_RTS__UART1_RTS			IOMUX_PAD(0x620, 0x230, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_UART1_CTS__UART1_CTS			IOMUX_PAD(0x624, 0x234, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_UART2_RXD__UART2_RXD			IOMUX_PAD(0x628, 0x238, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_UART2_TXD__UART2_TXD			IOMUX_PAD(0x62C, 0x23C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_UART3_RXD__UART3_RXD			IOMUX_PAD(0x630, 0x240, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_UART3_TXD__UART3_TXD			IOMUX_PAD(0x634, 0x244, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_OWIRE_LINE__OWIRE_LINE			IOMUX_PAD(0x638, 0x248, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_KEY_ROW0__KEY_ROW0			IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_KEY_ROW1__KEY_ROW1			IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_KEY_ROW2__KEY_ROW2			IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_KEY_ROW3__KEY_ROW3			IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_KEY_COL0__KEY_COL0			IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_KEY_COL1__KEY_COL1			IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_KEY_COL2__KEY_COL2			IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_KEY_COL3__KEY_COL3			IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_KEY_COL4__KEY_COL4			IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_KEY_COL5__KEY_COL5			IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_USBH1_CLK__USBH1_CLK			IOMUX_PAD(0x678, 0x278, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_USBH1_DIR__USBH1_DIR			IOMUX_PAD(0x67C, 0x27C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_USBH1_STP__USBH1_STP			IOMUX_PAD(0x680, 0x280, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_USBH1_NXT__USBH1_NXT			IOMUX_PAD(0x684, 0x284, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_USBH1_DATA0__USBH1_DATA0		IOMUX_PAD(0x688, 0x288, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_USBH1_DATA1__USBH1_DATA1		IOMUX_PAD(0x68C, 0x28C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_USBH1_DATA2__USBH1_DATA2		IOMUX_PAD(0x690, 0x290, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_USBH1_DATA3__USBH1_DATA3		IOMUX_PAD(0x694, 0x294, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_USBH1_DATA4__USBH1_DATA4		IOMUX_PAD(0x698, 0x298, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_USBH1_DATA5__USBH1_DATA5		IOMUX_PAD(0x69C, 0x29C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_USBH1_DATA6__USBH1_DATA6		IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_USBH1_DATA7__USBH1_DATA7		IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI1_PIN11__DI1_PIN11			IOMUX_PAD(0x6A8, 0x2A8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI1_PIN12__DI1_PIN12			IOMUX_PAD(0x6AC, 0x2AC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI1_PIN13__DI1_PIN13			IOMUX_PAD(0x6B0, 0x2B0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI1_D0_CS__DI1_D0_CS			IOMUX_PAD(0x6B4, 0x2B4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI1_D1_CS__DI1_D1_CS			IOMUX_PAD(0x6B8, 0x2B8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI1_D1_CS__GPIO3_4			IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0984, 1, NO_PAD_CTRL)
#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN		IOMUX_PAD(0x6BC, 0x2BC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO		IOMUX_PAD(0x6C0, 0x2C0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK		IOMUX_PAD(0x6C4, 0x2C4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS		IOMUX_PAD(0x6C8, 0x2C8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT0__DISP1_DAT0			IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT1__DISP1_DAT1			IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT2__DISP1_DAT2			IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT3__DISP1_DAT3			IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT4__DISP1_DAT4			IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT5__DISP1_DAT5			IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT6__DISP1_DAT6			IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT7__DISP1_DAT7			IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT8__DISP1_DAT8			IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT9__DISP1_DAT9			IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT10__DISP1_DAT10		IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT11__DISP1_DAT11		IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT12__DISP1_DAT12		IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT13__DISP1_DAT13		IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT14__DISP1_DAT14		IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT15__DISP1_DAT15		IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT16__DISP1_DAT16		IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT17__DISP1_DAT17		IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT18__DISP1_DAT18		IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT19__DISP1_DAT19		IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT20__DISP1_DAT20		IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT21__DISP1_DAT21		IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT22__DISP1_DAT22		IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT23__DISP1_DAT23		IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI1_PIN3__DI1_PIN3			IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI1_PIN2__DI1_PIN2			IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI_GP1__DI_GP1				IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI_GP2__DI_GP2				IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI_GP3__DI_GP3				IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI2_PIN4__DI2_PIN4			IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI_GP3__FEC_TX_ER			IOMUX_PAD(0x744, 0x33c, 2, 0x0, 0, MX51_FEC_PAD_CTRL)
#define MX51_PAD_DI2_PIN2__DI2_PIN2			IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI2_PIN2__FEC_MDC			IOMUX_PAD(0x74c, 0x344, 2, 0x0, 0, MX51_FEC_PAD_CTRL)
#define MX51_PAD_DI2_PIN3__DI2_PIN3			IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI2_PIN3__FEC_MDIO			IOMUX_PAD(0x750, 0x348, 2, 0x0954, 1, MX51_FEC_PAD_CTRL)
#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK		IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI_GP4__DI_GP4				IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DI_GP4__FEC_RDATA2			IOMUX_PAD(0x758, 0x350, 2, 0x0960, 1, MX51_FEC_PAD_CTRL)
#define MX51_PAD_DI2_PIN4__FEC_CRS			IOMUX_PAD(0x748, 0x340, 2, 0x0950, 1, MX51_FEC_PAD_CTRL)
#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1		IOMUX_PAD(0x754, 0x34c, 2, 0x095c, 1, MX51_FEC_PAD_CTRL)
#define MX51_PAD_DISP2_DAT0__DISP2_DAT0			IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT0__FEC_RDATA3			IOMUX_PAD(0x75c, 0x354, 2, 0x0964, 1, MX51_FEC_PAD_CTRL)
#define MX51_PAD_DISP2_DAT1__DISP2_DAT1			IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT1__FEC_RX_ER			IOMUX_PAD(0x760, 0x358, 2, 0x0970, 1, MX51_FEC_PAD_CTRL)
#define MX51_PAD_DISP2_DAT2__DISP2_DAT2			IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT3__DISP2_DAT3			IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT4__DISP2_DAT4			IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT5__DISP2_DAT5			IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT6__DISP2_DAT6			IOMUX_PAD(0x774, 0x36C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT6__FEC_TDATA1			IOMUX_PAD(0x774, 0x36c, 2, 0x0, 0, MX51_FEC_PAD_CTRL)
#define MX51_PAD_DISP2_DAT7__DISP2_DAT7			IOMUX_PAD(0x778, 0x370, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT7__FEC_TDATA2			IOMUX_PAD(0x778, 0x370, 2, 0x0, 0, MX51_FEC_PAD_CTRL)
#define MX51_PAD_DISP2_DAT8__DISP2_DAT8			IOMUX_PAD(0x77C, 0x374, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT8__FEC_TDATA3			IOMUX_PAD(0x77c, 0x374, 2, 0x0, 0, MX51_FEC_PAD_CTRL)
#define MX51_PAD_DISP2_DAT9__DISP2_DAT9			IOMUX_PAD(0x780, 0x378, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT9__FEC_TX_EN			IOMUX_PAD(0x780, 0x378, 2, 0x0, 0, MX51_FEC_PAD_CTRL)
#define MX51_PAD_DISP2_DAT10__DISP2_DAT10		IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT10__FEC_COL			IOMUX_PAD(0x784, 0x37c, 2, 0x094c, 1, MX51_FEC_PAD_CTRL)
#define MX51_PAD_DISP2_DAT11__DISP2_DAT11		IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK		IOMUX_PAD(0x788, 0x380, 2, 0x0968, 1, MX51_FEC_PAD_CTRL)
#define MX51_PAD_DISP2_DAT12__DISP2_DAT12		IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT12__FEC_RX_DV			IOMUX_PAD(0x78c, 0x384, 2, 0x096c, 1, MX51_FEC_PAD_CTRL)
#define MX51_PAD_DISP2_DAT13__DISP2_DAT13		IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK		IOMUX_PAD(0x790, 0x388, 2, 0x0974, 1, MX51_FEC_PAD_CTRL)
#define MX51_PAD_DISP2_DAT14__DISP2_DAT14		IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT14__FEC_RDATA0		IOMUX_PAD(0x794, 0x38c, 2, 0x0958, 1, MX51_FEC_PAD_CTRL)
#define MX51_PAD_DISP2_DAT15__DISP2_DAT15		IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT15__FEC_TDATA0		IOMUX_PAD(0x798, 0x390, 2, 0x0, 0, MX51_FEC_PAD_CTRL)
#define MX51_PAD_SD1_CMD__SD1_CMD			IOMUX_PAD(0x79C, 0x394, 0x10, 0x0, 0, MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_SD1_CLK__SD1_CLK			IOMUX_PAD(0x7A0, 0x398, 0x10, 0x0, 0, MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_SD1_DATA0__SD1_DATA0			IOMUX_PAD(0x7A4, 0x39C, 0x10, 0x0, 0, MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_SD1_DATA1__SD1_DATA1			IOMUX_PAD(0x7A8, 0x3A0, 0x10, 0x0, 0, MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_SD1_DATA2__SD1_DATA2			IOMUX_PAD(0x7AC, 0x3A4, 0x10, 0x0, 0, MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_SD1_DATA3__SD1_DATA3			IOMUX_PAD(0x7B0, 0x3A8, 0x10, 0x0, 0, MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_GPIO1_0__GPIO1_0			IOMUX_PAD(0x7B4, 0x3AC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_1__GPIO1_1			IOMUX_PAD(0x7B8, 0x3B0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_SD2_CMD__SD2_CMD			IOMUX_PAD(0x7BC, 0x3B4, 0x10, 0x0, 0, MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_SD2_CLK__SD2_CLK			IOMUX_PAD(0x7C0, 0x3B8, 0x10, 0x0, 0, MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_SD2_DATA0__SD2_DATA0			IOMUX_PAD(0x7C4, 0x3BC, 0x10, 0x0, 0, MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_SD2_DATA1__SD2_DATA1			IOMUX_PAD(0x7C8, 0x3C0, 0x10, 0x0, 0, MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_SD2_DATA2__SD2_DATA2			IOMUX_PAD(0x7CC, 0x3C4, 0x10, 0x0, 0, MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_SD2_DATA3__SD2_DATA3			IOMUX_PAD(0x7D0, 0x3C8, 0x10, 0x0, 0, MX51_SDHCI_PAD_CTRL)
#define MX51_PAD_GPIO1_2__GPIO1_2			IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_3__GPIO1_3			IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ		IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_4__GPIO1_4			IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_5__GPIO1_5			IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_6__GPIO1_6			IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_7__GPIO1_7			IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_8__GPIO1_8			IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_9__GPIO1_9			IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
#endif /* __MACH_IOMUX_MX51_H__ */

