/*
 * P1022 RDK 32-bit Physical Address Map Device Tree Source
 *
 * Copyright 2012 Freescale Semiconductor Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Freescale Semiconductor nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation, either version 2 of that License or (at your option) any
 * later version.
 *
 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/include/ "fsl/p1022si-pre.dtsi"
/ {
	model = "fsl,P1022RDK";
	compatible = "fsl,P1022RDK";

	memory {
		device_type = "memory";
	};

	board_lbc: lbc: localbus@ffe05000 {
		/* The P1022 RDK does not have any localbus devices */
		status = "disabled";
	};

	board_soc: soc: soc@ffe00000 {
		ranges = <0x0 0x0 0xffe00000 0x100000>;

		i2c@3100 {
			wm8960:codec@1a {
				compatible = "wlf,wm8960";
				reg = <0x1a>;
				/* MCLK source is a stand-alone oscillator */
				clock-frequency = <12288000>;
			};
			rtc@68 {
				compatible = "stm,m41t62";
				reg = <0x68>;
			};
			adt7461@4c{
				compatible = "adi,adt7461";
				reg = <0x4c>;
			};
			zl6100@21{
				compatible = "isil,zl6100";
				reg = <0x21>;
			};
			zl6100@24{
				compatible = "isil,zl6100";
				reg = <0x24>;
			};
			zl6100@26{
				compatible = "isil,zl6100";
				reg = <0x26>;
			};
			zl6100@29{
				compatible = "isil,zl6100";
				reg = <0x29>;
			};
		};

		spi@7000 {
			flash@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "spansion,m25p80";
				reg = <0>;
				spi-max-frequency = <1000000>;
				partition@0 {
					label = "full-spi-flash";
					reg = <0x00000000 0x00100000>;
				};
			};
		};

		ssi@15000 {
			fsl,mode = "i2s-slave";
			codec-handle = <&wm8960>;
		};

		usb@22000 {
			phy_type = "ulpi";
		};

		usb@23000 {
			phy_type = "ulpi";
		};

		mdio@24000 {
			phy0: ethernet-phy@0 {
				interrupts = <3 1 0 0>;
				reg = <0x1>;
			};
			phy1: ethernet-phy@1 {
				interrupts = <9 1 0 0>;
				reg = <0x2>;
			};
		};

		mdio@25000 {
			tbi0: tbi-phy@11 {
				reg = <0x11>;
				device_type = "tbi-phy";
			};
		};

		ethernet@b0000 {
			phy-handle = <&phy0>;
			phy-connection-type = "rgmii-id";
		};

		ethernet@b1000 {
			phy-handle = <&phy1>;
			tbi-handle = <&tbi0>;
			phy-connection-type = "sgmii";
		};
	};

	pci0: pcie@ffe09000 {
		ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
		reg = <0x0 0xffe09000 0 0x1000>;
		pcie@0 {
			ranges = <0x2000000 0x0 0xe0000000
				  0x2000000 0x0 0xe0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};

	pci1: pcie@ffe0a000 {
		ranges = <0x2000000 0x0 0xe0000000 0 0xc0000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
		reg = <0 0xffe0a000 0 0x1000>;
		pcie@0 {
			ranges = <0x2000000 0x0 0xe0000000
				  0x2000000 0x0 0xe0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};

	pci2: pcie@ffe0b000 {
		ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
		reg = <0 0xffe0b000 0 0x1000>;
		pcie@0 {
			ranges = <0x2000000 0x0 0xe0000000
				  0x2000000 0x0 0xe0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};
};

/include/ "fsl/p1022si-post.dtsi"
