
/ {
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			reg = <0>;
			model = "ti,c64x+";
		};
		cpu@1 {
			device_type = "cpu";
			reg = <1>;
			model = "ti,c64x+";
		};
		cpu@2 {
			device_type = "cpu";
			reg = <2>;
			model = "ti,c64x+";
		};
	};

	soc {
		compatible = "simple-bus";
		model = "tms320c6474";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		core_pic: interrupt-controller {
			interrupt-controller;
			#interrupt-cells = <1>;
			compatible = "ti,c64x+core-pic";
		};

		megamod_pic: interrupt-controller@1800000 {
		       compatible = "ti,c64x+megamod-pic";
		       interrupt-controller;
		       #interrupt-cells = <1>;
		       reg = <0x1800000 0x1000>;
		       interrupt-parent = <&core_pic>;
		};

		cache-controller@1840000 {
			compatible = "ti,c64x+cache";
			reg = <0x01840000 0x8400>;
		};

		timer3: timer@2940000 {
			compatible = "ti,c64x+timer64";
			ti,core-mask = < 0x04 >;
			reg = <0x2940000 0x40>;
		};

		timer4: timer@2950000 {
			compatible = "ti,c64x+timer64";
			ti,core-mask = < 0x02 >;
			reg = <0x2950000 0x40>;
		};

		timer5: timer@2960000 {
			compatible = "ti,c64x+timer64";
			ti,core-mask = < 0x01 >;
			reg = <0x2960000 0x40>;
		};

		device-state-controller@2880800 {
			compatible = "ti,c64x+dscr";
			reg = <0x02880800 0x400>;

			ti,dscr-devstat = <0x004>;
			ti,dscr-silicon-rev = <0x014 28 0xf>;
			ti,dscr-mac-fuse-regs = <0x34 3 4 5 6
						 0x38 0 0 1 2>;
		};

		clock-controller@29a0000 {
			compatible = "ti,c6474-pll", "ti,c64x+pll";
			reg = <0x029a0000 0x200>;
			ti,c64x+pll-bypass-delay = <120>;
			ti,c64x+pll-reset-delay = <30000>;
			ti,c64x+pll-lock-delay = <60000>;
		};
	};
};
