/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <arm/imx51-babbage.dts>

/ {
	chosen {
		stdout-path = &uart1;

		environment@0 {
			compatible = "barebox,environment";
			device-path = &esdhc1, "partname:barebox-environment";
		};
	};
};

&esdhc1 {
	#address-cells = <1>;
	#size-cells = <1>;

	partition@0 {
		label = "barebox-environment";
		reg = <0x80000 0x20000>;
	};
};

&iim {
	barebox,provide-mac-address = <&fec 1 9>;
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	imx51-babbage {
		pinctrl_fec: fecgrp {
			/*
			 * Overwrite upstream FEC iomux settings since these currently
			 * have NO_PAD_CTRL instead of real settings. Remove this once
			 * this is fixed upstream.
			 */
			fsl,pins = <
				MX51_PAD_EIM_EB2__FEC_MDIO		0x000001f5
				MX51_PAD_EIM_EB3__FEC_RDATA1		0x00000085
				MX51_PAD_EIM_CS2__FEC_RDATA2		0x00000085
				MX51_PAD_EIM_CS3__FEC_RDATA3		0x00000085
				MX51_PAD_EIM_CS4__FEC_RX_ER		0x00000180
				MX51_PAD_EIM_CS5__FEC_CRS		0x00000180
				MX51_PAD_NANDF_RB2__FEC_COL		0x00000180
				MX51_PAD_NANDF_RB3__FEC_RX_CLK		0x00000180
				MX51_PAD_NANDF_D9__FEC_RDATA0		0x00002180
				MX51_PAD_NANDF_D8__FEC_TDATA0		0x00002004
				MX51_PAD_NANDF_CS2__FEC_TX_ER		0x00002004
				MX51_PAD_NANDF_CS3__FEC_MDC		0x00002004
				MX51_PAD_NANDF_CS4__FEC_TDATA1		0x00002004
				MX51_PAD_NANDF_CS5__FEC_TDATA2		0x00002004
				MX51_PAD_NANDF_CS6__FEC_TDATA3		0x00002004
				MX51_PAD_NANDF_CS7__FEC_TX_EN		0x00002004
				MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK	0x00002180
				MX51_PAD_NANDF_D11__FEC_RX_DV		0x000020a4
				MX51_PAD_EIM_A20__GPIO2_14		0x00000085 /* Phy Reset */
			>;
		};
	};
};
