2013-05-10 06:00:46 +00:00
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/*
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* Raspberry PI MCI driver
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*
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* Support for SDHCI device on bcm2835
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* Based on sdhci-bcm2708.c (c) 2010 Broadcom
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* Inspired by bcm2835_sdhci.c from git://github.com/gonzoua/u-boot-pi.git
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*
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* Portions (e.g. read/write macros, concepts for back-to-back register write
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* timing workarounds) obviously extracted from the Linux kernel at:
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* https://github.com/raspberrypi/linux.git rpi-3.6.y
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*
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* The Linux kernel code has the following (c) and license, which is hence
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* propagated to here:
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Author: Wilhelm Lundgren <wilhelm.lundgren@cybercom.com>
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*/
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#include <common.h>
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#include <init.h>
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#include <mci.h>
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#include <io.h>
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#include <malloc.h>
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#include <clock.h>
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#include "mci-bcm2835.h"
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#include "sdhci.h"
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#define to_bcm2835_host(h) container_of(h, struct bcm2835_mci_host, mci)
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static int twoticks_delay;
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struct bcm2835_mci_host {
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struct mci_host mci;
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void __iomem *regs;
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struct device_d *hw_dev;
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int bus_width;
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u32 clock;
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u32 max_clock;
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u32 version;
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uint64_t last_write;
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};
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void bcm2835_mci_write(struct bcm2835_mci_host *host, u32 reg, u32 val)
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{
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/*
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* The Arasan has a bugette whereby it may lose the content of
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* successive writes to registers that are within two SD-card clock
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* cycles of each other (a clock domain crossing problem).
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* It seems, however, that the data register does not have this problem.
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* (Which is just as well - otherwise we'd have to nobble the DMA engine
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* too)
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*/
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if (host->last_write != 0)
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while ((get_time_ns() - host->last_write) < twoticks_delay)
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;
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host->last_write = get_time_ns();
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writel(val, host->regs + reg);
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}
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u32 bcm2835_mci_read(struct bcm2835_mci_host *host, u32 reg)
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{
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return readl(host->regs + reg);
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}
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/* Create special write data function since the data
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* register is not affected by the twoticks_delay bug
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* and we can thus get better speed here
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*/
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void bcm2835_mci_write_data(struct bcm2835_mci_host *host, u32 *p)
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{
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writel(*p, host->regs + SDHCI_BUFFER);
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}
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/* Make a read data functions as well just to keep structure */
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void bcm2835_mci_read_data(struct bcm2835_mci_host *host, u32 *p)
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{
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*p = readl(host->regs + SDHCI_BUFFER);
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}
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static int bcm2835_mci_transfer_data(struct bcm2835_mci_host *host,
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struct mci_cmd *cmd, struct mci_data *data) {
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u32 *p;
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u32 data_size, status, intr_status = 0;
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u32 data_ready_intr_mask;
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u32 data_ready_status_mask;
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int i = 0;
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void (*read_write_func)(struct bcm2835_mci_host*, u32*);
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data_size = data->blocksize * data->blocks;
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if (data->flags & MMC_DATA_READ) {
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p = (u32 *) data->dest;
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data_ready_intr_mask = IRQSTAT_BRR;
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data_ready_status_mask = PRSSTAT_BREN;
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read_write_func = &bcm2835_mci_read_data;
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} else {
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p = (u32 *) data->src;
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data_ready_intr_mask = IRQSTAT_BWR;
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data_ready_status_mask = PRSSTAT_BWEN;
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read_write_func = &bcm2835_mci_write_data;
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}
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do {
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intr_status = bcm2835_mci_read(host, SDHCI_INT_STATUS);
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if (intr_status & IRQSTAT_CIE) {
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dev_err(host->hw_dev,
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"Error occured while transferring data: 0x%X\n",
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intr_status);
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return -EPERM;
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}
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if (intr_status & data_ready_intr_mask) {
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status = bcm2835_mci_read(host, SDHCI_PRESENT_STATE);
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if ((status & data_ready_status_mask) == 0)
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continue;
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/*Clear latest int and transfer one block size of data*/
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bcm2835_mci_write(host, SDHCI_INT_STATUS,
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data_ready_intr_mask);
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for (i = 0; i < data->blocksize; i += 4) {
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read_write_func(host, p);
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p++;
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data_size -= 4;
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}
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}
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} while ((intr_status & IRQSTAT_TC) == 0);
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if (data_size != 0) {
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if (data->flags & MMC_DATA_READ)
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dev_err(host->hw_dev, "Error while reading:\n");
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else
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dev_err(host->hw_dev, "Error while writing:\n");
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dev_err(host->hw_dev, "Transferred %d bytes of data, wanted %d\n",
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(data->blocksize * data->blocks) - data_size,
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data->blocksize * data->blocks);
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dev_err(host->hw_dev, "Status: 0x%X, Interrupt: 0x%X\n",
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bcm2835_mci_read(host, SDHCI_PRESENT_STATE),
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bcm2835_mci_read(host, SDHCI_INT_STATUS));
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return -EPERM;
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}
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return 0;
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}
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static u32 bcm2835_mci_wait_command_done(struct bcm2835_mci_host *host)
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{
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u32 interrupt = 0;
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while (true) {
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interrupt = bcm2835_mci_read(
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host, SDHCI_INT_STATUS);
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if (interrupt & IRQSTAT_CIE)
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return -EPERM;
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if (interrupt & IRQSTAT_CC)
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break;
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}
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return 0;
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}
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static void bcm2835_mci_reset_emmc(struct bcm2835_mci_host *host, u32 reset,
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u32 wait_for)
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{
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u32 ret;
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u32 current = bcm2835_mci_read(host,
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SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET);
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bcm2835_mci_write(host,
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SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET,
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current | reset);
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while (true) {
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ret = bcm2835_mci_read(host,
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SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET);
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if (ret & wait_for)
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continue;
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break;
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}
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}
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/**
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* Process one command to the MCI card
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* @param host MCI host
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* @param cmd The command to process
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* @param data The data to handle in the command (can be NULL)
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* @return 0 on success, negative value else
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*/
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static int bcm2835_mci_request(struct mci_host *mci, struct mci_cmd *cmd,
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struct mci_data *data) {
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u32 command, block_data = 0, ret = 0;
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u32 wait_inhibit_mask = PRSSTAT_CICHB | PRSSTAT_CIDHB;
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struct bcm2835_mci_host *host = to_bcm2835_host(mci);
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command = COMMAND_CMD(cmd->cmdidx);
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if (cmd->resp_type != MMC_RSP_NONE) {
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if (cmd->resp_type & MMC_RSP_136)
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command |= COMMAND_RSPTYP_136;
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else if (cmd->resp_type & MMC_RSP_BUSY)
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command |= COMMAND_RSPTYP_48_BUSY;
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else
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command |= COMMAND_RSPTYP_48;
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if (cmd->resp_type & MMC_RSP_CRC)
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command |= COMMAND_CCCEN;
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}
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if (data != NULL) {
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command |= COMMAND_DPSEL | TRANSFER_MODE_BCEN;
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if (data->blocks > 1)
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command |= TRANSFER_MODE_MSBSEL;
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if (data->flags & MMC_DATA_READ)
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command |= TRANSFER_MODE_DTDSEL;
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block_data = (data->blocks << BLOCK_SHIFT);
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block_data |= data->blocksize;
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}
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/* We shouldn't wait for data inihibit for stop commands, even
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though they might use busy signaling */
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if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
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wait_inhibit_mask = PRSSTAT_CICHB;
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/*Wait for old command*/
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while (bcm2835_mci_read(host, SDHCI_PRESENT_STATE)
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& wait_inhibit_mask)
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;
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bcm2835_mci_write(host, SDHCI_INT_ENABLE, 0xFFFFFFFF);
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bcm2835_mci_write(host, SDHCI_INT_STATUS, 0xFFFFFFFF);
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bcm2835_mci_write(host, SDHCI_BLOCK_SIZE__BLOCK_COUNT, block_data);
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bcm2835_mci_write(host, SDHCI_ARGUMENT, cmd->cmdarg);
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bcm2835_mci_write(host, SDHCI_TRANSFER_MODE__COMMAND, command);
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ret = bcm2835_mci_wait_command_done(host);
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if (ret) {
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dev_err(host->hw_dev, "Error while executing command %d\n",
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cmd->cmdidx);
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dev_err(host->hw_dev, "Status: 0x%X, Interrupt: 0x%X\n",
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bcm2835_mci_read(host, SDHCI_PRESENT_STATE),
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bcm2835_mci_read(host, SDHCI_INT_STATUS));
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}
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if (cmd->resp_type != 0 && ret != -1) {
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int i = 0;
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/* CRC is stripped so we need to do some shifting. */
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if (cmd->resp_type & MMC_RSP_136) {
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for (i = 0; i < 4; i++) {
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cmd->response[i] = bcm2835_mci_read(
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host,
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SDHCI_RESPONSE_0 + (3 - i) * 4) << 8;
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if (i != 3)
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cmd->response[i] |=
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readb((u32) (host->regs) +
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SDHCI_RESPONSE_0 +
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(3 - i) * 4 - 1);
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}
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} else {
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cmd->response[0] = bcm2835_mci_read(
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host, SDHCI_RESPONSE_0);
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}
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bcm2835_mci_write(host, SDHCI_INT_STATUS,
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IRQSTAT_CC);
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}
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if (!ret && data)
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ret = bcm2835_mci_transfer_data(host, cmd, data);
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bcm2835_mci_write(host, SDHCI_INT_STATUS, 0xFFFFFFFF);
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if (ret) {
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bcm2835_mci_reset_emmc(host, CONTROL1_CMDRST,
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CONTROL1_CMDRST);
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bcm2835_mci_reset_emmc(host, CONTROL1_DATARST,
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CONTROL1_DATARST);
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}
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return ret;
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}
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static u32 bcm2835_mci_get_clock_divider(struct bcm2835_mci_host *host,
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u32 desired_hz)
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{
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u32 div;
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u32 clk_hz;
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if (host->version >= SDHCI_SPEC_300) {
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/* Version 3.00 divisors must be a multiple of 2. */
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if (host->max_clock <= desired_hz)
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div = 1;
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else {
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for (div = 2; div < MAX_CLK_DIVIDER_V3; div += 2) {
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clk_hz = host->max_clock / div;
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if (clk_hz <= desired_hz)
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break;
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}
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}
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} else {
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/* Version 2.00 divisors must be a power of 2. */
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for (div = 1; div < MAX_CLK_DIVIDER_V2; div *= 2) {
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clk_hz = host->max_clock / div;
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if (clk_hz <= desired_hz)
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break;
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}
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}
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/*Since setting lowest bit means divide by two, shift down*/
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dev_dbg(host->hw_dev,
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"Wanted %d hz, returning divider %d (%d) which yields %d hz\n",
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desired_hz, div >> 1, div, host->max_clock / div);
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twoticks_delay = ((2 * 1000000000) / (host->max_clock / div)) + 1;
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div = div >> 1;
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host->clock = desired_hz;
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return div;
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}
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/**
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* Setup the bus width and IO speed
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* @param host MCI host
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* @param bus_width New bus width value (1, 4 or 8)
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* @param clock New clock in Hz (can be '0' to disable the clock)
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*/
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static void bcm2835_mci_set_ios(struct mci_host *mci, struct mci_ios *ios)
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{
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u32 divider;
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u32 divider_msb, divider_lsb;
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u32 enable;
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u32 current_val;
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struct bcm2835_mci_host *host = to_bcm2835_host(mci);
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current_val = bcm2835_mci_read(host,
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SDHCI_HOST_CONTROL__POWER_CONTROL__BLOCK_GAP_CONTROL);
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switch (ios->bus_width) {
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case MMC_BUS_WIDTH_4:
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bcm2835_mci_write(host,
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SDHCI_HOST_CONTROL__POWER_CONTROL__BLOCK_GAP_CONTROL,
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current_val | CONTROL0_4DATA);
|
|
|
|
host->bus_width = 1;
|
|
|
|
dev_dbg(host->hw_dev, "Changing bus width to 4\n");
|
|
|
|
break;
|
|
|
|
case MMC_BUS_WIDTH_1:
|
|
|
|
bcm2835_mci_write(host,
|
|
|
|
SDHCI_HOST_CONTROL__POWER_CONTROL__BLOCK_GAP_CONTROL,
|
|
|
|
current_val & ~CONTROL0_4DATA);
|
|
|
|
host->bus_width = 0;
|
|
|
|
dev_dbg(host->hw_dev, "Changing bus width to 1\n");
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_warn(host->hw_dev, "Unsupported width received: %d\n",
|
|
|
|
ios->bus_width);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (ios->clock != host->clock && ios->clock != 0) {
|
|
|
|
bcm2835_mci_write(host,
|
|
|
|
SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET,
|
|
|
|
0x00);
|
|
|
|
|
|
|
|
if (ios->clock > 26000000) {
|
|
|
|
enable = bcm2835_mci_read(host,
|
|
|
|
SDHCI_HOST_CONTROL__POWER_CONTROL__BLOCK_GAP_CONTROL);
|
|
|
|
enable |= CONTROL0_HISPEED;
|
|
|
|
bcm2835_mci_write(host,
|
|
|
|
SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET,
|
|
|
|
enable);
|
|
|
|
}
|
|
|
|
|
|
|
|
divider = bcm2835_mci_get_clock_divider(host, ios->clock);
|
|
|
|
divider_msb = divider & 0x300;
|
|
|
|
divider_msb >>= CONTROL1_CLKLSB;
|
|
|
|
divider_lsb = divider & 0xFF;
|
|
|
|
enable = (divider_lsb << CONTROL1_CLKLSB);
|
|
|
|
enable |= (divider_msb << CONTROL1_CLKMSB);
|
|
|
|
enable |= CONTROL1_INTCLKENA | CONTROL1_TIMEOUT;
|
|
|
|
|
|
|
|
bcm2835_mci_write(host,
|
|
|
|
SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET,
|
|
|
|
enable);
|
|
|
|
while (true) {
|
|
|
|
u32 ret = bcm2835_mci_read(host,
|
|
|
|
SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET);
|
|
|
|
if (ret & CONTROL1_CLK_STABLE)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
enable |= CONTROL1_CLKENA;
|
|
|
|
bcm2835_mci_write(host,
|
|
|
|
SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET,
|
|
|
|
enable);
|
|
|
|
|
|
|
|
mdelay(100);
|
|
|
|
|
|
|
|
bcm2835_mci_reset_emmc(host, CONTROL1_CMDRST,
|
|
|
|
CONTROL1_CMDRST);
|
|
|
|
bcm2835_mci_reset_emmc(host, CONTROL1_DATARST,
|
|
|
|
CONTROL1_DATARST);
|
|
|
|
|
|
|
|
host->clock = ios->clock;
|
|
|
|
}
|
|
|
|
dev_dbg(host->hw_dev, "IO settings: bus width=%d, frequency=%u Hz\n",
|
|
|
|
host->bus_width, host->clock);
|
|
|
|
}
|
|
|
|
|
|
|
|
int bcm2835_mci_reset(struct mci_host *mci, struct device_d *mci_dev)
|
|
|
|
{
|
|
|
|
struct bcm2835_mci_host *host;
|
|
|
|
u32 ret = 0;
|
|
|
|
u32 reset = CONTROL1_HOSTRST | CONTROL1_CMDRST | CONTROL1_DATARST;
|
|
|
|
u32 enable = 0;
|
|
|
|
u32 divider;
|
|
|
|
u32 divider_msb, divider_lsb;
|
|
|
|
|
|
|
|
host = to_bcm2835_host(mci);
|
|
|
|
divider = bcm2835_mci_get_clock_divider(host, MIN_FREQ);
|
|
|
|
divider_msb = divider & 0x300;
|
|
|
|
divider_msb = divider_msb >> CONTROL1_CLKLSB;
|
|
|
|
divider_lsb = divider & 0xFF;
|
|
|
|
|
|
|
|
enable = (divider_lsb << CONTROL1_CLKLSB);
|
|
|
|
enable |= (divider_msb << CONTROL1_CLKMSB);
|
|
|
|
enable |= CONTROL1_INTCLKENA | CONTROL1_TIMEOUT;
|
|
|
|
|
|
|
|
bcm2835_mci_reset_emmc(host, enable | reset, CONTROL1_HOSTRST);
|
|
|
|
|
|
|
|
bcm2835_mci_write(host,
|
|
|
|
SDHCI_HOST_CONTROL__POWER_CONTROL__BLOCK_GAP_CONTROL,
|
|
|
|
0x00);
|
|
|
|
bcm2835_mci_write(host, SDHCI_ACMD12_ERR__HOST_CONTROL2,
|
|
|
|
0x00);
|
|
|
|
bcm2835_mci_write(host,
|
|
|
|
SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET,
|
|
|
|
enable);
|
|
|
|
while (true) {
|
|
|
|
ret = bcm2835_mci_read(host,
|
|
|
|
SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET);
|
|
|
|
if (ret & CONTROL1_CLK_STABLE)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
enable |= CONTROL1_CLKENA;
|
|
|
|
bcm2835_mci_write(host,
|
|
|
|
SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET,
|
|
|
|
enable);
|
|
|
|
|
|
|
|
/*Delay atelast 74 clk cycles for card init*/
|
|
|
|
mdelay(100);
|
|
|
|
|
|
|
|
bcm2835_mci_write(host, SDHCI_INT_ENABLE,
|
|
|
|
0xFFFFFFFF);
|
|
|
|
bcm2835_mci_write(host, SDHCI_INT_STATUS,
|
|
|
|
0xFFFFFFFF);
|
|
|
|
|
|
|
|
/*Now write command 0 and see if we get response*/
|
|
|
|
bcm2835_mci_write(host, SDHCI_ARGUMENT, 0x0);
|
|
|
|
bcm2835_mci_write(host, SDHCI_TRANSFER_MODE__COMMAND, 0x0);
|
|
|
|
return bcm2835_mci_wait_command_done(host);
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 bcm2835_mci_get_emmc_clock(struct msg_get_clock_rate *clk_data)
|
|
|
|
{
|
|
|
|
u32 val;
|
|
|
|
struct bcm2835_mbox_regs *regs =
|
|
|
|
(struct bcm2835_mbox_regs *) BCM2835_MBOX_PHYSADDR;
|
|
|
|
|
|
|
|
/*Read out old msg*/
|
|
|
|
while (true) {
|
|
|
|
val = readl(®s->status);
|
|
|
|
if (val & BCM2835_MBOX_STATUS_RD_EMPTY)
|
|
|
|
break;
|
|
|
|
val = readl(®s->read);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*Check for ok to write*/
|
|
|
|
while (true) {
|
|
|
|
val = readl(®s->status);
|
|
|
|
if (!(val & BCM2835_MBOX_STATUS_WR_FULL))
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
val = BCM2835_MBOX_PROP_CHAN + ((u32) &clk_data->hdr);
|
|
|
|
writel(val, ®s->write);
|
|
|
|
|
|
|
|
while (true) {
|
|
|
|
/* Wait for the response */
|
|
|
|
while (true) {
|
|
|
|
val = readl(®s->status);
|
|
|
|
if (!(val & BCM2835_MBOX_STATUS_RD_EMPTY))
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Read the response */
|
|
|
|
val = readl(®s->read);
|
|
|
|
if ((val & 0x0F) == BCM2835_MBOX_PROP_CHAN)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if ((val & ~0x0F) == ((u32) &clk_data->hdr))
|
|
|
|
if (clk_data->get_clock_rate.tag_hdr.val_len
|
|
|
|
& BCM2835_MBOX_TAG_VAL_LEN_RESPONSE)
|
|
|
|
return 1;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bcm2835_mci_probe(struct device_d *hw_dev)
|
|
|
|
{
|
|
|
|
struct bcm2835_mci_host *host;
|
|
|
|
struct msg_get_clock_rate *clk_data;
|
|
|
|
|
|
|
|
host = xzalloc(sizeof(*host));
|
|
|
|
host->mci.send_cmd = bcm2835_mci_request;
|
|
|
|
host->mci.set_ios = bcm2835_mci_set_ios;
|
|
|
|
host->mci.init = bcm2835_mci_reset;
|
|
|
|
host->mci.hw_dev = hw_dev;
|
|
|
|
host->hw_dev = hw_dev;
|
|
|
|
|
|
|
|
/* Allocate a buffer thats 16 bytes aligned in memory
|
|
|
|
* Of the 32 bits address passed into the mbox 28 bits
|
|
|
|
* are the address of the buffer, lower 4 bits is channel
|
|
|
|
*/
|
|
|
|
clk_data = memalign(16, sizeof(struct msg_get_clock_rate));
|
|
|
|
memset(clk_data, 0, sizeof(struct msg_get_clock_rate));
|
|
|
|
clk_data->hdr.buf_size = sizeof(struct msg_get_clock_rate);
|
|
|
|
clk_data->get_clock_rate.tag_hdr.tag = BCM2835_MBOX_TAG_GET_CLOCK_RATE;
|
|
|
|
clk_data->get_clock_rate.tag_hdr.val_buf_size =
|
|
|
|
sizeof(clk_data->get_clock_rate.body);
|
|
|
|
clk_data->get_clock_rate.tag_hdr.val_len =
|
|
|
|
sizeof(clk_data->get_clock_rate.body.req);
|
|
|
|
clk_data->get_clock_rate.body.req.clock_id = BCM2835_MBOX_CLOCK_ID_EMMC;
|
|
|
|
|
|
|
|
if (!bcm2835_mci_get_emmc_clock(clk_data)) {
|
|
|
|
dev_warn(host->hw_dev,
|
|
|
|
"Failed getting emmc clock, lets go anyway with 50MHz\n");
|
|
|
|
host->max_clock = 50000000;
|
|
|
|
} else {
|
|
|
|
host->max_clock = clk_data->get_clock_rate.body.resp.rate_hz;
|
|
|
|
dev_info(host->hw_dev, "Got emmc clock at %d Hz\n",
|
|
|
|
host->max_clock);
|
|
|
|
}
|
|
|
|
|
|
|
|
host->regs = dev_request_mem_region(hw_dev, 0);
|
|
|
|
if (host->regs == NULL) {
|
|
|
|
dev_err(host->hw_dev, "Failed request mem region, aborting...\n");
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
2013-06-03 08:59:35 +00:00
|
|
|
host->mci.host_caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
|
|
|
|
MMC_CAP_MMC_HIGHSPEED;
|
2013-05-10 06:00:46 +00:00
|
|
|
|
|
|
|
host->mci.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
|
|
|
|
|
|
|
|
host->mci.f_min = MIN_FREQ;
|
|
|
|
host->mci.f_max = host->max_clock;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The Arasan has a bugette whereby it may lose the content of
|
|
|
|
* successive writes to registers that are within two SD-card clock
|
|
|
|
* cycles of each other (a clock domain crossing problem).
|
|
|
|
*
|
|
|
|
* 1/MIN_FREQ is (max) time per tick of eMMC clock.
|
|
|
|
* 2/MIN_FREQ is time for two ticks.
|
|
|
|
* Multiply by 1000000000 to get nS per two ticks.
|
|
|
|
* +1 for hack rounding.
|
|
|
|
*/
|
|
|
|
|
|
|
|
twoticks_delay = ((2 * 1000000000) / MIN_FREQ) + 1;
|
|
|
|
|
|
|
|
host->version = bcm2835_mci_read(
|
|
|
|
host, BCM2835_MCI_SLOTISR_VER);
|
|
|
|
host->version = (host->version >> 16) & 0xFF;
|
|
|
|
return mci_register(&host->mci);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct driver_d bcm2835_mci_driver = {
|
|
|
|
.name = "bcm2835_mci",
|
|
|
|
.probe = bcm2835_mci_probe,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int bcm2835_mci_add(void)
|
|
|
|
{
|
|
|
|
return platform_driver_register(&bcm2835_mci_driver);
|
|
|
|
}
|
|
|
|
coredevice_initcall(bcm2835_mci_add);
|