320 lines
7.4 KiB
C
320 lines
7.4 KiB
C
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/*
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* at25.c -- support most SPI EEPROMs, such as Atmel AT25 models
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*
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* Copyright (C) 2011 Hubert Feurstein <h.feurstein@gmail.com>
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*
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* based on linux driver by:
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* Copyright (C) 2006 David Brownell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <common.h>
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#include <init.h>
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#include <clock.h>
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#include <driver.h>
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#include <errno.h>
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#include <xfuncs.h>
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#include <malloc.h>
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#include <spi/spi.h>
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#include <spi/eeprom.h>
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/*
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* NOTE: this is an *EEPROM* driver. The vagaries of product naming
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* mean that some AT25 products are EEPROMs, and others are FLASH.
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* Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver,
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* not this one!
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*/
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struct at25_data {
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struct cdev cdev;
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struct spi_device *spi;
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struct spi_eeprom chip;
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unsigned addrlen;
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};
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#define to_at25_data(cdev) ((struct at25_data *)(cdev)->priv)
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#define AT25_WREN 0x06 /* latch the write enable */
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#define AT25_WRDI 0x04 /* reset the write enable */
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#define AT25_RDSR 0x05 /* read status register */
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#define AT25_WRSR 0x01 /* write status register */
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#define AT25_READ 0x03 /* read byte(s) */
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#define AT25_WRITE 0x02 /* write byte(s)/sector */
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#define AT25_SR_nRDY 0x01 /* nRDY = write-in-progress */
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#define AT25_SR_WEN 0x02 /* write enable (latched) */
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#define AT25_SR_BP0 0x04 /* BP for software writeprotect */
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#define AT25_SR_BP1 0x08
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#define AT25_SR_WPEN 0x80 /* writeprotect enable */
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#define EE_MAXADDRLEN 3 /* 24 bit addresses, up to 2 MBytes */
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/* Specs often allow 5 msec for a page write, sometimes 20 msec;
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* it's important to recover from write timeouts.
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*/
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#define EE_TIMEOUT (25 * MSECOND)
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#define DRIVERNAME "at25x"
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/*-------------------------------------------------------------------------*/
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#define io_limit PAGE_SIZE /* bytes */
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static ssize_t at25_ee_read(struct cdev *cdev,
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void *buf,
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size_t count,
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ulong offset,
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ulong flags)
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{
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u8 command[EE_MAXADDRLEN + 1];
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u8 *cp;
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ssize_t status;
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struct spi_transfer t[2];
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struct spi_message m;
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struct at25_data *at25 = to_at25_data(cdev);
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if (unlikely(offset >= at25->chip.size))
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return 0;
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if ((offset + count) > at25->chip.size)
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count = at25->chip.size - offset;
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if (unlikely(!count))
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return count;
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cp = command;
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*cp++ = AT25_READ;
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/* 8/16/24-bit address is written MSB first */
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switch (at25->addrlen) {
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default: /* case 3 */
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*cp++ = offset >> 16;
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case 2:
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*cp++ = offset >> 8;
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case 1:
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case 0: /* can't happen: for better codegen */
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*cp++ = offset >> 0;
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}
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spi_message_init(&m);
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memset(t, 0, sizeof t);
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t[0].tx_buf = command;
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t[0].len = at25->addrlen + 1;
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spi_message_add_tail(&t[0], &m);
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t[1].rx_buf = buf;
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t[1].len = count;
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spi_message_add_tail(&t[1], &m);
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/* Read it all at once.
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*
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* REVISIT that's potentially a problem with large chips, if
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* other devices on the bus need to be accessed regularly or
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* this chip is clocked very slowly
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*/
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status = spi_sync(at25->spi, &m);
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dev_dbg(at25->cdev.dev,
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"read %d bytes at %lu --> %d\n",
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count, offset, (int) status);
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return status ? status : count;
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}
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static ssize_t at25_ee_write(struct cdev *cdev,
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const void *buf,
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size_t count,
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ulong off,
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ulong flags)
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{
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ssize_t status = 0;
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unsigned written = 0;
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unsigned buf_size;
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u8 *bounce;
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struct at25_data *at25 = to_at25_data(cdev);
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if (unlikely(off >= at25->chip.size))
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return -EFBIG;
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if ((off + count) > at25->chip.size)
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count = at25->chip.size - off;
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if (unlikely(!count))
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return count;
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/* Temp buffer starts with command and address */
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buf_size = at25->chip.page_size;
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if (buf_size > io_limit)
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buf_size = io_limit;
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bounce = xmalloc(buf_size + at25->addrlen + 1);
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/* For write, rollover is within the page ... so we write at
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* most one page, then manually roll over to the next page.
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*/
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bounce[0] = AT25_WRITE;
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do {
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uint64_t start_time;
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unsigned segment;
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unsigned offset = (unsigned) off;
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u8 *cp = bounce + 1;
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int sr;
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*cp = AT25_WREN;
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status = spi_write(at25->spi, cp, 1);
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if (status < 0) {
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dev_dbg(at25->cdev.dev, "WREN --> %d\n",
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(int) status);
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break;
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}
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/* 8/16/24-bit address is written MSB first */
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switch (at25->addrlen) {
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default: /* case 3 */
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*cp++ = offset >> 16;
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case 2:
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*cp++ = offset >> 8;
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case 1:
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case 0: /* can't happen: for better codegen */
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*cp++ = offset >> 0;
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}
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/* Write as much of a page as we can */
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segment = buf_size - (offset % buf_size);
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if (segment > count)
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segment = count;
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memcpy(cp, buf, segment);
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status = spi_write(at25->spi, bounce,
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segment + at25->addrlen + 1);
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dev_dbg(at25->cdev.dev,
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"write %u bytes at %u --> %d\n",
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segment, offset, (int) status);
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if (status < 0)
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break;
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/* REVISIT this should detect (or prevent) failed writes
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* to readonly sections of the EEPROM...
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*/
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/* Wait for non-busy status */
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start_time = get_time_ns();
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do {
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sr = spi_w8r8(at25->spi, AT25_RDSR);
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if (sr < 0 || (sr & AT25_SR_nRDY)) {
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dev_dbg(at25->cdev.dev,
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"rdsr --> %d (%02x)\n", sr, sr);
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continue;
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}
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if (!(sr & AT25_SR_nRDY))
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break;
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} while (!is_timeout(start_time, EE_TIMEOUT));
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if ((sr < 0) || (sr & AT25_SR_nRDY)) {
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dev_err(at25->cdev.dev,
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"write %d bytes offset %d, "
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"timeout after %u msecs\n",
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segment, offset,
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(unsigned int)(get_time_ns() - start_time) /
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1000000);
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status = -ETIMEDOUT;
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break;
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}
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off += segment;
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buf += segment;
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count -= segment;
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written += segment;
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} while (count > 0);
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free(bounce);
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return written ? written : status;
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}
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static off_t at25_ee_lseek(struct cdev *cdev, off_t off)
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{
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return off;
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}
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static struct file_operations at25_fops = {
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.read = at25_ee_read,
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.write = at25_ee_write,
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.lseek = at25_ee_lseek,
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};
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static int at25_probe(struct device_d *dev)
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{
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int err, sr;
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int addrlen;
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struct at25_data *at25 = NULL;
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const struct spi_eeprom *chip;
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/* Chip description */
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chip = dev->platform_data;
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if (!chip) {
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dev_dbg(dev, "no chip description\n");
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err = -ENODEV;
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goto fail;
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}
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/* For now we only support 8/16/24 bit addressing */
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if (chip->flags & EE_ADDR1) {
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addrlen = 1;
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} else if (chip->flags & EE_ADDR2) {
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addrlen = 2;
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} else if (chip->flags & EE_ADDR3) {
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addrlen = 3;
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} else {
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dev_dbg(dev, "unsupported address type\n");
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err = -EINVAL;
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goto fail;
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}
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at25 = xzalloc(sizeof(*at25));
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at25->chip = *chip;
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at25->addrlen = addrlen;
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at25->spi = dev->type_data;
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at25->spi->mode = SPI_MODE_0;
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at25->spi->bits_per_word = 8;
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at25->cdev.ops = &at25_fops;
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at25->cdev.size = chip->size;
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at25->cdev.dev = dev;
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at25->cdev.name = at25->chip.name[0] ? at25->chip.name : DRIVERNAME;
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at25->cdev.priv = at25;
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/* Ping the chip ... the status register is pretty portable,
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* unlike probing manufacturer IDs. We do expect that system
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* firmware didn't write it in the past few milliseconds!
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*/
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sr = spi_w8r8(at25->spi, AT25_RDSR);
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if (sr < 0 || sr & AT25_SR_nRDY) {
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dev_dbg(dev, "rdsr --> %d (%02x)\n", sr, sr);
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err = -ENXIO;
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goto fail;
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}
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dev_dbg(dev, "%s probed\n", at25->cdev.name);
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devfs_create(&at25->cdev);
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return 0;
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fail:
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if (at25)
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free(at25);
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return err;
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}
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static struct driver_d at25_driver = {
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.name = DRIVERNAME,
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.probe = at25_probe,
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};
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static int at25_init(void)
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{
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register_driver(&at25_driver);
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return 0;
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}
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device_initcall(at25_init);
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