2009-06-23 14:23:37 +00:00
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/*------------------------------------------------------------------------
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. smc91111.c
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. This is a driver for SMSC's 91C111 single-chip Ethernet device.
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.
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. (C) Copyright 2002
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. Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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. Rolf Offermanns <rof@sysgo.de>
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.
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. Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
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. Developed by Simple Network Magic Corporation (SNMC)
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. Copyright (C) 1996 by Erik Stahlman (ES)
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.
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. This program is free software; you can redistribute it and/or modify
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. it under the terms of the GNU General Public License as published by
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. the Free Software Foundation; either version 2 of the License, or
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. (at your option) any later version.
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.
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. This program is distributed in the hope that it will be useful,
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. but WITHOUT ANY WARRANTY; without even the implied warranty of
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. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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. GNU General Public License for more details.
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.
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. You should have received a copy of the GNU General Public License
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. along with this program; if not, write to the Free Software
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. Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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.
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. Information contained in this file was obtained from the LAN91C111
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. manual from SMC. To get a copy, if you really want one, you can find
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. information under www.smsc.com.
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.
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.
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. "Features" of the SMC chip:
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. Integrated PHY/MAC for 10/100BaseT Operation
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. Supports internal and external MII
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. Integrated 8K packet memory
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. EEPROM interface for configuration
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.
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. Arguments:
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. io = for the base address
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. irq = for the IRQ
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.
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. author:
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. Erik Stahlman ( erik@vt.edu )
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. Daris A Nevil ( dnevil@snmc.com )
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.
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.
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. Hardware multicast code from Peter Cammaert ( pc@denkart.be )
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.
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. Sources:
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. o SMSC LAN91C111 databook (www.smsc.com)
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. o smc9194.c by Erik Stahlman
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. o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
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.
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. History:
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2009-12-15 08:11:09 +00:00
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. 06/19/03 Richard Woodruff Made barebox environment aware and added mac addr checks.
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2009-06-23 14:23:37 +00:00
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. 10/17/01 Marco Hasewinkel Modify for DNP/1110
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. 07/25/01 Woojung Huh Modify for ADS Bitsy
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. 04/25/01 Daris A Nevil Initial public release through SMSC
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. 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
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----------------------------------------------------------------------------*/
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#ifdef CONFIG_ENABLE_DEVICE_NOISE
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# define DEBUG
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#endif
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#include <common.h>
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#include <command.h>
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#include <net.h>
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2010-08-26 16:33:28 +00:00
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#include <miidev.h>
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2009-06-23 14:23:37 +00:00
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#include <malloc.h>
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#include <init.h>
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#include <xfuncs.h>
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#include <errno.h>
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#include <clock.h>
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#include <asm/io.h>
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/*---------------------------------------------------------------
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.
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. A description of the SMSC registers is probably in order here,
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. although for details, the SMC datasheet is invaluable.
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.
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. Basically, the chip has 4 banks of registers ( 0 to 3 ), which
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. are accessed by writing a number into the BANK_SELECT register
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. ( I also use a SMC_SELECT_BANK macro for this ).
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.
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. The banks are configured so that for most purposes, bank 2 is all
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. that is needed for simple run time tasks.
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-----------------------------------------------------------------------*/
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/*
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* Bank Select Register:
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* yyyy yyyy 0000 00xx
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* xx = bank number
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* yyyy yyyy = 0x33, for identification purposes.
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*/
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#define BANK_SELECT 14
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/* Transmit Control Register */
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/* BANK 0 */
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#define TCR_REG 0x0000 /* transmit control register */
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#define TCR_ENABLE 0x0001 /* When 1 we can transmit */
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#define TCR_LOOP 0x0002 /* Controls output pin LBK */
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#define TCR_FORCOL 0x0004 /* When 1 will force a collision */
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#define TCR_PAD_EN 0x0080 /* When 1 will pad tx frames < 64 bytes w/0 */
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#define TCR_NOCRC 0x0100 /* When 1 will not append CRC to tx frames */
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#define TCR_MON_CSN 0x0400 /* When 1 tx monitors carrier */
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#define TCR_FDUPLX 0x0800 /* When 1 enables full duplex operation */
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#define TCR_STP_SQET 0x1000 /* When 1 stops tx if Signal Quality Error */
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#define TCR_EPH_LOOP 0x2000 /* When 1 enables EPH block loopback */
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#define TCR_SWFDUP 0x8000 /* When 1 enables Switched Full Duplex mode */
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#define TCR_CLEAR 0 /* do NOTHING */
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/* the default settings for the TCR register : */
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/* QUESTION: do I want to enable padding of short packets ? */
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#define TCR_DEFAULT TCR_ENABLE
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/* EPH Status Register */
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/* BANK 0 */
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#define EPH_STATUS_REG 0x0002
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#define ES_TX_SUC 0x0001 /* Last TX was successful */
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#define ES_SNGL_COL 0x0002 /* Single collision detected for last tx */
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#define ES_MUL_COL 0x0004 /* Multiple collisions detected for last tx */
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#define ES_LTX_MULT 0x0008 /* Last tx was a multicast */
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#define ES_16COL 0x0010 /* 16 Collisions Reached */
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#define ES_SQET 0x0020 /* Signal Quality Error Test */
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#define ES_LTXBRD 0x0040 /* Last tx was a broadcast */
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#define ES_TXDEFR 0x0080 /* Transmit Deferred */
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#define ES_LATCOL 0x0200 /* Late collision detected on last tx */
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#define ES_LOSTCARR 0x0400 /* Lost Carrier Sense */
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#define ES_EXC_DEF 0x0800 /* Excessive Deferral */
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#define ES_CTR_ROL 0x1000 /* Counter Roll Over indication */
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#define ES_LINK_OK 0x4000 /* Driven by inverted value of nLNK pin */
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#define ES_TXUNRN 0x8000 /* Tx Underrun */
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/* Receive Control Register */
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/* BANK 0 */
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#define RCR_REG 0x0004
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#define RCR_RX_ABORT 0x0001 /* Set if a rx frame was aborted */
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#define RCR_PRMS 0x0002 /* Enable promiscuous mode */
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#define RCR_ALMUL 0x0004 /* When set accepts all multicast frames */
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#define RCR_RXEN 0x0100 /* IFF this is set, we can receive packets */
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#define RCR_STRIP_CRC 0x0200 /* When set strips CRC from rx packets */
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#define RCR_ABORT_ENB 0x0200 /* When set will abort rx on collision */
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#define RCR_FILT_CAR 0x0400 /* When set filters leading 12 bit s of carrier */
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#define RCR_SOFTRST 0x8000 /* resets the chip */
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/* the normal settings for the RCR register : */
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#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
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#define RCR_CLEAR 0x0 /* set it to a base state */
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/* Counter Register */
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/* BANK 0 */
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#define COUNTER_REG 0x0006
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/* Memory Information Register */
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/* BANK 0 */
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#define MIR_REG 0x0008
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/* Receive/Phy Control Register */
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/* BANK 0 */
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#define RPC_REG 0x000A
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#define RPC_SPEED 0x2000 /* When 1 PHY is in 100Mbps mode. */
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#define RPC_DPLX 0x1000 /* When 1 PHY is in Full-Duplex Mode */
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#define RPC_ANEG 0x0800 /* When 1 PHY is in Auto-Negotiate Mode */
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#define RPC_LSXA_SHFT 5 /* Bits to shift LS2A,LS1A,LS0A to lsb */
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#define RPC_LSXB_SHFT 2 /* Bits to get LS2B,LS1B,LS0B to lsb */
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#define RPC_LED_100_10 (0x00) /* LED = 100Mbps OR's with 10Mbps link detect */
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#define RPC_LED_RES (0x01) /* LED = Reserved */
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#define RPC_LED_10 (0x02) /* LED = 10Mbps link detect */
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#define RPC_LED_FD (0x03) /* LED = Full Duplex Mode */
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#define RPC_LED_TX_RX (0x04) /* LED = TX or RX packet occurred */
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#define RPC_LED_100 (0x05) /* LED = 100Mbps link dectect */
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#define RPC_LED_TX (0x06) /* LED = TX packet occurred */
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#define RPC_LED_RX (0x07) /* LED = RX packet occurred */
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/* SMSC reference design: LEDa --> green, LEDb --> yellow */
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#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \
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| (RPC_LED_100_10 << RPC_LSXA_SHFT) \
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| (RPC_LED_TX_RX << RPC_LSXB_SHFT) )
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/* Bank 0 0x000C is reserved */
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/* Bank Select Register */
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/* All Banks */
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#define BSR_REG 0x000E
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/* Configuration Reg */
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/* BANK 1 */
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#define CONFIG_REG 0x0000
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#define CONFIG_EXT_PHY 0x0200 /* 1=external MII, 0=internal Phy */
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#define CONFIG_GPCNTRL 0x0400 /* Inverse value drives pin nCNTRL */
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#define CONFIG_NO_WAIT 0x1000 /* When 1 no extra wait states on ISA bus */
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#define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */
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/* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */
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#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
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/* Base Address Register */
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/* BANK 1 */
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#define BASE_REG 0x0002
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/* Individual Address Registers */
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/* BANK 1 */
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#define ADDR0_REG 0x0004
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#define ADDR1_REG 0x0006
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#define ADDR2_REG 0x0008
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/* General Purpose Register */
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/* BANK 1 */
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#define GP_REG 0x000A
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/* Control Register */
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/* BANK 1 */
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#define CTL_REG 0x000C
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#define CTL_RCV_BAD 0x4000 /* When 1 bad CRC packets are received */
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#define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */
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#define CTL_LE_ENABLE 0x0080 /* When 1 enables Link Error interrupt */
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#define CTL_CR_ENABLE 0x0040 /* When 1 enables Counter Rollover interrupt */
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#define CTL_TE_ENABLE 0x0020 /* When 1 enables Transmit Error interrupt */
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#define CTL_EEPROM_SELECT 0x0004 /* Controls EEPROM reload & store */
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#define CTL_RELOAD 0x0002 /* When set reads EEPROM into registers */
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#define CTL_STORE 0x0001 /* When set stores registers into EEPROM */
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#define CTL_DEFAULT (0x1A10) /* Autorelease enabled*/
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/* MMU Command Register */
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/* BANK 2 */
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#define MMU_CMD_REG 0x0000
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#define MC_BUSY 1 /* When 1 the last release has not completed */
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#define MC_NOP (0<<5) /* No Op */
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#define MC_ALLOC (1<<5) /* OR with number of 256 byte packets */
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#define MC_RESET (2<<5) /* Reset MMU to initial state */
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#define MC_REMOVE (3<<5) /* Remove the current rx packet */
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#define MC_RELEASE (4<<5) /* Remove and release the current rx packet */
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#define MC_FREEPKT (5<<5) /* Release packet in PNR register */
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#define MC_ENQUEUE (6<<5) /* Enqueue the packet for transmit */
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#define MC_RSTTXFIFO (7<<5) /* Reset the TX FIFOs */
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/* Packet Number Register */
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/* BANK 2 */
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#define PN_REG 0x0002
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/* Allocation Result Register */
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/* BANK 2 */
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#define AR_REG 0x0003
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#define AR_FAILED 0x80 /* Alocation Failed */
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/* RX FIFO Ports Register */
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/* BANK 2 */
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#define RXFIFO_REG 0x0004 /* Must be read as a unsigned short*/
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#define RXFIFO_REMPTY 0x8000 /* RX FIFO Empty */
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/* TX FIFO Ports Register */
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/* BANK 2 */
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#define TXFIFO_REG RXFIFO_REG /* Must be read as a unsigned short*/
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#define TXFIFO_TEMPTY 0x80 /* TX FIFO Empty */
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/* Pointer Register */
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/* BANK 2 */
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#define PTR_REG 0x0006
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#define PTR_RCV 0x8000 /* 1=Receive area, 0=Transmit area */
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#define PTR_AUTOINC 0x4000 /* Auto increment the pointer on each access */
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#define PTR_READ 0x2000 /* When 1 the operation is a read */
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#define PTR_NOTEMPTY 0x0800 /* When 1 _do not_ write fifo DATA REG */
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/* Data Register */
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/* BANK 2 */
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#define SMC91111_DATA_REG 0x0008
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/* Interrupt Status/Acknowledge Register */
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/* BANK 2 */
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#define SMC91111_INT_REG 0x000C
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/* Interrupt Mask Register */
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/* BANK 2 */
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#define IM_REG 0x000D
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#define IM_MDINT 0x80 /* PHY MI Register 18 Interrupt */
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#define IM_ERCV_INT 0x40 /* Early Receive Interrupt */
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#define IM_EPH_INT 0x20 /* Set by Etheret Protocol Handler section */
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#define IM_RX_OVRN_INT 0x10 /* Set by Receiver Overruns */
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#define IM_ALLOC_INT 0x08 /* Set when allocation request is completed */
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#define IM_TX_EMPTY_INT 0x04 /* Set if the TX FIFO goes empty */
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#define IM_TX_INT 0x02 /* Transmit Interrrupt */
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#define IM_RCV_INT 0x01 /* Receive Interrupt */
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/* Multicast Table Registers */
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/* BANK 3 */
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#define MCAST_REG1 0x0000
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#define MCAST_REG2 0x0002
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#define MCAST_REG3 0x0004
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#define MCAST_REG4 0x0006
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/* Management Interface Register (MII) */
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/* BANK 3 */
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#define MII_REG 0x0008
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#define MII_MSK_CRS100 0x4000 /* Disables CRS100 detection during tx half dup */
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#define MII_MDOE 0x0008 /* MII Output Enable */
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#define MII_MCLK 0x0004 /* MII Clock, pin MDCLK */
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#define MII_MDI 0x0002 /* MII Input, pin MDI */
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#define MII_MDO 0x0001 /* MII Output, pin MDO */
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/* Revision Register */
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/* BANK 3 */
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#define REV_REG 0x000A /* ( hi: chip id low: rev # ) */
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/* Early RCV Register */
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/* BANK 3 */
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/* this is NOT on SMC9192 */
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#define ERCV_REG 0x000C
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#define ERCV_RCV_DISCRD 0x0080 /* When 1 discards a packet being received */
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#define ERCV_THRESHOLD 0x001F /* ERCV Threshold Mask */
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/* External Register */
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/* BANK 7 */
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#define EXT_REG 0x0000
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#define CHIP_9192 3
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#define CHIP_9194 4
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#define CHIP_9195 5
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#define CHIP_9196 6
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#define CHIP_91100 7
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#define CHIP_91100FD 8
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#define CHIP_91111FD 9
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/* Transmit status bits*/
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#define TS_SUCCESS 0x0001
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#define TS_LOSTCAR 0x0400
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#define TS_LATCOL 0x0200
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#define TS_16COL 0x0010
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|
|
|
/* Receive status bits */
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|
|
|
#define RS_ALGNERR 0x8000
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|
#define RS_BRODCAST 0x4000
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#define RS_BADCRC 0x2000
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|
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#define RS_ODDFRAME 0x1000 /* bug: the LAN91C111 never sets this on receive */
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#define RS_TOOLONG 0x0800
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#define RS_TOOSHORT 0x0400
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#define RS_MULTICAST 0x0001
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#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
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/* PHY Register Addresses (LAN91C111 Internal PHY) */
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/* PHY Control Register */
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#define PHY_CNTL_REG 0x00
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#define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */
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#define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */
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#define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */
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#define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */
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#define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */
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#define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */
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#define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */
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#define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */
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#define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */
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|
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/* PHY Status Register */
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#define PHY_STAT_REG 0x01
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#define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */
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#define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */
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#define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */
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#define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */
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#define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */
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|
#define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */
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#define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */
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#define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */
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#define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */
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#define PHY_STAT_LINK 0x0004 /* 1=valid link */
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#define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */
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#define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */
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|
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/* PHY Identifier Registers */
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|
#define PHY_ID1_REG 0x02 /* PHY Identifier 1 */
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#define PHY_ID2_REG 0x03 /* PHY Identifier 2 */
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/* PHY Auto-Negotiation Advertisement Register */
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#define PHY_AD_REG 0x04
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#define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */
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#define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */
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|
#define PHY_AD_RF 0x2000 /* 1=advertise remote fault */
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|
#define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */
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#define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */
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|
#define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */
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|
#define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */
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|
#define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */
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|
|
#define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */
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|
|
/* PHY Auto-negotiation Remote End Capability Register */
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|
|
#define PHY_RMT_REG 0x05
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|
|
/* Uses same bit definitions as PHY_AD_REG */
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|
|
/* PHY Configuration Register 1 */
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|
|
#define PHY_CFG1_REG 0x10
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#define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */
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|
#define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */
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|
|
#define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */
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|
|
#define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */
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|
|
#define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */
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|
|
#define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */
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|
|
#define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */
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|
#define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */
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|
|
#define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */
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|
|
#define PHY_CFG1_TLVL_MASK 0x003C
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|
#define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */
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|
|
/* PHY Configuration Register 2 */
|
|
|
|
#define PHY_CFG2_REG 0x11
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|
|
#define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */
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|
|
#define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */
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|
|
#define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */
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|
|
#define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */
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|
|
/* PHY Status Output (and Interrupt status) Register */
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|
|
#define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */
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|
|
#define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */
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|
|
#define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */
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|
|
#define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */
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|
|
#define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */
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|
#define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */
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|
#define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */
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|
|
#define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */
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|
|
#define PHY_INT_JAB 0x0100 /* 1=Jabber detected */
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|
|
#define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */
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|
|
|
#define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */
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|
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|
|
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|
|
/* PHY Interrupt/Status Mask Register */
|
|
|
|
#define PHY_MASK_REG 0x13 /* Interrupt Mask */
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|
|
/* Uses the same bit definitions as PHY_INT_REG */
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|
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|
|
#define SMC_DEBUG 0
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|
|
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|
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|
|
/* Autonegotiation timeout in seconds */
|
|
|
|
#define CONFIG_SMC_AUTONEG_TIMEOUT 10
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|
|
|
|
|
|
|
/*
|
|
|
|
. Wait time for memory to be free. This probably shouldn't be
|
|
|
|
. tuned that much, as waiting for this means nothing else happens
|
|
|
|
. in the system
|
|
|
|
*/
|
|
|
|
#define MEMORY_WAIT_TIME 16
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|
|
|
|
|
|
|
struct accessors {
|
2010-11-18 13:29:31 +00:00
|
|
|
void (*ob)(unsigned, void __iomem *);
|
|
|
|
void (*ow)(unsigned, void __iomem *);
|
|
|
|
void (*ol)(unsigned long, void __iomem *);
|
|
|
|
void (*osl)(void __iomem *, const void *, int);
|
|
|
|
unsigned (*ib)(void __iomem *);
|
|
|
|
unsigned (*iw)(void __iomem *);
|
|
|
|
unsigned long (*il)(void __iomem *);
|
|
|
|
void (*isl)(void __iomem *, void*, int);
|
2009-06-23 14:23:37 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
struct smc91c111_priv {
|
2010-08-26 16:33:28 +00:00
|
|
|
struct mii_device miidev;
|
2009-06-23 14:23:37 +00:00
|
|
|
struct accessors a;
|
2010-11-18 13:29:31 +00:00
|
|
|
void __iomem *base;
|
2009-06-23 14:23:37 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
#if (SMC_DEBUG > 2 )
|
|
|
|
#define PRINTK3(args...) printf(args)
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|
|
|
#else
|
|
|
|
#define PRINTK3(args...)
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#if SMC_DEBUG > 1
|
|
|
|
#define PRINTK2(args...) printf(args)
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|
|
|
#else
|
|
|
|
#define PRINTK2(args...)
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef SMC_DEBUG
|
|
|
|
#define PRINTK(args...) printf(args)
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|
|
|
#else
|
|
|
|
#define PRINTK(args...)
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
|
|
#define SMC_DEV_NAME "SMC91111"
|
|
|
|
#define SMC_ALLOC_MAX_TRY 5
|
|
|
|
#define SMC_TX_TIMEOUT 30
|
|
|
|
|
2009-07-09 13:22:43 +00:00
|
|
|
#define SMC_PHY_CLOCK_DELAY 100
|
2009-06-23 14:23:37 +00:00
|
|
|
|
|
|
|
#define ETH_ZLEN 60
|
|
|
|
|
2010-11-18 13:29:31 +00:00
|
|
|
static void a_outb(unsigned value, void __iomem *offset)
|
2009-06-23 14:23:37 +00:00
|
|
|
{
|
|
|
|
writeb(value, offset);
|
|
|
|
}
|
|
|
|
|
2010-11-18 13:29:31 +00:00
|
|
|
static void a_outw(unsigned value, void __iomem *offset)
|
2009-06-23 14:23:37 +00:00
|
|
|
{
|
|
|
|
writew(value, offset);
|
|
|
|
}
|
|
|
|
|
2010-11-18 13:29:31 +00:00
|
|
|
static void a_outl(unsigned long value, void __iomem *offset)
|
2009-06-23 14:23:37 +00:00
|
|
|
{
|
|
|
|
writel(value, offset);
|
|
|
|
}
|
|
|
|
|
2010-11-18 13:29:31 +00:00
|
|
|
static void a_outsl(void __iomem *offset, const void *data, int count)
|
2009-06-23 14:23:37 +00:00
|
|
|
{
|
2010-11-18 13:29:31 +00:00
|
|
|
writesl(offset, data, count);
|
2009-06-23 14:23:37 +00:00
|
|
|
}
|
|
|
|
|
2010-11-18 13:29:31 +00:00
|
|
|
static unsigned a_inb(void __iomem *offset)
|
2009-06-23 14:23:37 +00:00
|
|
|
{
|
|
|
|
return readb(offset);
|
|
|
|
}
|
|
|
|
|
2010-11-18 13:29:31 +00:00
|
|
|
static unsigned a_inw(void __iomem *offset)
|
2009-06-23 14:23:37 +00:00
|
|
|
{
|
|
|
|
return readw(offset);
|
|
|
|
}
|
|
|
|
|
2010-11-18 13:29:31 +00:00
|
|
|
static unsigned long a_inl(void __iomem *offset)
|
2009-06-23 14:23:37 +00:00
|
|
|
{
|
|
|
|
return readl(offset);
|
|
|
|
}
|
|
|
|
|
2010-11-18 13:29:31 +00:00
|
|
|
static inline void a_insl(void __iomem *offset, void *data, int count)
|
2009-06-23 14:23:37 +00:00
|
|
|
{
|
2010-11-18 13:29:31 +00:00
|
|
|
readsl(offset, data, count);
|
2009-06-23 14:23:37 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* access happens via a 32 bit bus */
|
|
|
|
static const struct accessors access_via_32bit = {
|
|
|
|
.ob = a_outb,
|
|
|
|
.ow = a_outw,
|
|
|
|
.ol = a_outl,
|
|
|
|
.osl = a_outsl,
|
|
|
|
.ib = a_inb,
|
|
|
|
.iw = a_inw,
|
|
|
|
.il = a_inl,
|
|
|
|
.isl = a_insl,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* ------------------------------------------------------------------------ */
|
|
|
|
|
|
|
|
static inline void SMC_outb(struct smc91c111_priv *p, unsigned value,
|
|
|
|
unsigned offset)
|
|
|
|
{
|
|
|
|
(p->a.ob)(value, p->base + offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void SMC_outw(struct smc91c111_priv *p, unsigned value,
|
|
|
|
unsigned offset)
|
|
|
|
{
|
|
|
|
(p->a.ow)(value, p->base + offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void SMC_outl(struct smc91c111_priv *p, unsigned long value,
|
|
|
|
unsigned offset)
|
|
|
|
{
|
|
|
|
(p->a.ol)(value, p->base + offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void SMC_outsl(struct smc91c111_priv *p, unsigned offset,
|
|
|
|
const void *data, int count)
|
|
|
|
{
|
|
|
|
(p->a.osl)(p->base + offset, data, count);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned SMC_inb(struct smc91c111_priv *p, unsigned offset)
|
|
|
|
{
|
|
|
|
return (p->a.ib)(p->base + offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned SMC_inw(struct smc91c111_priv *p, unsigned offset)
|
|
|
|
{
|
|
|
|
return (p->a.iw)(p->base + offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned long SMC_inl(struct smc91c111_priv *p, unsigned offset)
|
|
|
|
{
|
|
|
|
return (p->a.il)(p->base + offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void SMC_insl(struct smc91c111_priv *p, unsigned offset,
|
|
|
|
void *data, int count)
|
|
|
|
{
|
|
|
|
(p->a.isl)(p->base + offset, data, count);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void SMC_SELECT_BANK(struct smc91c111_priv *p, int bank)
|
|
|
|
{
|
|
|
|
SMC_outw(p, bank, BANK_SELECT);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* note: timeout in seconds */
|
|
|
|
static int poll4int(struct smc91c111_priv *priv, unsigned char mask,
|
|
|
|
int timeout)
|
|
|
|
{
|
|
|
|
unsigned old_bank = SMC_inw(priv, BSR_REG);
|
|
|
|
int i;
|
|
|
|
|
|
|
|
timeout *= 1000;
|
|
|
|
SMC_SELECT_BANK(priv, 2);
|
|
|
|
|
|
|
|
for (i = 0; i < timeout; i++) {
|
|
|
|
if (SMC_inw(priv, SMC91111_INT_REG) & mask) {
|
|
|
|
SMC_SELECT_BANK(priv, old_bank);
|
|
|
|
return 0; /* return happy */
|
|
|
|
}
|
|
|
|
mdelay(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
SMC_SELECT_BANK(priv, old_bank);
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void smc_wait_mmu_release_complete(struct smc91c111_priv *priv)
|
|
|
|
{
|
|
|
|
int count = 0;
|
|
|
|
|
|
|
|
/* assume bank 2 selected */
|
|
|
|
while (SMC_inw(priv, MMU_CMD_REG) & MC_BUSY) {
|
|
|
|
udelay(1); /* Wait until not busy */
|
|
|
|
if (++count > 200)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-08-26 16:33:28 +00:00
|
|
|
static int smc91c111_phy_write(struct mii_device *mdev, int phyaddr,
|
|
|
|
int phyreg, int phydata)
|
2009-06-23 14:23:37 +00:00
|
|
|
{
|
|
|
|
struct eth_device *edev = mdev->edev;
|
|
|
|
struct smc91c111_priv *priv = (struct smc91c111_priv *)edev->priv;
|
|
|
|
int oldBank;
|
|
|
|
int i;
|
|
|
|
unsigned mask;
|
|
|
|
unsigned short mii_reg;
|
|
|
|
unsigned char bits[65];
|
|
|
|
int clk_idx = 0;
|
|
|
|
|
|
|
|
/* 32 consecutive ones on MDO to establish sync */
|
|
|
|
for (i = 0; i < 32; ++i)
|
|
|
|
bits[clk_idx++] = MII_MDOE | MII_MDO;
|
|
|
|
|
|
|
|
/* Start code <01> */
|
|
|
|
bits[clk_idx++] = MII_MDOE;
|
|
|
|
bits[clk_idx++] = MII_MDOE | MII_MDO;
|
|
|
|
|
|
|
|
/* Write command <01> */
|
|
|
|
bits[clk_idx++] = MII_MDOE;
|
|
|
|
bits[clk_idx++] = MII_MDOE | MII_MDO;
|
|
|
|
|
|
|
|
/* Output the PHY address, msb first */
|
|
|
|
mask = 0x10;
|
|
|
|
for (i = 0; i < 5; ++i) {
|
|
|
|
if (phyaddr & mask)
|
|
|
|
bits[clk_idx++] = MII_MDOE | MII_MDO;
|
|
|
|
else
|
|
|
|
bits[clk_idx++] = MII_MDOE;
|
|
|
|
|
|
|
|
/* Shift to next lowest bit */
|
|
|
|
mask >>= 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Output the phy register number, msb first */
|
|
|
|
mask = 0x10;
|
|
|
|
for (i = 0; i < 5; ++i) {
|
|
|
|
if (phyreg & mask)
|
|
|
|
bits[clk_idx++] = MII_MDOE | MII_MDO;
|
|
|
|
else
|
|
|
|
bits[clk_idx++] = MII_MDOE;
|
|
|
|
|
|
|
|
/* Shift to next lowest bit */
|
|
|
|
mask >>= 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Tristate and turnaround (2 bit times) */
|
|
|
|
bits[clk_idx++] = 0;
|
|
|
|
bits[clk_idx++] = 0;
|
|
|
|
|
|
|
|
/* Write out 16 bits of data, msb first */
|
|
|
|
mask = 0x8000;
|
|
|
|
for (i = 0; i < 16; ++i) {
|
|
|
|
if (phydata & mask)
|
|
|
|
bits[clk_idx++] = MII_MDOE | MII_MDO;
|
|
|
|
else
|
|
|
|
bits[clk_idx++] = MII_MDOE;
|
|
|
|
|
|
|
|
/* Shift to next lowest bit */
|
|
|
|
mask >>= 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Final clock bit (tristate) */
|
|
|
|
bits[clk_idx++] = 0;
|
|
|
|
|
|
|
|
/* Save the current bank */
|
|
|
|
oldBank = SMC_inw(priv, BANK_SELECT);
|
|
|
|
|
|
|
|
/* Select bank 3 */
|
|
|
|
SMC_SELECT_BANK(priv, 3);
|
|
|
|
|
|
|
|
/* Get the current MII register value */
|
|
|
|
mii_reg = SMC_inw(priv, MII_REG);
|
|
|
|
|
|
|
|
/* Turn off all MII Interface bits */
|
|
|
|
mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
|
|
|
|
|
|
|
|
/* Clock all cycles */
|
|
|
|
for (i = 0; i < sizeof bits; ++i) {
|
|
|
|
/* Clock Low - output data */
|
|
|
|
SMC_outw(priv, mii_reg | bits[i], MII_REG);
|
|
|
|
udelay(SMC_PHY_CLOCK_DELAY);
|
|
|
|
|
|
|
|
/* Clock Hi - input data */
|
|
|
|
SMC_outw(priv, mii_reg | bits[i] | MII_MCLK, MII_REG);
|
|
|
|
udelay (SMC_PHY_CLOCK_DELAY);
|
|
|
|
bits[i] |= SMC_inw(priv, MII_REG) & MII_MDI;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Return to idle state */
|
|
|
|
/* Set clock to low, data to low, and output tristated */
|
|
|
|
SMC_outw(priv, mii_reg, MII_REG);
|
|
|
|
udelay(SMC_PHY_CLOCK_DELAY);
|
|
|
|
|
|
|
|
/* Restore original bank select */
|
|
|
|
SMC_SELECT_BANK(priv, oldBank);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-08-26 16:33:28 +00:00
|
|
|
static int smc91c111_phy_read(struct mii_device *mdev, int phyaddr, int phyreg)
|
2009-06-23 14:23:37 +00:00
|
|
|
{
|
|
|
|
struct eth_device *edev = mdev->edev;
|
|
|
|
struct smc91c111_priv *priv = (struct smc91c111_priv *)edev->priv;
|
|
|
|
int oldBank;
|
|
|
|
int i;
|
|
|
|
unsigned char mask;
|
|
|
|
unsigned short mii_reg;
|
|
|
|
unsigned char bits[64];
|
|
|
|
int clk_idx = 0;
|
|
|
|
int input_idx;
|
|
|
|
uint16_t phydata;
|
|
|
|
|
|
|
|
/* 32 consecutive ones on MDO to establish sync */
|
|
|
|
for (i = 0; i < 32; ++i)
|
|
|
|
bits[clk_idx++] = MII_MDOE | MII_MDO;
|
|
|
|
|
|
|
|
/* Start code <01> */
|
|
|
|
bits[clk_idx++] = MII_MDOE;
|
|
|
|
bits[clk_idx++] = MII_MDOE | MII_MDO;
|
|
|
|
|
|
|
|
/* Read command <10> */
|
|
|
|
bits[clk_idx++] = MII_MDOE | MII_MDO;
|
|
|
|
bits[clk_idx++] = MII_MDOE;
|
|
|
|
|
|
|
|
/* Output the PHY address, msb first */
|
|
|
|
mask = 0x10;
|
|
|
|
for (i = 0; i < 5; ++i) {
|
|
|
|
if (phyaddr & mask)
|
|
|
|
bits[clk_idx++] = MII_MDOE | MII_MDO;
|
|
|
|
else
|
|
|
|
bits[clk_idx++] = MII_MDOE;
|
|
|
|
|
|
|
|
/* Shift to next lowest bit */
|
|
|
|
mask >>= 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Output the phy register number, msb first */
|
|
|
|
mask = 0x10;
|
|
|
|
for (i = 0; i < 5; ++i) {
|
|
|
|
if (phyreg & mask)
|
|
|
|
bits[clk_idx++] = MII_MDOE | MII_MDO;
|
|
|
|
else
|
|
|
|
bits[clk_idx++] = MII_MDOE;
|
|
|
|
|
|
|
|
/* Shift to next lowest bit */
|
|
|
|
mask >>= 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Tristate and turnaround (2 bit times) */
|
|
|
|
bits[clk_idx++] = 0;
|
|
|
|
/*bits[clk_idx++] = 0; */
|
|
|
|
|
|
|
|
/* Input starts at this bit time */
|
|
|
|
input_idx = clk_idx;
|
|
|
|
|
|
|
|
/* Will input 16 bits */
|
|
|
|
for (i = 0; i < 16; ++i)
|
|
|
|
bits[clk_idx++] = 0;
|
|
|
|
|
|
|
|
/* Final clock bit */
|
|
|
|
bits[clk_idx++] = 0;
|
|
|
|
|
|
|
|
/* Save the current bank */
|
|
|
|
oldBank = SMC_inw(priv, BANK_SELECT);
|
|
|
|
|
|
|
|
/* Select bank 3 */
|
|
|
|
SMC_SELECT_BANK(priv, 3);
|
|
|
|
|
|
|
|
/* Get the current MII register value */
|
|
|
|
mii_reg = SMC_inw(priv, MII_REG);
|
|
|
|
|
|
|
|
/* Turn off all MII Interface bits */
|
|
|
|
mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
|
|
|
|
|
|
|
|
/* Clock all 64 cycles */
|
|
|
|
for (i = 0; i < sizeof bits; ++i) {
|
|
|
|
/* Clock Low - output data */
|
|
|
|
SMC_outw(priv, mii_reg | bits[i], MII_REG);
|
|
|
|
udelay(SMC_PHY_CLOCK_DELAY);
|
|
|
|
|
|
|
|
/* Clock Hi - input data */
|
|
|
|
SMC_outw(priv, mii_reg | bits[i] | MII_MCLK, MII_REG);
|
|
|
|
udelay(SMC_PHY_CLOCK_DELAY);
|
|
|
|
bits[i] |= SMC_inw(priv, MII_REG) & MII_MDI;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Return to idle state */
|
|
|
|
/* Set clock to low, data to low, and output tristated */
|
|
|
|
SMC_outw(priv, mii_reg, MII_REG);
|
|
|
|
udelay(SMC_PHY_CLOCK_DELAY);
|
|
|
|
|
|
|
|
/* Restore original bank select */
|
|
|
|
SMC_SELECT_BANK(priv, oldBank);
|
|
|
|
|
|
|
|
/* Recover input data */
|
|
|
|
phydata = 0;
|
|
|
|
for (i = 0; i < 16; ++i) {
|
|
|
|
phydata <<= 1;
|
|
|
|
if (bits[input_idx++] & MII_MDI)
|
|
|
|
phydata |= 0x0001;
|
|
|
|
}
|
|
|
|
|
2010-08-26 16:33:28 +00:00
|
|
|
return phydata;
|
2009-06-23 14:23:37 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void smc91c111_reset(struct eth_device *edev)
|
|
|
|
{
|
|
|
|
struct smc91c111_priv *priv = (struct smc91c111_priv *)edev->priv;
|
|
|
|
|
|
|
|
/* This resets the registers mostly to defaults, but doesn't
|
|
|
|
affect EEPROM. That seems unnecessary */
|
|
|
|
SMC_SELECT_BANK(priv, 0);
|
|
|
|
SMC_outw(priv, RCR_SOFTRST, RCR_REG);
|
|
|
|
|
|
|
|
/* Setup the Configuration Register */
|
|
|
|
/* This is necessary because the CONFIG_REG is not affected */
|
|
|
|
/* by a soft reset */
|
|
|
|
|
|
|
|
SMC_SELECT_BANK(priv, 1);
|
|
|
|
SMC_outw(priv, CONFIG_DEFAULT, CONFIG_REG);
|
|
|
|
|
|
|
|
/* Release from possible power-down state */
|
|
|
|
/* Configuration register is not affected by Soft Reset */
|
|
|
|
SMC_outw(priv, SMC_inw(priv, CONFIG_REG) | CONFIG_EPH_POWER_EN,
|
|
|
|
CONFIG_REG);
|
|
|
|
|
|
|
|
SMC_SELECT_BANK(priv, 0);
|
|
|
|
|
|
|
|
/* this should pause enough for the chip to be happy */
|
|
|
|
udelay (10);
|
|
|
|
|
|
|
|
/* Disable transmit and receive functionality */
|
|
|
|
SMC_outw(priv, RCR_CLEAR, RCR_REG);
|
|
|
|
SMC_outw(priv, TCR_CLEAR, TCR_REG);
|
|
|
|
|
|
|
|
/* set the control register */
|
|
|
|
SMC_SELECT_BANK(priv, 1);
|
|
|
|
SMC_outw(priv, CTL_DEFAULT, CTL_REG);
|
|
|
|
|
|
|
|
/* Reset the MMU */
|
|
|
|
SMC_SELECT_BANK(priv, 2);
|
|
|
|
smc_wait_mmu_release_complete(priv);
|
|
|
|
SMC_outw(priv, MC_RESET, MMU_CMD_REG);
|
|
|
|
|
|
|
|
while (SMC_inw(priv, MMU_CMD_REG) & MC_BUSY)
|
|
|
|
udelay(1); /* Wait until not busy */
|
|
|
|
|
|
|
|
/* Note: It doesn't seem that waiting for the MMU busy is needed here,
|
|
|
|
but this is a place where future chipsets _COULD_ break. Be wary
|
|
|
|
of issuing another MMU command right after this */
|
|
|
|
|
|
|
|
/* Disable all interrupts */
|
|
|
|
SMC_outb(priv, 0, IM_REG);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void smc91c111_enable(struct eth_device *edev)
|
|
|
|
{
|
|
|
|
struct smc91c111_priv *priv = (struct smc91c111_priv *)edev->priv;
|
|
|
|
|
|
|
|
SMC_SELECT_BANK(priv, 0);
|
|
|
|
/* see the header file for options in TCR/RCR DEFAULT*/
|
|
|
|
SMC_outw(priv, TCR_DEFAULT, TCR_REG );
|
|
|
|
SMC_outw(priv, RCR_DEFAULT, RCR_REG );
|
|
|
|
}
|
|
|
|
|
|
|
|
static int smc91c111_eth_open(struct eth_device *edev)
|
|
|
|
{
|
2009-07-09 13:22:43 +00:00
|
|
|
struct smc91c111_priv *priv = (struct smc91c111_priv *)edev->priv;
|
2009-06-23 14:23:37 +00:00
|
|
|
smc91c111_enable(edev);
|
2009-07-09 13:22:43 +00:00
|
|
|
|
2010-08-26 16:33:28 +00:00
|
|
|
miidev_wait_aneg(&priv->miidev);
|
|
|
|
miidev_print_status(&priv->miidev);
|
2009-07-09 13:22:43 +00:00
|
|
|
|
|
|
|
return 0;
|
2009-06-23 14:23:37 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int smc91c111_eth_send(struct eth_device *edev, void *packet,
|
|
|
|
int packet_length)
|
|
|
|
{
|
|
|
|
struct smc91c111_priv *priv = (struct smc91c111_priv *)edev->priv;
|
|
|
|
unsigned char packet_no;
|
|
|
|
unsigned char *buf;
|
|
|
|
int length;
|
|
|
|
int numPages;
|
|
|
|
int try = 0;
|
|
|
|
int time_out;
|
|
|
|
unsigned char status;
|
|
|
|
unsigned char saved_pnr;
|
|
|
|
unsigned short saved_ptr;
|
|
|
|
|
|
|
|
/* save PTR and PNR registers before manipulation */
|
|
|
|
SMC_SELECT_BANK(priv, 2);
|
|
|
|
saved_pnr = SMC_inb(priv, PN_REG );
|
|
|
|
saved_ptr = SMC_inw(priv, PTR_REG );
|
|
|
|
|
|
|
|
length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
|
|
|
|
|
|
|
|
/* allocate memory
|
|
|
|
** The MMU wants the number of pages to be the number of 256 bytes
|
|
|
|
** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
|
|
|
|
**
|
|
|
|
** The 91C111 ignores the size bits, but the code is left intact
|
|
|
|
** for backwards and future compatibility.
|
|
|
|
**
|
|
|
|
** Pkt size for allocating is data length +6 (for additional status
|
|
|
|
** words, length and ctl!)
|
|
|
|
**
|
|
|
|
** If odd size then last byte is included in this header.
|
|
|
|
*/
|
|
|
|
numPages = ((length & 0xfffe) + 6);
|
|
|
|
numPages >>= 8; /* Divide by 256 */
|
|
|
|
|
|
|
|
if (numPages > 7) {
|
|
|
|
printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* now, try to allocate the memory */
|
|
|
|
SMC_SELECT_BANK(priv, 2);
|
|
|
|
SMC_outw(priv, MC_ALLOC | numPages, MMU_CMD_REG);
|
|
|
|
|
|
|
|
/* FIXME: the ALLOC_INT bit never gets set *
|
|
|
|
* so the following will always give a *
|
|
|
|
* memory allocation error. *
|
|
|
|
* same code works in armboot though *
|
|
|
|
* -ro
|
|
|
|
*/
|
|
|
|
|
|
|
|
again:
|
|
|
|
try++;
|
|
|
|
time_out = MEMORY_WAIT_TIME;
|
|
|
|
do {
|
|
|
|
status = SMC_inb(priv, SMC91111_INT_REG);
|
|
|
|
if (status & IM_ALLOC_INT) {
|
|
|
|
/* acknowledge the interrupt */
|
|
|
|
SMC_outb(priv, IM_ALLOC_INT, SMC91111_INT_REG);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} while (--time_out);
|
|
|
|
|
|
|
|
if (!time_out) {
|
|
|
|
if (try < SMC_ALLOC_MAX_TRY)
|
|
|
|
goto again;
|
|
|
|
else
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
|
|
|
|
SMC_DEV_NAME, try);
|
|
|
|
|
|
|
|
/* I can send the packet now.. */
|
|
|
|
|
|
|
|
buf = (unsigned char *) packet;
|
|
|
|
|
|
|
|
/* If I get here, I _know_ there is a packet slot waiting for me */
|
|
|
|
packet_no = SMC_inb(priv, AR_REG);
|
|
|
|
if (packet_no & AR_FAILED) {
|
|
|
|
/* or isn't there? BAD CHIP! */
|
|
|
|
printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* we have a packet address, so tell the card to use it */
|
|
|
|
SMC_outb(priv, packet_no, PN_REG);
|
|
|
|
|
|
|
|
/* do not write new ptr value if Write data fifo not empty */
|
|
|
|
while ( saved_ptr & PTR_NOTEMPTY )
|
|
|
|
printf ("Write data fifo not empty!\n");
|
|
|
|
|
|
|
|
/* point to the beginning of the packet */
|
|
|
|
SMC_outw(priv, PTR_AUTOINC, PTR_REG);
|
|
|
|
|
|
|
|
/* send the packet length ( +6 for status, length and ctl byte )
|
|
|
|
and the status unsigned short( set to zeros ) */
|
|
|
|
SMC_outl(priv, (length + 6) << 16, SMC91111_DATA_REG);
|
|
|
|
|
|
|
|
/* send the actual data
|
|
|
|
. I _think_ it's faster to send the longs first, and then
|
|
|
|
. mop up by sending the last word. It depends heavily
|
|
|
|
. on alignment, at least on the 486. Maybe it would be
|
|
|
|
. a good idea to check which is optimal? But that could take
|
|
|
|
. almost as much time as is saved?
|
|
|
|
*/
|
|
|
|
SMC_outsl(priv, SMC91111_DATA_REG, buf, length >> 2);
|
|
|
|
if (length & 0x2)
|
|
|
|
SMC_outw(priv,
|
|
|
|
*((unsigned short*) (buf + (length & 0xFFFFFFFC))),
|
|
|
|
SMC91111_DATA_REG);
|
|
|
|
|
|
|
|
/* Send the last byte, if there is one. */
|
|
|
|
if ((length & 1) == 0)
|
|
|
|
SMC_outw(priv, 0, SMC91111_DATA_REG);
|
|
|
|
else
|
|
|
|
SMC_outw(priv, buf[length - 1] | 0x2000, SMC91111_DATA_REG);
|
|
|
|
|
|
|
|
/* and let the chipset deal with it */
|
|
|
|
SMC_outw(priv, MC_ENQUEUE, MMU_CMD_REG);
|
|
|
|
|
|
|
|
/* poll for TX INT */
|
|
|
|
/* if (poll4int (IM_TX_INT, SMC_TX_TIMEOUT)) { */
|
|
|
|
/* poll for TX_EMPTY INT - autorelease enabled */
|
|
|
|
if (poll4int(priv, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) {
|
|
|
|
/* release packet */
|
|
|
|
/* no need to release, MMU does that now */
|
|
|
|
|
|
|
|
/* wait for MMU getting ready (low) */
|
|
|
|
while (SMC_inw(priv, MMU_CMD_REG) & MC_BUSY)
|
|
|
|
udelay (10);
|
|
|
|
return 0;
|
|
|
|
} else {
|
|
|
|
/* ack. int */
|
|
|
|
SMC_outb(priv, IM_TX_EMPTY_INT, SMC91111_INT_REG);
|
|
|
|
|
|
|
|
/* release packet */
|
|
|
|
/* no need to release, MMU does that now */
|
|
|
|
|
|
|
|
/* wait for MMU getting ready (low) */
|
|
|
|
while (SMC_inw(priv, MMU_CMD_REG) & MC_BUSY)
|
|
|
|
udelay (10);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* restore previously saved registers */
|
|
|
|
SMC_outb(priv, saved_pnr, PN_REG );
|
|
|
|
SMC_outw(priv, saved_ptr, PTR_REG );
|
|
|
|
|
|
|
|
return length;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void smc91c111_eth_halt(struct eth_device *edev)
|
|
|
|
{
|
|
|
|
struct smc91c111_priv *priv = (struct smc91c111_priv *)edev->priv;
|
|
|
|
|
|
|
|
/* no more interrupts for me */
|
|
|
|
SMC_SELECT_BANK(priv, 2);
|
|
|
|
SMC_outb(priv, 0, IM_REG);
|
|
|
|
|
|
|
|
/* and tell the card to stay away from that nasty outside world */
|
|
|
|
SMC_SELECT_BANK(priv, 0);
|
|
|
|
SMC_outb(priv, RCR_CLEAR, RCR_REG);
|
|
|
|
SMC_outb(priv, TCR_CLEAR, TCR_REG);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int smc91c111_eth_rx(struct eth_device *edev)
|
|
|
|
{
|
|
|
|
struct smc91c111_priv *priv = (struct smc91c111_priv *)edev->priv;
|
|
|
|
int packet_number;
|
|
|
|
unsigned short status;
|
|
|
|
unsigned short packet_length;
|
|
|
|
int is_error = 0;
|
|
|
|
unsigned long stat_len;
|
|
|
|
unsigned char saved_pnr;
|
|
|
|
unsigned short saved_ptr;
|
|
|
|
|
|
|
|
SMC_SELECT_BANK(priv, 2);
|
|
|
|
/* save PTR and PTR registers */
|
|
|
|
saved_pnr = SMC_inb(priv, PN_REG );
|
|
|
|
saved_ptr = SMC_inw(priv, PTR_REG );
|
|
|
|
|
|
|
|
packet_number = SMC_inw(priv, RXFIFO_REG);
|
|
|
|
|
|
|
|
if (packet_number & RXFIFO_REMPTY)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* start reading from the start of the packet */
|
|
|
|
SMC_outw(priv, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
|
|
|
|
|
|
|
|
/* First two words are status and packet_length */
|
|
|
|
stat_len = SMC_inl(priv, SMC91111_DATA_REG);
|
|
|
|
status = stat_len & 0xffff;
|
|
|
|
packet_length = stat_len >> 16;
|
|
|
|
|
|
|
|
packet_length &= 0x07ff; /* mask off top bits */
|
|
|
|
|
|
|
|
if ( !(status & RS_ERRORS ) ){
|
|
|
|
/* Adjust for having already read the first two words */
|
|
|
|
packet_length -= 4; /*4; */
|
|
|
|
|
|
|
|
|
|
|
|
/* set odd length for bug in LAN91C111, */
|
|
|
|
/* which never sets RS_ODDFRAME */
|
|
|
|
/* TODO ? */
|
|
|
|
|
|
|
|
|
|
|
|
PRINTK3(" Reading %d dwords (and %d bytes) \n",
|
|
|
|
packet_length >> 2, packet_length & 3 );
|
|
|
|
/* QUESTION: Like in the TX routine, do I want
|
|
|
|
to send the DWORDs or the bytes first, or some
|
|
|
|
mixture. A mixture might improve already slow PIO
|
|
|
|
performance */
|
|
|
|
SMC_insl(priv, SMC91111_DATA_REG , NetRxPackets[0],
|
|
|
|
packet_length >> 2);
|
|
|
|
/* read the left over bytes */
|
|
|
|
if (packet_length & 3) {
|
|
|
|
int i;
|
|
|
|
|
|
|
|
unsigned char *tail =
|
|
|
|
(unsigned char *)(NetRxPackets[0] +
|
|
|
|
(packet_length & ~3));
|
|
|
|
unsigned long leftover = SMC_inl(priv,
|
|
|
|
SMC91111_DATA_REG);
|
|
|
|
for (i=0; i<(packet_length & 3); i++)
|
|
|
|
*tail++ =
|
|
|
|
(unsigned char) (leftover >> (8*i)) & 0xff;
|
|
|
|
}
|
|
|
|
|
|
|
|
#if SMC_DEBUG > 2
|
|
|
|
printf("Receiving Packet\n");
|
|
|
|
print_packet( NetRxPackets[0], packet_length );
|
|
|
|
#endif
|
|
|
|
} else {
|
|
|
|
/* error ... */
|
|
|
|
/* TODO ? */
|
|
|
|
is_error = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
while (SMC_inw(priv, MMU_CMD_REG ) & MC_BUSY )
|
|
|
|
udelay(1); /* Wait until not busy */
|
|
|
|
|
|
|
|
/* error or good, tell the card to get rid of this packet */
|
|
|
|
SMC_outw(priv, MC_RELEASE, MMU_CMD_REG );
|
|
|
|
|
|
|
|
while (SMC_inw(priv, MMU_CMD_REG ) & MC_BUSY )
|
|
|
|
udelay(1); /* Wait until not busy */
|
|
|
|
|
|
|
|
/* restore saved registers */
|
|
|
|
SMC_outb(priv, saved_pnr, PN_REG );
|
|
|
|
SMC_outw(priv, saved_ptr, PTR_REG );
|
|
|
|
|
|
|
|
if (!is_error) {
|
|
|
|
/* Pass the packet up to the protocol layers. */
|
2010-06-02 13:59:16 +00:00
|
|
|
net_receive(NetRxPackets[0], packet_length);
|
2009-06-23 14:23:37 +00:00
|
|
|
return packet_length;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int smc91c111_get_ethaddr(struct eth_device *edev, unsigned char *m)
|
|
|
|
{
|
|
|
|
struct smc91c111_priv *priv = (struct smc91c111_priv *)edev->priv;
|
2010-02-01 10:31:02 +00:00
|
|
|
int valid = 0;
|
|
|
|
int i;
|
2009-06-23 14:23:37 +00:00
|
|
|
|
|
|
|
SMC_SELECT_BANK(priv, 1);
|
2010-02-01 10:31:02 +00:00
|
|
|
|
|
|
|
for (i = 0; i < 6; ++i)
|
|
|
|
valid += m[i] = SMC_inb(priv, (ADDR0_REG + i));
|
|
|
|
|
|
|
|
/* no eeprom, no mac */
|
|
|
|
if (!valid)
|
|
|
|
return -1;
|
2009-06-23 14:23:37 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int smc91c111_set_ethaddr(struct eth_device *edev,
|
|
|
|
unsigned char *mac_addr)
|
|
|
|
{
|
|
|
|
struct smc91c111_priv *priv = (struct smc91c111_priv *)edev->priv;
|
|
|
|
unsigned address;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
SMC_SELECT_BANK(priv, 1);
|
|
|
|
|
|
|
|
for (i = 0; i < 6; i += 2) {
|
|
|
|
address = mac_addr[i + 1] << 8;
|
|
|
|
address |= mac_addr[i];
|
|
|
|
SMC_outw(priv, address, (ADDR0_REG + i));
|
|
|
|
}
|
|
|
|
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
#if (SMC_DEBUG > 2 )
|
|
|
|
|
|
|
|
/*------------------------------------------------------------
|
|
|
|
. Debugging function for viewing MII Management serial bitstream
|
|
|
|
.-------------------------------------------------------------*/
|
|
|
|
static void smc_dump_mii_stream (unsigned char * bits, int size)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
printf ("BIT#:");
|
|
|
|
for (i = 0; i < size; ++i) {
|
|
|
|
printf ("%d", i % 10);
|
|
|
|
}
|
|
|
|
|
|
|
|
printf ("\nMDOE:");
|
|
|
|
for (i = 0; i < size; ++i) {
|
|
|
|
if (bits[i] & MII_MDOE)
|
|
|
|
printf ("1");
|
|
|
|
else
|
|
|
|
printf ("0");
|
|
|
|
}
|
|
|
|
|
|
|
|
printf ("\nMDO :");
|
|
|
|
for (i = 0; i < size; ++i) {
|
|
|
|
if (bits[i] & MII_MDO)
|
|
|
|
printf ("1");
|
|
|
|
else
|
|
|
|
printf ("0");
|
|
|
|
}
|
|
|
|
|
|
|
|
printf ("\nMDI :");
|
|
|
|
for (i = 0; i < size; ++i) {
|
|
|
|
if (bits[i] & MII_MDI)
|
|
|
|
printf ("1");
|
|
|
|
else
|
|
|
|
printf ("0");
|
|
|
|
}
|
|
|
|
|
|
|
|
printf ("\n");
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
|
|
#if SMC_DEBUG > 2
|
|
|
|
static void print_packet( unsigned char * buf, int length )
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
int remainder;
|
|
|
|
int lines;
|
|
|
|
|
|
|
|
printf("Packet of length %d \n", length );
|
|
|
|
|
|
|
|
#if SMC_DEBUG > 3
|
|
|
|
lines = length / 16;
|
|
|
|
remainder = length % 16;
|
|
|
|
|
|
|
|
for ( i = 0; i < lines ; i ++ ) {
|
|
|
|
int cur;
|
|
|
|
|
|
|
|
for ( cur = 0; cur < 8; cur ++ ) {
|
|
|
|
unsigned char a, b;
|
|
|
|
|
|
|
|
a = *(buf ++ );
|
|
|
|
b = *(buf ++ );
|
|
|
|
printf("%02x%02x ", a, b );
|
|
|
|
}
|
|
|
|
printf("\n");
|
|
|
|
}
|
|
|
|
for ( i = 0; i < remainder/2 ; i++ ) {
|
|
|
|
unsigned char a, b;
|
|
|
|
|
|
|
|
a = *(buf ++ );
|
|
|
|
b = *(buf ++ );
|
|
|
|
printf("%02x%02x ", a, b );
|
|
|
|
}
|
|
|
|
printf("\n");
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static int smc91c111_init_dev(struct eth_device *edev)
|
|
|
|
{
|
2009-07-09 13:22:43 +00:00
|
|
|
struct smc91c111_priv *priv = (struct smc91c111_priv *)edev->priv;
|
|
|
|
|
|
|
|
/* Configure the Receive/Phy Control register */
|
|
|
|
SMC_SELECT_BANK(priv, 0);
|
|
|
|
SMC_outw(priv, RPC_DEFAULT, RPC_REG);
|
|
|
|
|
2010-08-26 16:33:28 +00:00
|
|
|
miidev_restart_aneg(&priv->miidev);
|
2009-07-09 13:22:43 +00:00
|
|
|
|
2009-06-23 14:23:37 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int smc91c111_probe(struct device_d *dev)
|
|
|
|
{
|
|
|
|
struct eth_device *edev;
|
|
|
|
struct smc91c111_priv *priv;
|
|
|
|
|
|
|
|
edev = xzalloc(sizeof(struct eth_device) +
|
|
|
|
sizeof(struct smc91c111_priv));
|
|
|
|
dev->type_data = edev;
|
|
|
|
edev->priv = (struct smc91c111_priv *)(edev + 1);
|
|
|
|
|
|
|
|
priv = edev->priv;
|
|
|
|
|
|
|
|
priv->a = access_via_32bit;
|
|
|
|
|
|
|
|
edev->init = smc91c111_init_dev;
|
|
|
|
edev->open = smc91c111_eth_open;
|
|
|
|
edev->send = smc91c111_eth_send;
|
|
|
|
edev->recv = smc91c111_eth_rx;
|
|
|
|
edev->halt = smc91c111_eth_halt;
|
|
|
|
edev->get_ethaddr = smc91c111_get_ethaddr;
|
|
|
|
edev->set_ethaddr = smc91c111_set_ethaddr;
|
|
|
|
|
2010-08-26 16:33:28 +00:00
|
|
|
priv->miidev.read = smc91c111_phy_read;
|
|
|
|
priv->miidev.write = smc91c111_phy_write;
|
|
|
|
priv->miidev.address = 0;
|
|
|
|
priv->miidev.flags = 0;
|
|
|
|
priv->miidev.edev = edev;
|
2011-07-28 13:39:41 +00:00
|
|
|
priv->base = dev_request_mem_region(dev, 0);
|
2009-06-23 14:23:37 +00:00
|
|
|
|
|
|
|
smc91c111_reset(edev);
|
|
|
|
|
2010-08-26 16:33:28 +00:00
|
|
|
mii_register(&priv->miidev);
|
2009-06-23 14:23:37 +00:00
|
|
|
eth_register(edev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct driver_d smc91c111_driver = {
|
|
|
|
.name = "smc91c111",
|
|
|
|
.probe = smc91c111_probe,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int smc91c111_init(void)
|
|
|
|
{
|
|
|
|
register_driver(&smc91c111_driver);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
device_initcall(smc91c111_init);
|