2008-08-12 15:05:17 +00:00
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/*
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/*
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* MX21 Hardware contains a bug which causes HW ECC to fail for two
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* consecutive read pages containing 1bit Errors (See MX21 Chip Erata,
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* Erratum 16). Use software ECC for this chip.
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*/
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#include <common.h>
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#include <driver.h>
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#include <malloc.h>
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#include <init.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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2009-10-28 09:10:56 +00:00
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#include <mach/generic.h>
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2009-10-22 12:21:25 +00:00
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#include <mach/imx-nand.h>
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#include <mach/imx-regs.h>
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2008-08-12 15:05:17 +00:00
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#include <asm/io.h>
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#include <errno.h>
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#define DVR_VER "2.0"
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2009-12-18 11:24:33 +00:00
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#define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35() || cpu_is_mx21())
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2009-10-26 11:18:35 +00:00
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#define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27())
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2008-08-12 15:05:17 +00:00
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/*
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* Addresses for NFC registers
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*/
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#define NFC_BUF_SIZE 0xE00
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#define NFC_BUF_ADDR 0xE04
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#define NFC_FLASH_ADDR 0xE06
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#define NFC_FLASH_CMD 0xE08
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#define NFC_CONFIG 0xE0A
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#define NFC_ECC_STATUS_RESULT 0xE0C
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#define NFC_RSLTMAIN_AREA 0xE0E
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#define NFC_RSLTSPARE_AREA 0xE10
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2009-10-26 14:42:49 +00:00
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#define NFC_SPAS 0xe10
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2008-08-12 15:05:17 +00:00
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#define NFC_WRPROT 0xE12
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2009-10-26 11:18:35 +00:00
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#define NFC_V1_UNLOCKSTART_BLKADDR 0xe14
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#define NFC_V1_UNLOCKEND_BLKADDR 0xe16
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#define NFC_V21_UNLOCKSTART_BLKADDR 0xe20
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#define NFC_V21_UNLOCKEND_BLKADDR 0xe22
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2008-08-12 15:05:17 +00:00
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#define NFC_NF_WRPRST 0xE18
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#define NFC_CONFIG1 0xE1A
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#define NFC_CONFIG2 0xE1C
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/*
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* Addresses for NFC RAM BUFFER Main area 0
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*/
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#define MAIN_AREA0 0x000
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#define MAIN_AREA1 0x200
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#define MAIN_AREA2 0x400
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#define MAIN_AREA3 0x600
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/*
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* Addresses for NFC SPARE BUFFER Spare area 0
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*/
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#define SPARE_AREA0 0x800
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#define SPARE_AREA1 0x810
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#define SPARE_AREA2 0x820
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#define SPARE_AREA3 0x830
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/*
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* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command
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* operation
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*/
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#define NFC_CMD 0x1
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/*
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* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address
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* operation
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*/
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#define NFC_ADDR 0x2
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/*
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* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input
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* operation
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*/
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#define NFC_INPUT 0x4
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/*
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* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data Output
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* operation
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*/
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#define NFC_OUTPUT 0x8
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/*
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* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID
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* operation
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*/
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#define NFC_ID 0x10
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/*
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* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read Status
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* operation
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*/
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#define NFC_STATUS 0x20
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/*
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* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status
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* operation
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*/
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#define NFC_INT 0x8000
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2009-10-26 14:42:49 +00:00
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#define NFC_ECC_MODE (1 << 0)
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2008-08-12 15:05:17 +00:00
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#define NFC_SP_EN (1 << 2)
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#define NFC_ECC_EN (1 << 3)
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#define NFC_INT_MSK (1 << 4)
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#define NFC_BIG (1 << 5)
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#define NFC_RST (1 << 6)
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#define NFC_CE (1 << 7)
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#define NFC_ONE_CYCLE (1 << 8)
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2009-10-26 14:42:49 +00:00
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#define NFC_SPAS_16 8
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#define NFC_SPAS_64 32
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#define NFC_SPAS_128 64
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#define NFC_SPAS_218 109
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2008-08-12 15:05:17 +00:00
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#ifdef CONFIG_NAND_IMX_BOOT
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#define __nand_boot_init __bare_init
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#else
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#define __nand_boot_init
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#endif
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struct imx_nand_host {
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struct mtd_info mtd;
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struct nand_chip nand;
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struct mtd_partition *parts;
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struct device_d *dev;
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2009-10-26 11:02:05 +00:00
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void *spare0;
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void *main_area0;
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void *main_area1;
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void __iomem *base;
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2008-08-12 15:05:17 +00:00
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void __iomem *regs;
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int status_request;
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struct clk *clk;
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int pagesize_2k;
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2009-10-23 10:13:51 +00:00
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uint8_t *data_buf;
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unsigned int buf_start;
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int spare_len;
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2008-08-12 15:05:17 +00:00
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};
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/*
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* OOB placement block for use with hardware ecc generation
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*/
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2009-10-26 11:18:35 +00:00
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static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
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2008-08-12 15:05:17 +00:00
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.eccbytes = 5,
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.eccpos = {6, 7, 8, 9, 10},
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2009-10-23 09:06:02 +00:00
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.oobfree = {{0, 5}, {12, 4}}
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2008-08-12 15:05:17 +00:00
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};
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2009-10-26 11:18:35 +00:00
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static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
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2009-10-23 09:06:02 +00:00
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.eccbytes = 20,
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.eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
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38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
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.oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
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2008-08-12 15:05:17 +00:00
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};
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2009-10-26 11:18:35 +00:00
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/* OOB description for 512 byte pages with 16 byte OOB */
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static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
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.eccbytes = 1 * 9,
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.eccpos = {
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7, 8, 9, 10, 11, 12, 13, 14, 15
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},
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.oobfree = {
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{.offset = 0, .length = 5}
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}
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};
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/* OOB description for 2048 byte pages with 64 byte OOB */
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static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
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.eccbytes = 4 * 9,
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.eccpos = {
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7, 8, 9, 10, 11, 12, 13, 14, 15,
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23, 24, 25, 26, 27, 28, 29, 30, 31,
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39, 40, 41, 42, 43, 44, 45, 46, 47,
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55, 56, 57, 58, 59, 60, 61, 62, 63
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},
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.oobfree = {
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{.offset = 2, .length = 4},
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{.offset = 16, .length = 7},
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{.offset = 32, .length = 7},
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{.offset = 48, .length = 7}
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}
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};
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2009-10-23 10:13:51 +00:00
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static void __nand_boot_init memcpy32(void *trg, const void *src, int size)
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{
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int i;
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unsigned int *t = trg;
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unsigned const int *s = src;
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for (i = 0; i < (size >> 2); i++)
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*t++ = *s++;
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}
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2008-08-12 15:05:17 +00:00
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/*
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* This function polls the NANDFC to wait for the basic operation to complete by
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* checking the INT bit of config2 register.
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*
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* @param max_retries number of retry attempts (separated by 1 us)
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* @param param parameter for debug
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*/
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2009-10-23 10:50:10 +00:00
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static void __nand_boot_init wait_op_done(struct imx_nand_host *host)
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2008-08-12 15:05:17 +00:00
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{
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u32 tmp;
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2009-05-13 13:58:57 +00:00
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int i;
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2008-08-12 15:05:17 +00:00
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2009-05-13 13:58:57 +00:00
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/* This is a timeout of roughly 15ms on my system. We
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* need about 2us, but be generous. Don't use udelay
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* here as we might be here from nand booting.
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*/
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for (i = 0; i < 100000; i++) {
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2008-08-12 15:05:17 +00:00
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if (readw(host->regs + NFC_CONFIG2) & NFC_INT) {
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tmp = readw(host->regs + NFC_CONFIG2);
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tmp &= ~NFC_INT;
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writew(tmp, host->regs + NFC_CONFIG2);
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2009-05-13 13:58:57 +00:00
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return;
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2008-08-12 15:05:17 +00:00
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}
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}
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}
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/*
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* This function issues the specified command to the NAND device and
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* waits for completion.
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*
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* @param cmd command for NAND Flash
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*/
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static void __nand_boot_init send_cmd(struct imx_nand_host *host, u16 cmd)
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{
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2009-04-24 19:42:37 +00:00
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MTD_DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
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2008-08-12 15:05:17 +00:00
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writew(cmd, host->regs + NFC_FLASH_CMD);
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writew(NFC_CMD, host->regs + NFC_CONFIG2);
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/* Wait for operation to complete */
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2009-10-23 10:50:10 +00:00
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wait_op_done(host);
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2008-08-12 15:05:17 +00:00
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}
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/*
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* This function sends an address (or partial address) to the
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* NAND device. The address is used to select the source/destination for
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* a NAND command.
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*
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* @param addr address to be written to NFC.
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* @param islast True if this is the last address cycle for command
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*/
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2009-10-26 10:52:15 +00:00
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static void __nand_boot_init noinline send_addr(struct imx_nand_host *host, u16 addr)
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2008-08-12 15:05:17 +00:00
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{
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2009-04-24 19:42:37 +00:00
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MTD_DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
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2008-08-12 15:05:17 +00:00
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writew(addr, host->regs + NFC_FLASH_ADDR);
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writew(NFC_ADDR, host->regs + NFC_CONFIG2);
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/* Wait for operation to complete */
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2009-10-23 10:50:10 +00:00
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wait_op_done(host);
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2008-08-12 15:05:17 +00:00
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}
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/*
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* This function requests the NANDFC to initate the transfer
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* of data currently in the NANDFC RAM buffer to the NAND device.
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*
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* @param buf_id Specify Internal RAM Buffer number (0-3)
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* @param spare_only set true if only the spare area is transferred
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*/
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2009-10-23 11:08:25 +00:00
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static void __nand_boot_init send_page(struct imx_nand_host *host,
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2009-10-23 10:13:51 +00:00
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unsigned int ops)
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2008-08-12 15:05:17 +00:00
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{
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2009-10-23 11:08:25 +00:00
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int bufs, i;
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2008-08-12 15:05:17 +00:00
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2009-10-26 11:18:35 +00:00
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if (nfc_is_v1() && host->pagesize_2k)
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2009-10-23 11:08:25 +00:00
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bufs = 4;
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else
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bufs = 1;
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2008-08-12 15:05:17 +00:00
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2009-10-23 11:08:25 +00:00
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for (i = 0; i < bufs; i++) {
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/* NANDFC buffer 0 is used for page read/write */
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writew(i, host->regs + NFC_BUF_ADDR);
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2008-08-12 15:05:17 +00:00
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2009-10-23 11:08:25 +00:00
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writew(ops, host->regs + NFC_CONFIG2);
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/* Wait for operation to complete */
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wait_op_done(host);
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}
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2008-08-12 15:05:17 +00:00
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}
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/*
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* This function requests the NANDFC to perform a read of the
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* NAND device ID.
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*/
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2009-10-23 11:02:47 +00:00
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static void send_read_id(struct imx_nand_host *host)
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2008-08-12 15:05:17 +00:00
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{
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struct nand_chip *this = &host->nand;
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u16 tmp;
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/* NANDFC buffer 0 is used for device ID output */
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writew(0x0, host->regs + NFC_BUF_ADDR);
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/* Read ID into main buffer */
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tmp = readw(host->regs + NFC_CONFIG1);
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tmp &= ~NFC_SP_EN;
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writew(tmp, host->regs + NFC_CONFIG1);
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writew(NFC_ID, host->regs + NFC_CONFIG2);
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/* Wait for operation to complete */
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2009-10-23 10:50:10 +00:00
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wait_op_done(host);
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2008-08-12 15:05:17 +00:00
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if (this->options & NAND_BUSWIDTH_16) {
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2009-10-26 11:02:05 +00:00
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volatile u16 *mainbuf = host->main_area0;
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2008-08-12 15:05:17 +00:00
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/*
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|
|
* Pack the every-other-byte result for 16-bit ID reads
|
|
|
|
* into every-byte as the generic code expects and various
|
|
|
|
* chips implement.
|
|
|
|
*/
|
|
|
|
|
|
|
|
mainbuf[0] = (mainbuf[0] & 0xff) | ((mainbuf[1] & 0xff) << 8);
|
|
|
|
mainbuf[1] = (mainbuf[2] & 0xff) | ((mainbuf[3] & 0xff) << 8);
|
|
|
|
mainbuf[2] = (mainbuf[4] & 0xff) | ((mainbuf[5] & 0xff) << 8);
|
|
|
|
}
|
2009-10-26 11:02:05 +00:00
|
|
|
memcpy32(host->data_buf, host->main_area0, 16);
|
2008-08-12 15:05:17 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This function requests the NANDFC to perform a read of the
|
|
|
|
* NAND device status and returns the current status.
|
|
|
|
*
|
|
|
|
* @return device status
|
|
|
|
*/
|
|
|
|
static u16 get_dev_status(struct imx_nand_host *host)
|
|
|
|
{
|
2009-10-26 11:02:05 +00:00
|
|
|
volatile u16 *mainbuf = host->main_area1;
|
2008-08-12 15:05:17 +00:00
|
|
|
u32 store;
|
|
|
|
u16 ret, tmp;
|
|
|
|
/* Issue status request to NAND device */
|
|
|
|
|
|
|
|
/* store the main area1 first word, later do recovery */
|
|
|
|
store = *((u32 *) mainbuf);
|
|
|
|
/*
|
|
|
|
* NANDFC buffer 1 is used for device status to prevent
|
|
|
|
* corruption of read/write buffer on status requests.
|
|
|
|
*/
|
|
|
|
writew(1, host->regs + NFC_BUF_ADDR);
|
|
|
|
|
|
|
|
/* Read status into main buffer */
|
|
|
|
tmp = readw(host->regs + NFC_CONFIG1);
|
|
|
|
tmp &= ~NFC_SP_EN;
|
|
|
|
writew(tmp, host->regs + NFC_CONFIG1);
|
|
|
|
|
|
|
|
writew(NFC_STATUS, host->regs + NFC_CONFIG2);
|
|
|
|
|
|
|
|
/* Wait for operation to complete */
|
2009-10-23 10:50:10 +00:00
|
|
|
wait_op_done(host);
|
2008-08-12 15:05:17 +00:00
|
|
|
|
|
|
|
/* Status is placed in first word of main buffer */
|
|
|
|
/* get status, then recovery area 1 data */
|
|
|
|
ret = mainbuf[0];
|
|
|
|
*((u32 *) mainbuf) = store;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This function is used by upper layer to checks if device is ready
|
|
|
|
*
|
|
|
|
* @param mtd MTD structure for the NAND Flash
|
|
|
|
*
|
|
|
|
* @return 0 if device is busy else 1
|
|
|
|
*/
|
|
|
|
static int imx_nand_dev_ready(struct mtd_info *mtd)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* NFC handles R/B internally.Therefore,this function
|
|
|
|
* always returns status as ready.
|
|
|
|
*/
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void imx_nand_enable_hwecc(struct mtd_info *mtd, int mode)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* If HW ECC is enabled, we turn it on during init. There is
|
|
|
|
* no need to enable again here.
|
|
|
|
*/
|
|
|
|
}
|
|
|
|
|
|
|
|
static int imx_nand_correct_data(struct mtd_info *mtd, u_char * dat,
|
|
|
|
u_char * read_ecc, u_char * calc_ecc)
|
|
|
|
{
|
|
|
|
struct nand_chip *nand_chip = mtd->priv;
|
|
|
|
struct imx_nand_host *host = nand_chip->priv;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 1-Bit errors are automatically corrected in HW. No need for
|
|
|
|
* additional correction. 2-Bit errors cannot be corrected by
|
|
|
|
* HW ECC, so we need to return failure
|
|
|
|
*/
|
|
|
|
u16 ecc_status = readw(host->regs + NFC_ECC_STATUS_RESULT);
|
|
|
|
|
|
|
|
if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
|
2009-04-24 19:42:37 +00:00
|
|
|
MTD_DEBUG(MTD_DEBUG_LEVEL0,
|
2008-08-12 15:05:17 +00:00
|
|
|
"MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int imx_nand_calculate_ecc(struct mtd_info *mtd, const u_char * dat,
|
|
|
|
u_char * ecc_code)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This function reads byte from the NAND Flash
|
|
|
|
*
|
|
|
|
* @param mtd MTD structure for the NAND Flash
|
|
|
|
*
|
|
|
|
* @return data read from the NAND Flash
|
|
|
|
*/
|
|
|
|
static u_char imx_nand_read_byte(struct mtd_info *mtd)
|
|
|
|
{
|
|
|
|
struct nand_chip *nand_chip = mtd->priv;
|
|
|
|
struct imx_nand_host *host = nand_chip->priv;
|
2009-10-23 10:13:51 +00:00
|
|
|
u_char ret;
|
2008-08-12 15:05:17 +00:00
|
|
|
|
|
|
|
/* Check for status request */
|
|
|
|
if (host->status_request)
|
|
|
|
return get_dev_status(host) & 0xFF;
|
|
|
|
|
2009-10-23 10:13:51 +00:00
|
|
|
ret = *(uint8_t *)(host->data_buf + host->buf_start);
|
|
|
|
host->buf_start++;
|
2008-08-12 15:05:17 +00:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This function reads word from the NAND Flash
|
|
|
|
*
|
|
|
|
* @param mtd MTD structure for the NAND Flash
|
|
|
|
*
|
|
|
|
* @return data read from the NAND Flash
|
|
|
|
*/
|
|
|
|
static u16 imx_nand_read_word(struct mtd_info *mtd)
|
|
|
|
{
|
|
|
|
struct nand_chip *nand_chip = mtd->priv;
|
|
|
|
struct imx_nand_host *host = nand_chip->priv;
|
2009-10-23 10:13:51 +00:00
|
|
|
uint16_t ret;
|
2008-08-12 15:05:17 +00:00
|
|
|
|
2009-10-23 10:13:51 +00:00
|
|
|
ret = *(uint16_t *)(host->data_buf + host->buf_start);
|
|
|
|
host->buf_start += 2;
|
2008-08-12 15:05:17 +00:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This function writes data of length \b len to buffer \b buf. The data to be
|
|
|
|
* written on NAND Flash is first copied to RAMbuffer. After the Data Input
|
|
|
|
* Operation by the NFC, the data is written to NAND Flash
|
|
|
|
*
|
|
|
|
* @param mtd MTD structure for the NAND Flash
|
|
|
|
* @param buf data to be written to NAND Flash
|
|
|
|
* @param len number of bytes to be written
|
|
|
|
*/
|
|
|
|
static void imx_nand_write_buf(struct mtd_info *mtd,
|
|
|
|
const u_char *buf, int len)
|
|
|
|
{
|
|
|
|
struct nand_chip *nand_chip = mtd->priv;
|
|
|
|
struct imx_nand_host *host = nand_chip->priv;
|
2009-10-23 10:13:51 +00:00
|
|
|
u16 col = host->buf_start;
|
|
|
|
int n = mtd->oobsize + mtd->writesize - col;
|
2008-08-12 15:05:17 +00:00
|
|
|
|
2009-10-23 10:13:51 +00:00
|
|
|
n = min(n, len);
|
|
|
|
memcpy32(host->data_buf + col, buf, n);
|
2008-08-12 15:05:17 +00:00
|
|
|
|
2009-10-23 10:13:51 +00:00
|
|
|
host->buf_start += n;
|
2008-08-12 15:05:17 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This function is used to read the data buffer from the NAND Flash. To
|
|
|
|
* read the data from NAND Flash first the data output cycle is initiated by
|
|
|
|
* the NFC, which copies the data to RAMbuffer. This data of length \b len is
|
|
|
|
* then copied to buffer \b buf.
|
|
|
|
*
|
|
|
|
* @param mtd MTD structure for the NAND Flash
|
|
|
|
* @param buf data to be read from NAND Flash
|
|
|
|
* @param len number of bytes to be read
|
|
|
|
*/
|
|
|
|
static void imx_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len)
|
|
|
|
{
|
|
|
|
struct nand_chip *nand_chip = mtd->priv;
|
|
|
|
struct imx_nand_host *host = nand_chip->priv;
|
2009-10-23 10:13:51 +00:00
|
|
|
u16 col = host->buf_start;
|
|
|
|
int n = mtd->oobsize + mtd->writesize - col;
|
2008-08-12 15:05:17 +00:00
|
|
|
|
2009-10-23 10:13:51 +00:00
|
|
|
n = min(n, len);
|
2008-08-12 15:05:17 +00:00
|
|
|
|
2009-10-23 10:13:51 +00:00
|
|
|
memcpy32(buf, host->data_buf + col, len);
|
2008-08-12 15:05:17 +00:00
|
|
|
|
2009-10-23 10:13:51 +00:00
|
|
|
host->buf_start += len;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Function to transfer data to/from spare area.
|
|
|
|
*/
|
|
|
|
static void copy_spare(struct mtd_info *mtd, int bfrom)
|
|
|
|
{
|
|
|
|
struct nand_chip *this = mtd->priv;
|
|
|
|
struct imx_nand_host *host = this->priv;
|
|
|
|
u16 i, j;
|
|
|
|
u16 n = mtd->writesize >> 9;
|
|
|
|
u8 *d = host->data_buf + mtd->writesize;
|
2009-10-26 11:02:05 +00:00
|
|
|
u8 *s = host->spare0;
|
2009-10-23 10:13:51 +00:00
|
|
|
u16 t = host->spare_len;
|
|
|
|
|
|
|
|
j = (mtd->oobsize / n >> 1) << 1;
|
|
|
|
|
|
|
|
if (bfrom) {
|
|
|
|
for (i = 0; i < n - 1; i++)
|
|
|
|
memcpy32(d + i * j, s + i * t, j);
|
2008-08-12 15:05:17 +00:00
|
|
|
|
2009-10-23 10:13:51 +00:00
|
|
|
/* the last section */
|
|
|
|
memcpy32(d + i * j, s + i * t, mtd->oobsize - i * j);
|
|
|
|
} else {
|
|
|
|
for (i = 0; i < n - 1; i++)
|
|
|
|
memcpy32(&s[i * t], &d[i * j], j);
|
|
|
|
|
|
|
|
/* the last section */
|
|
|
|
memcpy32(&s[i * t], &d[i * j], mtd->oobsize - i * j);
|
|
|
|
}
|
2008-08-12 15:05:17 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This function is used by the upper layer to verify the data in NAND Flash
|
|
|
|
* with the data in the \b buf.
|
|
|
|
*
|
|
|
|
* @param mtd MTD structure for the NAND Flash
|
|
|
|
* @param buf data to be verified
|
|
|
|
* @param len length of the data to be verified
|
|
|
|
*
|
|
|
|
* @return -EFAULT if error else 0
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
static int
|
|
|
|
imx_nand_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
|
|
|
|
{
|
|
|
|
return -EFAULT;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This function is used by upper layer for select and deselect of the NAND
|
|
|
|
* chip
|
|
|
|
*
|
|
|
|
* @param mtd MTD structure for the NAND Flash
|
|
|
|
* @param chip val indicating select or deselect
|
|
|
|
*/
|
|
|
|
static void imx_nand_select_chip(struct mtd_info *mtd, int chip)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_MTD_NAND_MXC_FORCE_CE
|
|
|
|
u16 tmp;
|
|
|
|
|
|
|
|
if (chip > 0) {
|
2009-04-24 19:42:37 +00:00
|
|
|
MTD_DEBUG(MTD_DEBUG_LEVEL0,
|
2008-08-12 15:05:17 +00:00
|
|
|
"ERROR: Illegal chip select (chip = %d)\n", chip);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (chip == -1) {
|
|
|
|
tmp = readw(host->regs + NFC_CONFIG1);
|
|
|
|
tmp &= ~NFC_CE;
|
|
|
|
writew(tmp, host->regs + NFC_CONFIG1);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
tmp = readw(host->regs + NFC_CONFIG1);
|
|
|
|
tmp |= NFC_CE;
|
|
|
|
writew(tmp, host->regs + NFC_CONFIG1);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2009-10-23 09:11:57 +00:00
|
|
|
static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
|
|
|
|
{
|
|
|
|
struct nand_chip *nand_chip = mtd->priv;
|
|
|
|
struct imx_nand_host *host = nand_chip->priv;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Write out column address, if necessary
|
|
|
|
*/
|
|
|
|
if (column != -1) {
|
|
|
|
/*
|
|
|
|
* MXC NANDFC can only perform full page+spare or
|
|
|
|
* spare-only read/write. When the upper layers
|
|
|
|
* layers perform a read/write buf operation,
|
|
|
|
* we will used the saved column adress to index into
|
|
|
|
* the full page.
|
|
|
|
*/
|
|
|
|
send_addr(host, 0);
|
|
|
|
if (host->pagesize_2k)
|
|
|
|
/* another col addr cycle for 2k page */
|
|
|
|
send_addr(host, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Write out page address, if necessary
|
|
|
|
*/
|
|
|
|
if (page_addr != -1) {
|
|
|
|
send_addr(host, (page_addr & 0xff)); /* paddr_0 - p_addr_7 */
|
|
|
|
|
|
|
|
if (host->pagesize_2k) {
|
|
|
|
send_addr(host, (page_addr >> 8) & 0xFF);
|
|
|
|
if (mtd->size >= 0x10000000) {
|
|
|
|
send_addr(host, (page_addr >> 16) & 0xff);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* One more address cycle for higher density devices */
|
|
|
|
if (mtd->size >= 0x4000000) {
|
|
|
|
/* paddr_8 - paddr_15 */
|
|
|
|
send_addr(host, (page_addr >> 8) & 0xff);
|
|
|
|
send_addr(host, (page_addr >> 16) & 0xff);
|
|
|
|
} else
|
|
|
|
/* paddr_8 - paddr_15 */
|
|
|
|
send_addr(host, (page_addr >> 8) & 0xff);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-08-12 15:05:17 +00:00
|
|
|
/*
|
|
|
|
* This function is used by the upper layer to write command to NAND Flash for
|
|
|
|
* different operations to be carried out on NAND Flash
|
|
|
|
*
|
|
|
|
* @param mtd MTD structure for the NAND Flash
|
|
|
|
* @param command command for NAND Flash
|
|
|
|
* @param column column offset for the page read
|
|
|
|
* @param page_addr page to be read from NAND Flash
|
|
|
|
*/
|
|
|
|
static void imx_nand_command(struct mtd_info *mtd, unsigned command,
|
|
|
|
int column, int page_addr)
|
|
|
|
{
|
|
|
|
struct nand_chip *nand_chip = mtd->priv;
|
|
|
|
struct imx_nand_host *host = nand_chip->priv;
|
|
|
|
|
2009-04-24 19:42:37 +00:00
|
|
|
MTD_DEBUG(MTD_DEBUG_LEVEL3,
|
2008-08-12 15:05:17 +00:00
|
|
|
"imx_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
|
|
|
|
command, column, page_addr);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Reset command state information
|
|
|
|
*/
|
|
|
|
host->status_request = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Command pre-processing step
|
|
|
|
*/
|
|
|
|
switch (command) {
|
|
|
|
|
|
|
|
case NAND_CMD_STATUS:
|
2009-10-23 10:13:51 +00:00
|
|
|
host->buf_start = 0;
|
2008-08-12 15:05:17 +00:00
|
|
|
host->status_request = 1;
|
2009-10-23 11:02:47 +00:00
|
|
|
send_cmd(host, command);
|
|
|
|
mxc_do_addr_cycle(mtd, column, page_addr);
|
2008-08-12 15:05:17 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
case NAND_CMD_READ0:
|
|
|
|
case NAND_CMD_READOOB:
|
2009-10-23 11:02:47 +00:00
|
|
|
if (command == NAND_CMD_READ0)
|
|
|
|
host->buf_start = column;
|
|
|
|
else
|
|
|
|
host->buf_start = column + mtd->writesize;
|
|
|
|
|
2009-10-26 10:53:00 +00:00
|
|
|
command = NAND_CMD_READ0;
|
2009-10-23 11:02:47 +00:00
|
|
|
|
|
|
|
send_cmd(host, command);
|
|
|
|
mxc_do_addr_cycle(mtd, column, page_addr);
|
|
|
|
|
2009-10-23 11:08:25 +00:00
|
|
|
if (host->pagesize_2k)
|
2009-10-23 11:02:47 +00:00
|
|
|
/* send read confirm command */
|
|
|
|
send_cmd(host, NAND_CMD_READSTART);
|
2009-10-23 11:08:25 +00:00
|
|
|
|
|
|
|
send_page(host, NFC_OUTPUT);
|
2009-10-23 11:02:47 +00:00
|
|
|
|
2009-10-26 11:02:05 +00:00
|
|
|
memcpy32(host->data_buf, host->main_area0, mtd->writesize);
|
2009-10-23 11:02:47 +00:00
|
|
|
copy_spare(mtd, 1);
|
2008-08-12 15:05:17 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
case NAND_CMD_SEQIN:
|
|
|
|
if (column >= mtd->writesize) {
|
|
|
|
if (host->pagesize_2k) {
|
|
|
|
/**
|
|
|
|
* FIXME: before send SEQIN command for write
|
|
|
|
* OOB, we must read one page out. For K9F1GXX
|
|
|
|
* has no READ1 command to set current HW
|
|
|
|
* pointer to spare area, we must write the
|
|
|
|
* whole page including OOB together.
|
|
|
|
*/
|
|
|
|
/* call ourself to read a page */
|
|
|
|
imx_nand_command(mtd, NAND_CMD_READ0, 0,
|
|
|
|
page_addr);
|
|
|
|
}
|
2009-10-23 10:13:51 +00:00
|
|
|
host->buf_start = column;
|
|
|
|
|
2008-08-12 15:05:17 +00:00
|
|
|
/* Set program pointer to spare region */
|
|
|
|
if (!host->pagesize_2k)
|
|
|
|
send_cmd(host, NAND_CMD_READOOB);
|
|
|
|
} else {
|
2009-10-23 10:13:51 +00:00
|
|
|
host->buf_start = column;
|
|
|
|
|
2008-08-12 15:05:17 +00:00
|
|
|
/* Set program pointer to page start */
|
|
|
|
if (!host->pagesize_2k)
|
|
|
|
send_cmd(host, NAND_CMD_READ0);
|
|
|
|
}
|
2009-10-23 11:02:47 +00:00
|
|
|
send_cmd(host, command);
|
|
|
|
mxc_do_addr_cycle(mtd, column, page_addr);
|
|
|
|
|
2008-08-12 15:05:17 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
case NAND_CMD_PAGEPROG:
|
2009-10-26 11:02:05 +00:00
|
|
|
memcpy32(host->main_area0, host->data_buf, mtd->writesize);
|
2009-10-23 10:13:51 +00:00
|
|
|
copy_spare(mtd, 0);
|
2009-10-23 11:08:25 +00:00
|
|
|
send_page(host, NFC_INPUT);
|
2009-10-23 11:02:47 +00:00
|
|
|
send_cmd(host, command);
|
|
|
|
mxc_do_addr_cycle(mtd, column, page_addr);
|
2008-08-12 15:05:17 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
case NAND_CMD_READID:
|
2009-10-23 11:02:47 +00:00
|
|
|
send_cmd(host, command);
|
|
|
|
mxc_do_addr_cycle(mtd, column, page_addr);
|
2009-10-23 10:13:51 +00:00
|
|
|
host->buf_start = 0;
|
2008-08-12 15:05:17 +00:00
|
|
|
send_read_id(host);
|
|
|
|
break;
|
|
|
|
|
2009-10-23 11:02:47 +00:00
|
|
|
case NAND_CMD_ERASE1:
|
2008-08-12 15:05:17 +00:00
|
|
|
case NAND_CMD_ERASE2:
|
2009-12-09 13:55:15 +00:00
|
|
|
case NAND_CMD_RESET:
|
2009-10-23 11:02:47 +00:00
|
|
|
send_cmd(host, command);
|
|
|
|
mxc_do_addr_cycle(mtd, column, page_addr);
|
2008-08-12 15:05:17 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_MXC_NAND_LOW_LEVEL_ERASE
|
|
|
|
static void imx_low_erase(struct mtd_info *mtd)
|
|
|
|
{
|
|
|
|
|
|
|
|
struct nand_chip *this = mtd->priv;
|
|
|
|
unsigned int page_addr, addr;
|
|
|
|
u_char status;
|
|
|
|
|
2009-04-24 19:42:37 +00:00
|
|
|
MTD_DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : imx_low_erase:Erasing NAND\n");
|
2008-08-12 15:05:17 +00:00
|
|
|
for (addr = 0; addr < this->chipsize; addr += mtd->erasesize) {
|
|
|
|
page_addr = addr / mtd->writesize;
|
|
|
|
imx_nand_command(mtd, NAND_CMD_ERASE1, -1, page_addr);
|
|
|
|
imx_nand_command(mtd, NAND_CMD_ERASE2, -1, -1);
|
|
|
|
imx_nand_command(mtd, NAND_CMD_STATUS, -1, -1);
|
|
|
|
status = imx_nand_read_byte(mtd);
|
|
|
|
if (status & NAND_STATUS_FAIL) {
|
|
|
|
printk(KERN_ERR
|
|
|
|
"ERASE FAILED(block = %d,status = 0x%x)\n",
|
|
|
|
addr / mtd->erasesize, status);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
#endif
|
2009-10-26 11:42:00 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* The generic flash bbt decriptors overlap with our ecc
|
|
|
|
* hardware, so define some i.MX specific ones.
|
|
|
|
*/
|
|
|
|
static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
|
|
|
|
static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
|
|
|
|
|
|
|
|
static struct nand_bbt_descr bbt_main_descr = {
|
|
|
|
.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
|
|
|
|
| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
|
|
|
|
.offs = 0,
|
|
|
|
.len = 4,
|
|
|
|
.veroffs = 4,
|
|
|
|
.maxblocks = 4,
|
|
|
|
.pattern = bbt_pattern,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct nand_bbt_descr bbt_mirror_descr = {
|
|
|
|
.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
|
|
|
|
| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
|
|
|
|
.offs = 0,
|
|
|
|
.len = 4,
|
|
|
|
.veroffs = 4,
|
|
|
|
.maxblocks = 4,
|
|
|
|
.pattern = mirror_pattern,
|
|
|
|
};
|
|
|
|
|
2008-08-12 15:05:17 +00:00
|
|
|
/*
|
|
|
|
* This function is called during the driver binding process.
|
|
|
|
*
|
|
|
|
* @param pdev the device structure used to store device specific
|
|
|
|
* information that is used by the suspend, resume and
|
|
|
|
* remove functions
|
|
|
|
*
|
|
|
|
* @return The function always returns 0.
|
|
|
|
*/
|
2009-07-15 15:18:40 +00:00
|
|
|
|
2008-08-12 15:05:17 +00:00
|
|
|
static int __init imxnd_probe(struct device_d *dev)
|
|
|
|
{
|
|
|
|
struct nand_chip *this;
|
|
|
|
struct mtd_info *mtd;
|
|
|
|
struct imx_nand_platform_data *pdata = dev->platform_data;
|
|
|
|
struct imx_nand_host *host;
|
2009-10-26 11:18:35 +00:00
|
|
|
struct nand_ecclayout *oob_smallpage, *oob_largepage;
|
2008-08-12 15:05:17 +00:00
|
|
|
u16 tmp;
|
|
|
|
int err = 0;
|
2009-07-15 15:18:40 +00:00
|
|
|
#ifdef CONFIG_ARCH_IMX27
|
2008-08-12 15:05:17 +00:00
|
|
|
PCCR1 |= PCCR1_NFC_BAUDEN;
|
2008-11-10 16:53:24 +00:00
|
|
|
#endif
|
2008-08-12 15:05:17 +00:00
|
|
|
/* Allocate memory for MTD device structure and private data */
|
2009-10-23 10:13:51 +00:00
|
|
|
host = kzalloc(sizeof(struct imx_nand_host) + NAND_MAX_PAGESIZE +
|
|
|
|
NAND_MAX_OOBSIZE, GFP_KERNEL);
|
2008-08-12 15:05:17 +00:00
|
|
|
if (!host)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2009-10-23 10:13:51 +00:00
|
|
|
host->data_buf = (uint8_t *)(host + 1);
|
2009-10-26 11:18:35 +00:00
|
|
|
host->base = (void __iomem *)dev->map_base;
|
2009-10-23 10:13:51 +00:00
|
|
|
|
2009-10-26 11:02:05 +00:00
|
|
|
host->main_area0 = host->base;
|
|
|
|
host->main_area1 = host->base + 0x200;
|
2009-10-26 11:18:35 +00:00
|
|
|
|
|
|
|
if (nfc_is_v21()) {
|
|
|
|
host->regs = host->base + 0x1000;
|
|
|
|
host->spare0 = host->base + 0x1000;
|
|
|
|
host->spare_len = 64;
|
|
|
|
oob_smallpage = &nandv2_hw_eccoob_smallpage;
|
|
|
|
oob_largepage = &nandv2_hw_eccoob_largepage;
|
|
|
|
} else if (nfc_is_v1()) {
|
|
|
|
host->regs = host->base;
|
|
|
|
host->spare0 = host->base + 0x800;
|
|
|
|
host->spare_len = 16;
|
|
|
|
oob_smallpage = &nandv1_hw_eccoob_smallpage;
|
|
|
|
oob_largepage = &nandv1_hw_eccoob_largepage;
|
|
|
|
}
|
2009-10-26 11:02:05 +00:00
|
|
|
|
2008-08-12 15:05:17 +00:00
|
|
|
host->dev = dev;
|
|
|
|
/* structures must be linked */
|
|
|
|
this = &host->nand;
|
|
|
|
mtd = &host->mtd;
|
|
|
|
mtd->priv = this;
|
|
|
|
|
|
|
|
/* 50 us command delay time */
|
|
|
|
this->chip_delay = 5;
|
|
|
|
|
|
|
|
this->priv = host;
|
|
|
|
this->dev_ready = imx_nand_dev_ready;
|
|
|
|
this->cmdfunc = imx_nand_command;
|
|
|
|
this->select_chip = imx_nand_select_chip;
|
|
|
|
this->read_byte = imx_nand_read_byte;
|
|
|
|
this->read_word = imx_nand_read_word;
|
|
|
|
this->write_buf = imx_nand_write_buf;
|
|
|
|
this->read_buf = imx_nand_read_buf;
|
|
|
|
this->verify_buf = imx_nand_verify_buf;
|
|
|
|
#if 0
|
|
|
|
host->clk = clk_get(&pdev->dev, "nfc_clk");
|
|
|
|
if (IS_ERR(host->clk))
|
|
|
|
goto eclk;
|
|
|
|
|
|
|
|
clk_enable(host->clk);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
tmp = readw(host->regs + NFC_CONFIG1);
|
|
|
|
tmp |= NFC_INT_MSK;
|
2009-10-23 10:13:51 +00:00
|
|
|
tmp &= ~NFC_SP_EN;
|
2009-10-26 14:42:49 +00:00
|
|
|
if (nfc_is_v21())
|
|
|
|
/* currently no support for 218 byte OOB with stronger ECC */
|
|
|
|
tmp |= NFC_ECC_MODE;
|
2008-08-12 15:05:17 +00:00
|
|
|
writew(tmp, host->regs + NFC_CONFIG1);
|
|
|
|
|
|
|
|
if (pdata->hw_ecc) {
|
|
|
|
this->ecc.calculate = imx_nand_calculate_ecc;
|
|
|
|
this->ecc.hwctl = imx_nand_enable_hwecc;
|
|
|
|
this->ecc.correct = imx_nand_correct_data;
|
|
|
|
this->ecc.mode = NAND_ECC_HW;
|
|
|
|
this->ecc.size = 512;
|
|
|
|
tmp = readw(host->regs + NFC_CONFIG1);
|
|
|
|
tmp |= NFC_ECC_EN;
|
|
|
|
writew(tmp, host->regs + NFC_CONFIG1);
|
|
|
|
} else {
|
|
|
|
this->ecc.size = 512;
|
|
|
|
this->ecc.mode = NAND_ECC_SOFT;
|
|
|
|
tmp = readw(host->regs + NFC_CONFIG1);
|
|
|
|
tmp &= ~NFC_ECC_EN;
|
|
|
|
writew(tmp, host->regs + NFC_CONFIG1);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Reset NAND */
|
|
|
|
this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
|
|
|
|
|
|
|
|
/* preset operation */
|
|
|
|
/* Unlock the internal RAM Buffer */
|
|
|
|
writew(0x2, host->regs + NFC_CONFIG);
|
|
|
|
|
|
|
|
/* Blocks to be unlocked */
|
2009-10-26 11:18:35 +00:00
|
|
|
if (nfc_is_v21()) {
|
|
|
|
writew(0x0, host->regs + NFC_V21_UNLOCKSTART_BLKADDR);
|
|
|
|
writew(0xffff, host->regs + NFC_V21_UNLOCKEND_BLKADDR);
|
|
|
|
this->ecc.bytes = 9;
|
|
|
|
} else if (nfc_is_v1()) {
|
|
|
|
writew(0x0, host->regs + NFC_V1_UNLOCKSTART_BLKADDR);
|
|
|
|
writew(0x4000, host->regs + NFC_V1_UNLOCKEND_BLKADDR);
|
|
|
|
this->ecc.bytes = 3;
|
|
|
|
}
|
2008-08-12 15:05:17 +00:00
|
|
|
|
|
|
|
/* Unlock Block Command for given address range */
|
|
|
|
writew(0x4, host->regs + NFC_WRPROT);
|
|
|
|
|
2009-10-26 11:18:35 +00:00
|
|
|
this->ecc.layout = oob_smallpage;
|
|
|
|
|
2008-08-12 15:05:17 +00:00
|
|
|
/* NAND bus width determines access funtions used by upper layer */
|
|
|
|
if (pdata->width == 2) {
|
|
|
|
this->options |= NAND_BUSWIDTH_16;
|
2009-10-26 11:18:35 +00:00
|
|
|
this->ecc.layout = &nandv1_hw_eccoob_smallpage;
|
2009-11-24 11:21:35 +00:00
|
|
|
imx_nand_set_layout(0, 16);
|
2008-08-12 15:05:17 +00:00
|
|
|
}
|
|
|
|
|
2009-10-26 11:42:00 +00:00
|
|
|
if (pdata->flash_bbt) {
|
|
|
|
this->bbt_td = &bbt_main_descr;
|
|
|
|
this->bbt_md = &bbt_mirror_descr;
|
|
|
|
/* update flash based bbt */
|
|
|
|
this->options |= NAND_USE_FLASH_BBT;
|
|
|
|
}
|
2009-08-04 12:23:51 +00:00
|
|
|
|
2009-10-23 09:06:02 +00:00
|
|
|
/* first scan to find the device and get the page size */
|
|
|
|
if (nand_scan_ident(mtd, 1)) {
|
|
|
|
err = -ENXIO;
|
|
|
|
goto escan;
|
|
|
|
}
|
|
|
|
|
2009-11-24 11:21:35 +00:00
|
|
|
imx_nand_set_layout(mtd->writesize, pdata->width == 2 ? 16 : 8);
|
|
|
|
|
2009-10-23 09:06:02 +00:00
|
|
|
if (mtd->writesize == 2048) {
|
2009-10-26 11:18:35 +00:00
|
|
|
this->ecc.layout = oob_largepage;
|
2009-10-23 09:06:02 +00:00
|
|
|
host->pagesize_2k = 1;
|
2009-10-26 14:42:49 +00:00
|
|
|
if (nfc_is_v21()) {
|
|
|
|
tmp = readw(host->regs + NFC_SPAS);
|
|
|
|
tmp &= 0xff00;
|
|
|
|
tmp |= NFC_SPAS_64;
|
|
|
|
writew(tmp, host->regs + NFC_SPAS);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (nfc_is_v21()) {
|
|
|
|
tmp = readw(host->regs + NFC_SPAS);
|
|
|
|
tmp &= 0xff00;
|
|
|
|
tmp |= NFC_SPAS_16;
|
|
|
|
writew(tmp, host->regs + NFC_SPAS);
|
|
|
|
}
|
2009-10-23 09:06:02 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* second phase scan */
|
|
|
|
if (nand_scan_tail(mtd)) {
|
2008-08-12 15:05:17 +00:00
|
|
|
err = -ENXIO;
|
|
|
|
goto escan;
|
|
|
|
}
|
|
|
|
|
|
|
|
add_mtd_device(mtd);
|
|
|
|
|
|
|
|
dev->priv = host;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
escan:
|
|
|
|
kfree(host);
|
|
|
|
|
|
|
|
return err;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct driver_d imx_nand_driver = {
|
|
|
|
.name = "imx_nand",
|
|
|
|
.probe = imxnd_probe,
|
|
|
|
};
|
|
|
|
|
|
|
|
#ifdef CONFIG_NAND_IMX_BOOT
|
|
|
|
|
|
|
|
static void __nand_boot_init nfc_addr(struct imx_nand_host *host, u32 offs)
|
|
|
|
{
|
2009-10-26 10:52:15 +00:00
|
|
|
if (host->pagesize_2k) {
|
|
|
|
send_addr(host, offs & 0xff);
|
|
|
|
send_addr(host, offs & 0xff);
|
|
|
|
send_addr(host, (offs >> 11) & 0xff);
|
|
|
|
send_addr(host, (offs >> 19) & 0xff);
|
|
|
|
send_addr(host, (offs >> 27) & 0xff);
|
|
|
|
} else {
|
|
|
|
send_addr(host, offs & 0xff);
|
|
|
|
send_addr(host, (offs >> 9) & 0xff);
|
|
|
|
send_addr(host, (offs >> 17) & 0xff);
|
|
|
|
send_addr(host, (offs >> 25) & 0xff);
|
|
|
|
}
|
2008-08-12 15:05:17 +00:00
|
|
|
}
|
|
|
|
|
2009-10-23 11:43:36 +00:00
|
|
|
void __nand_boot_init imx_nand_load_image(void *dest, int size)
|
2008-08-12 15:05:17 +00:00
|
|
|
{
|
|
|
|
struct imx_nand_host host;
|
2009-10-23 11:43:36 +00:00
|
|
|
u32 tmp, page, block, blocksize, pagesize;
|
|
|
|
|
|
|
|
#ifdef CONFIG_ARCH_IMX27
|
|
|
|
tmp = readl(IMX_SYSTEM_CTL_BASE + 0x14);
|
|
|
|
if (tmp & (1 << 5))
|
|
|
|
host.pagesize_2k = 1;
|
|
|
|
else
|
|
|
|
host.pagesize_2k = 0;
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_IMX31
|
|
|
|
tmp = readl(IMX_CCM_BASE + CCM_RCSR);
|
|
|
|
if (tmp & RCSR_NFMS)
|
|
|
|
host.pagesize_2k = 1;
|
|
|
|
else
|
|
|
|
host.pagesize_2k = 0;
|
|
|
|
#endif
|
2009-10-26 14:43:18 +00:00
|
|
|
#ifdef CONFIG_ARCH_IMX35
|
|
|
|
if (readl(IMX_CCM_BASE + CCM_RCSR) & (1 << 8))
|
|
|
|
host.pagesize_2k = 1;
|
|
|
|
else
|
|
|
|
host.pagesize_2k = 0;
|
|
|
|
#endif
|
2009-10-23 11:43:36 +00:00
|
|
|
if (host.pagesize_2k) {
|
|
|
|
pagesize = 2048;
|
|
|
|
blocksize = 128 * 1024;
|
|
|
|
} else {
|
|
|
|
pagesize = 512;
|
|
|
|
blocksize = 16 * 1024;
|
|
|
|
}
|
2008-08-12 15:05:17 +00:00
|
|
|
|
2009-10-26 14:43:18 +00:00
|
|
|
host.base = (void __iomem *)IMX_NFC_BASE;
|
2009-10-26 11:18:35 +00:00
|
|
|
if (nfc_is_v21()) {
|
2009-10-26 14:43:18 +00:00
|
|
|
host.regs = host.base + 0x1000;
|
|
|
|
host.spare0 = host.base + 0x1000;
|
2009-10-26 11:18:35 +00:00
|
|
|
host.spare_len = 64;
|
|
|
|
} else if (nfc_is_v1()) {
|
2009-10-26 14:43:18 +00:00
|
|
|
host.regs = host.base;
|
|
|
|
host.spare0 = host.base + 0x800;
|
2009-10-26 11:18:35 +00:00
|
|
|
host.spare_len = 16;
|
|
|
|
}
|
2008-08-12 15:05:17 +00:00
|
|
|
|
|
|
|
send_cmd(&host, NAND_CMD_RESET);
|
|
|
|
|
|
|
|
/* preset operation */
|
|
|
|
/* Unlock the internal RAM Buffer */
|
|
|
|
writew(0x2, host.regs + NFC_CONFIG);
|
|
|
|
|
|
|
|
/* Unlock Block Command for given address range */
|
|
|
|
writew(0x4, host.regs + NFC_WRPROT);
|
|
|
|
|
|
|
|
tmp = readw(host.regs + NFC_CONFIG1);
|
2009-10-26 14:43:18 +00:00
|
|
|
tmp |= NFC_ECC_EN | NFC_INT_MSK;
|
|
|
|
if (nfc_is_v21())
|
|
|
|
/* currently no support for 218 byte OOB with stronger ECC */
|
|
|
|
tmp |= NFC_ECC_MODE;
|
2009-10-26 10:52:15 +00:00
|
|
|
tmp &= ~NFC_SP_EN;
|
2008-08-12 15:05:17 +00:00
|
|
|
writew(tmp, host.regs + NFC_CONFIG1);
|
|
|
|
|
2009-10-26 14:43:18 +00:00
|
|
|
if (nfc_is_v21()) {
|
|
|
|
if (host.pagesize_2k) {
|
|
|
|
tmp = readw(host.regs + NFC_SPAS);
|
|
|
|
tmp &= 0xff00;
|
|
|
|
tmp |= NFC_SPAS_64;
|
|
|
|
writew(tmp, host.regs + NFC_SPAS);
|
|
|
|
} else {
|
|
|
|
tmp = readw(host.regs + NFC_SPAS);
|
|
|
|
tmp &= 0xff00;
|
|
|
|
tmp |= NFC_SPAS_16;
|
|
|
|
writew(tmp, host.regs + NFC_SPAS);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-08-12 15:05:17 +00:00
|
|
|
block = page = 0;
|
|
|
|
|
|
|
|
while (1) {
|
2009-10-26 10:52:15 +00:00
|
|
|
page = 0;
|
|
|
|
while (page * pagesize < blocksize) {
|
|
|
|
debug("page: %d block: %d dest: %p src "
|
|
|
|
"0x%08x\n",
|
|
|
|
page, block, dest,
|
|
|
|
block * blocksize +
|
|
|
|
page * pagesize);
|
|
|
|
|
|
|
|
send_cmd(&host, NAND_CMD_READ0);
|
|
|
|
nfc_addr(&host, block * blocksize +
|
|
|
|
page * pagesize);
|
|
|
|
if (host.pagesize_2k)
|
|
|
|
send_cmd(&host, NAND_CMD_READSTART);
|
|
|
|
send_page(&host, NFC_OUTPUT);
|
|
|
|
page++;
|
|
|
|
|
|
|
|
if (host.pagesize_2k) {
|
2009-10-26 11:02:05 +00:00
|
|
|
if ((readw(host.spare0) & 0xff)
|
2009-10-26 10:52:15 +00:00
|
|
|
!= 0xff)
|
|
|
|
continue;
|
|
|
|
} else {
|
2009-10-26 11:02:05 +00:00
|
|
|
if ((readw(host.spare0 + 4) & 0xff00)
|
2009-10-26 10:52:15 +00:00
|
|
|
!= 0xff00)
|
|
|
|
continue;
|
2008-08-12 15:05:17 +00:00
|
|
|
}
|
2009-10-26 10:52:15 +00:00
|
|
|
|
2009-10-26 14:43:18 +00:00
|
|
|
memcpy32(dest, host.base, pagesize);
|
2009-10-26 10:52:15 +00:00
|
|
|
dest += pagesize;
|
|
|
|
size -= pagesize;
|
|
|
|
|
|
|
|
if (size <= 0)
|
|
|
|
return;
|
|
|
|
}
|
2008-08-12 15:05:17 +00:00
|
|
|
block++;
|
|
|
|
}
|
|
|
|
}
|
2009-04-09 11:18:51 +00:00
|
|
|
#define CONFIG_NAND_IMX_BOOT_DEBUG
|
|
|
|
#ifdef CONFIG_NAND_IMX_BOOT_DEBUG
|
|
|
|
#include <command.h>
|
|
|
|
|
|
|
|
static int do_nand_boot_test(cmd_tbl_t *cmdtp, int argc, char *argv[])
|
|
|
|
{
|
|
|
|
void *dest;
|
2009-10-23 11:43:36 +00:00
|
|
|
int size;
|
2009-04-09 11:18:51 +00:00
|
|
|
|
2009-10-23 11:43:36 +00:00
|
|
|
if (argc < 3)
|
2009-10-17 10:44:19 +00:00
|
|
|
return COMMAND_ERROR_USAGE;
|
2009-04-09 11:18:51 +00:00
|
|
|
|
|
|
|
dest = (void *)strtoul_suffix(argv[1], NULL, 0);
|
|
|
|
size = strtoul_suffix(argv[2], NULL, 0);
|
|
|
|
|
2009-10-23 11:43:36 +00:00
|
|
|
imx_nand_load_image(dest, size);
|
2009-04-09 11:18:51 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const __maybe_unused char cmd_nand_boot_test_help[] =
|
2009-10-23 11:43:36 +00:00
|
|
|
"Usage: nand_boot_test <dest> <size>\n";
|
2009-04-09 11:18:51 +00:00
|
|
|
|
2009-12-15 08:11:09 +00:00
|
|
|
BAREBOX_CMD_START(nand_boot_test)
|
2009-04-09 11:18:51 +00:00
|
|
|
.cmd = do_nand_boot_test,
|
|
|
|
.usage = "list a file or directory",
|
2009-12-15 08:11:09 +00:00
|
|
|
BAREBOX_CMD_HELP(cmd_nand_boot_test_help)
|
|
|
|
BAREBOX_CMD_END
|
2009-04-09 11:18:51 +00:00
|
|
|
#endif
|
|
|
|
|
2008-08-12 15:05:17 +00:00
|
|
|
#endif /* CONFIG_NAND_IMX_BOOT */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Main initialization routine
|
|
|
|
* @return 0 if successful; non-zero otherwise
|
|
|
|
*/
|
|
|
|
static int __init imx_nand_init(void)
|
|
|
|
{
|
|
|
|
return register_driver(&imx_nand_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
device_initcall(imx_nand_init);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Freescale Semiconductor, Inc.");
|
|
|
|
MODULE_DESCRIPTION("MXC NAND MTD driver");
|
|
|
|
MODULE_LICENSE("GPL");
|