2009-06-23 13:46:15 +00:00
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/*
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* Copyright (C) 2009 Juergen Beisert, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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/* S3C2410 device base addresses */
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#define S3C24X0_SDRAM_BASE 0x30000000
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#define S3C24X0_SDRAM_END 0x40000000
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#define S3C24X0_MEMCTL_BASE 0x48000000
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#define S3C2410_USB_HOST_BASE 0x49000000
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#define S3C2410_INTERRUPT_BASE 0x4A000000
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#define S3C2410_DMA_BASE 0x4B000000
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#define S3C24X0_CLOCK_POWER_BASE 0x4C000000
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#define S3C2410_LCD_BASE 0x4D000000
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#define S3C24X0_NAND_BASE 0x4E000000
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#define S3C24X0_UART_BASE 0x50000000
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#define S3C24X0_TIMER_BASE 0x51000000
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#define S3C2410_USB_DEVICE_BASE 0x52000140
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#define S3C24X0_WATCHDOG_BASE 0x53000000
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#define S3C2410_I2C_BASE 0x54000000
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#define S3C2410_I2S_BASE 0x55000000
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#define S3C24X0_GPIO_BASE 0x56000000
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#define S3C2410_RTC_BASE 0x57000000
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#define S3C2410_ADC_BASE 0x58000000
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#define S3C2410_SPI_BASE 0x59000000
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#define S3C2410_SDI_BASE 0x5A000000
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/* Clock control (direct access) */
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#define LOCKTIME (S3C24X0_CLOCK_POWER_BASE)
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#define MPLLCON (S3C24X0_CLOCK_POWER_BASE + 0x4)
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#define UPLLCON (S3C24X0_CLOCK_POWER_BASE + 0x8)
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#define CLKCON (S3C24X0_CLOCK_POWER_BASE + 0xc)
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#define CLKSLOW (S3C24X0_CLOCK_POWER_BASE + 0x10)
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#define CLKDIVN (S3C24X0_CLOCK_POWER_BASE + 0x14)
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/* Timer (direct access) */
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#define TCFG0 (S3C24X0_TIMER_BASE + 0x00)
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#define TCFG1 (S3C24X0_TIMER_BASE + 0x04)
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#define TCON (S3C24X0_TIMER_BASE + 0x08)
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#define TCNTB0 (S3C24X0_TIMER_BASE + 0x0c)
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#define TCMPB0 (S3C24X0_TIMER_BASE + 0x10)
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#define TCNTO0 (S3C24X0_TIMER_BASE + 0x14)
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#define TCNTB1 (S3C24X0_TIMER_BASE + 0x18)
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#define TCMPB1 (S3C24X0_TIMER_BASE + 0x1c)
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#define TCNTO1 (S3C24X0_TIMER_BASE + 0x20)
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#define TCNTB2 (S3C24X0_TIMER_BASE + 0x24)
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#define TCMPB2 (S3C24X0_TIMER_BASE + 0x28)
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#define TCNTO2 (S3C24X0_TIMER_BASE + 0x2c)
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#define TCNTB3 (S3C24X0_TIMER_BASE + 0x30)
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#define TCMPB3 (S3C24X0_TIMER_BASE + 0x34)
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#define TCNTO3 (S3C24X0_TIMER_BASE + 0x38)
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#define TCNTB4 (S3C24X0_TIMER_BASE + 0x3c)
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#define TCNTO4 (S3C24X0_TIMER_BASE + 0x40)
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/* Watchdog (direct access) */
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#define WTCON (S3C24X0_WATCHDOG_BASE)
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#define WTDAT (S3C24X0_WATCHDOG_BASE + 0x04)
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#define WTCNT (S3C24X0_WATCHDOG_BASE + 0x08)
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/*
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* if we are booting from NAND, its internal SRAM occures at
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* a different address than without this feature
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*/
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#ifdef CONFIG_S3C24XX_NAND_BOOT
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# define NFC_RAM_AREA 0x00000000
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#else
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# define NFC_RAM_AREA 0x40000000
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#endif
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#define NFC_RAM_SIZE 4096
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/* internal UARTs (driver based) */
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#define UART1_BASE (S3C24X0_UART_BASE)
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#define UART1_SIZE 0x4000
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#define UART2_BASE (S3C24X0_UART_BASE + 0x4000)
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2011-02-16 18:13:27 +00:00
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#define UART2_SIZE 0x4000
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2009-06-23 13:46:15 +00:00
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#define UART3_BASE (S3C24X0_UART_BASE + 0x8000)
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#define UART3_SIZE 0x4000
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/* CS configuration (direct access) */
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#define BWSCON (S3C24X0_MEMCTL_BASE)
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#define BANKCON0 (S3C24X0_MEMCTL_BASE + 0x04)
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#define BANKCON1 (S3C24X0_MEMCTL_BASE + 0x08)
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#define BANKCON2 (S3C24X0_MEMCTL_BASE + 0x0c)
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#define BANKCON3 (S3C24X0_MEMCTL_BASE + 0x10)
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#define BANKCON4 (S3C24X0_MEMCTL_BASE + 0x14)
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#define BANKCON5 (S3C24X0_MEMCTL_BASE + 0x18)
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#define BANKCON6 (S3C24X0_MEMCTL_BASE + 0x1c)
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#define BANKCON7 (S3C24X0_MEMCTL_BASE + 0x20)
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#define REFRESH (S3C24X0_MEMCTL_BASE + 0x24)
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#define BANKSIZE (S3C24X0_MEMCTL_BASE + 0x28)
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#define MRSRB6 (S3C24X0_MEMCTL_BASE + 0x2c)
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#define MRSRB7 (S3C24X0_MEMCTL_BASE + 0x30)
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/* GPIO registers (direct access) */
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#define GPACON (S3C24X0_GPIO_BASE)
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#define GPADAT (S3C24X0_GPIO_BASE + 0x04)
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#define GPBCON (S3C24X0_GPIO_BASE + 0x10)
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#define GPBDAT (S3C24X0_GPIO_BASE + 0x14)
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#define GPBUP (S3C24X0_GPIO_BASE + 0x18)
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#define GPCCON (S3C24X0_GPIO_BASE + 0x20)
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#define GPCDAT (S3C24X0_GPIO_BASE + 0x24)
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#define GPCUP (S3C24X0_GPIO_BASE + 0x28)
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#define GPDCON (S3C24X0_GPIO_BASE + 0x30)
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#define GPDDAT (S3C24X0_GPIO_BASE + 0x34)
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#define GPDUP (S3C24X0_GPIO_BASE + 0x38)
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#define GPECON (S3C24X0_GPIO_BASE + 0x40)
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#define GPEDAT (S3C24X0_GPIO_BASE + 0x44)
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#define GPEUP (S3C24X0_GPIO_BASE + 0x48)
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#define GPFCON (S3C24X0_GPIO_BASE + 0x50)
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#define GPFDAT (S3C24X0_GPIO_BASE + 0x54)
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#define GPFUP (S3C24X0_GPIO_BASE + 0x58)
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#define GPGCON (S3C24X0_GPIO_BASE + 0x60)
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#define GPGDAT (S3C24X0_GPIO_BASE + 0x64)
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#define GPGUP (S3C24X0_GPIO_BASE + 0x68)
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#define GPHCON (S3C24X0_GPIO_BASE + 0x70)
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#define GPHDAT (S3C24X0_GPIO_BASE + 0x74)
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#define GPHUP (S3C24X0_GPIO_BASE + 0x78)
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#ifdef CONFIG_CPU_S3C2440
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# define GPJCON (S3C24X0_GPIO_BASE + 0xd0)
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# define GPJDAT (S3C24X0_GPIO_BASE + 0xd4)
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# define GPJUP (S3C24X0_GPIO_BASE + 0xd8)
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#endif
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#define MISCCR (S3C24X0_GPIO_BASE + 0x80)
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#define DCLKCON (S3C24X0_GPIO_BASE + 0x84)
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#define EXTINT0 (S3C24X0_GPIO_BASE + 0x88)
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#define EXTINT1 (S3C24X0_GPIO_BASE + 0x8c)
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#define EXTINT2 (S3C24X0_GPIO_BASE + 0x90)
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#define EINTFLT0 (S3C24X0_GPIO_BASE + 0x94)
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#define EINTFLT1 (S3C24X0_GPIO_BASE + 0x98)
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#define EINTFLT2 (S3C24X0_GPIO_BASE + 0x9c)
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#define EINTFLT3 (S3C24X0_GPIO_BASE + 0xa0)
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#define EINTMASK (S3C24X0_GPIO_BASE + 0xa4)
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#define EINTPEND (S3C24X0_GPIO_BASE + 0xa8)
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#define GSTATUS0 (S3C24X0_GPIO_BASE + 0xac)
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#define GSTATUS1 (S3C24X0_GPIO_BASE + 0xb0)
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#define GSTATUS2 (S3C24X0_GPIO_BASE + 0xb4)
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#define GSTATUS3 (S3C24X0_GPIO_BASE + 0xb8)
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#define GSTATUS4 (S3C24X0_GPIO_BASE + 0xbc)
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#ifdef CONFIG_CPU_S3C2440
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# define DSC0 (S3C24X0_GPIO_BASE + 0xc4)
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# define DSC1 (S3C24X0_GPIO_BASE + 0xc8)
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#endif
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/* external IO space */
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#define CS0_BASE 0x00000000
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#define CS1_BASE 0x08000000
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#define CS2_BASE 0x10000000
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#define CS3_BASE 0x18000000
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#define CS4_BASE 0x20000000
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#define CS5_BASE 0x28000000
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#define CS6_BASE 0x30000000
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