2012-06-14 06:59:38 +00:00
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/*
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* (C) Copyright 2009-2010 Digi International, Inc.
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* Copyright (C) 2007 Sascha Hauer, Pengutronix
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* (c) 2011 Eukrea Electromatique, Eric Bénard <eric@eukrea.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <net.h>
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#include <init.h>
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#include <environment.h>
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2012-10-11 07:09:29 +00:00
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#include <mach/imx51-regs.h>
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2012-06-14 06:59:38 +00:00
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#include <fec.h>
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#include <mach/gpio.h>
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#include <asm/armlinux.h>
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#include <generated/mach-types.h>
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#include <partition.h>
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#include <fs.h>
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#include <fcntl.h>
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#include <sizes.h>
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#include <nand.h>
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#include <notifier.h>
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#include <spi/spi.h>
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#include <mfd/mc13xxx.h>
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#include <asm/io.h>
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#include <mach/imx-nand.h>
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#include <mach/spi.h>
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#include <mach/generic.h>
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#include <mach/iomux-mx51.h>
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#include <mach/devices-imx51.h>
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#include <mach/iim.h>
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#include <mach/clock-imx51_53.h>
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#include <mach/imx5.h>
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2012-09-30 16:14:08 +00:00
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#include <mach/revision.h>
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2012-06-14 06:59:38 +00:00
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#include "ccxmx51.h"
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static struct ccxmx51_ident ccxmx51_ids[] = {
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2013-01-22 11:08:31 +00:00
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/* 0x00 */ { "Unknown", 0, 0, 0, 0 },
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/* 0x01 */ { "Not supported", 0, 0, 0, 0 },
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/* 0x02 */ { "i.MX515@800MHz, Wireless, PHY, Ext. Eth, Accel", 0, 1, 1, 1 },
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/* 0x03 */ { "i.MX515@800MHz, PHY, Ext. Eth, Accel", 0, 1, 1, 0 },
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/* 0x04 */ { "i.MX515@600MHz, Wireless, PHY, Ext. Eth, Accel", 1, 1, 1, 1 },
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/* 0x05 */ { "i.MX515@600MHz, PHY, Ext. Eth, Accel", 1, 1, 1, 0 },
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/* 0x06 */ { "i.MX515@800MHz, Wireless, PHY, Accel", 0, 1, 0, 1 },
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/* 0x07 */ { "i.MX515@800MHz, PHY, Accel", 0, 1, 0, 0 },
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/* 0x08 */ { "i.MX515@800MHz, Wireless, PHY, Accel", 0, 1, 0, 1 },
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/* 0x09 */ { "i.MX515@800MHz, PHY, Accel", 0, 1, 0, 0 },
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/* 0x0a */ { "i.MX515@600MHz, Wireless, PHY, Accel", 1, 1, 0, 1 },
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/* 0x0b */ { "i.MX515@600MHz, PHY, Accel", 1, 1, 0, 0 },
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/* 0x0c */ { "i.MX515@800MHz, Wireless, PHY, Accel", 0, 1, 0, 1 },
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/* 0x0d */ { "i.MX512@800MHz", 0, 0, 0, 0 },
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/* 0x0e */ { "i.MX515@800MHz, Wireless, PHY, Accel", 0, 1, 0, 1 },
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/* 0x0f */ { "i.MX515@600MHz, PHY, Accel", 1, 1, 0, 0 },
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/* 0x10 */ { "i.MX515@600MHz, Wireless, PHY, Accel", 1, 1, 0, 1 },
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/* 0x11 */ { "i.MX515@800MHz, PHY, Accel", 0, 1, 0, 0 },
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/* 0x12 */ { "i.MX515@600MHz, Wireless, PHY, Accel", 1, 1, 0, 1 },
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/* 0x13 */ { "i.MX515@800MHz, PHY, Accel", 0, 1, 0, 0 },
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2012-06-14 06:59:38 +00:00
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};
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struct ccxmx51_ident *ccxmx51_id;
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struct imx_nand_platform_data nand_info = {
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.width = 1,
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.hw_ecc = 1,
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.flash_bbt = 1,
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};
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#ifdef CONFIG_DRIVER_NET_FEC_IMX
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static struct fec_platform_data fec_info = {
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.xcv_type = MII100,
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.phy_addr = 7,
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};
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#endif
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static iomux_v3_cfg_t ccxmx51_pads[] = {
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/* UART1 */
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MX51_PAD_UART1_RXD__UART1_RXD,
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MX51_PAD_UART1_TXD__UART1_TXD,
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/* UART2 */
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MX51_PAD_UART2_RXD__UART2_RXD,
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MX51_PAD_UART2_TXD__UART2_TXD,
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/* UART3 */
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MX51_PAD_UART3_RXD__UART3_RXD,
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MX51_PAD_UART3_TXD__UART3_TXD,
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/* I2C2 */
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MX51_PAD_GPIO1_2__I2C2_SCL,
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MX51_PAD_GPIO1_3__I2C2_SDA,
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/* eCSPI1 */
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MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
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MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
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MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
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MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
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MX51_PAD_CSPI1_SS0__ECSPI1_SS0,
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MX51_PAD_CSPI1_SS1__ECSPI1_SS1,
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/* FEC */
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MX51_PAD_DISP2_DAT14__FEC_RDATA0,
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MX51_PAD_DI2_DISP_CLK__FEC_RDATA1,
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MX51_PAD_DI_GP4__FEC_RDATA2,
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MX51_PAD_DISP2_DAT0__FEC_RDATA3,
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MX51_PAD_DISP2_DAT15__FEC_TDATA0,
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MX51_PAD_DISP2_DAT6__FEC_TDATA1,
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MX51_PAD_DISP2_DAT7__FEC_TDATA2,
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MX51_PAD_DISP2_DAT8__FEC_TDATA3,
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MX51_PAD_DISP2_DAT9__FEC_TX_EN,
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MX51_PAD_DISP2_DAT10__FEC_COL,
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MX51_PAD_DISP2_DAT11__FEC_RX_CLK,
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MX51_PAD_DISP2_DAT12__FEC_RX_DV,
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MX51_PAD_DISP2_DAT13__FEC_TX_CLK,
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MX51_PAD_DI2_PIN2__FEC_MDC,
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MX51_PAD_DI2_PIN4__FEC_CRS,
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MX51_PAD_DI2_PIN3__FEC_MDIO,
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MX51_PAD_DI_GP3__FEC_TX_ER,
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MX51_PAD_DISP2_DAT1__FEC_RX_ER,
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/* WEIM */
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MX51_PAD_EIM_DA0__EIM_DA0,
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MX51_PAD_EIM_DA1__EIM_DA1,
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MX51_PAD_EIM_DA2__EIM_DA2,
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MX51_PAD_EIM_DA3__EIM_DA3,
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MX51_PAD_EIM_DA4__EIM_DA4,
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MX51_PAD_EIM_DA5__EIM_DA5,
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MX51_PAD_EIM_DA6__EIM_DA6,
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MX51_PAD_EIM_DA7__EIM_DA7,
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MX51_PAD_EIM_D16__EIM_D16,
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MX51_PAD_EIM_D17__EIM_D17,
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MX51_PAD_EIM_D18__EIM_D18,
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MX51_PAD_EIM_D19__EIM_D19,
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MX51_PAD_EIM_D20__EIM_D20,
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MX51_PAD_EIM_D21__EIM_D21,
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MX51_PAD_EIM_D22__EIM_D22,
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MX51_PAD_EIM_D23__EIM_D23,
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MX51_PAD_EIM_D24__EIM_D24,
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MX51_PAD_EIM_D25__EIM_D25,
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MX51_PAD_EIM_D26__EIM_D26,
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MX51_PAD_EIM_D27__EIM_D27,
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MX51_PAD_EIM_D28__EIM_D28,
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MX51_PAD_EIM_D29__EIM_D29,
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MX51_PAD_EIM_D30__EIM_D30,
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MX51_PAD_EIM_D31__EIM_D31,
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MX51_PAD_EIM_OE__EIM_OE,
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MX51_PAD_EIM_CS5__EIM_CS5,
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/* NAND */
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MX51_PAD_NANDF_D0__NANDF_D0,
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MX51_PAD_NANDF_D1__NANDF_D1,
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MX51_PAD_NANDF_D2__NANDF_D2,
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MX51_PAD_NANDF_D3__NANDF_D3,
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MX51_PAD_NANDF_D4__NANDF_D4,
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MX51_PAD_NANDF_D5__NANDF_D5,
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MX51_PAD_NANDF_D6__NANDF_D6,
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MX51_PAD_NANDF_D7__NANDF_D7,
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MX51_PAD_NANDF_ALE__NANDF_ALE,
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MX51_PAD_NANDF_CLE__NANDF_CLE,
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MX51_PAD_NANDF_RE_B__NANDF_RE_B,
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MX51_PAD_NANDF_WE_B__NANDF_WE_B,
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MX51_PAD_NANDF_WP_B__NANDF_WP_B,
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MX51_PAD_NANDF_CS0__NANDF_CS0,
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MX51_PAD_NANDF_RB0__NANDF_RB0,
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/* LAN9221 IRQ (GPIO1.9) */
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MX51_PAD_GPIO1_9__GPIO1_9,
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/* MC13892 IRQ (GPIO1.5) */
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MX51_PAD_GPIO1_5__GPIO1_5,
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/* MMA7455LR IRQ1 (GPIO1.7) */
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MX51_PAD_GPIO1_7__GPIO1_7,
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/* MMA7455LR IRQ2 (GPIO1.6) */
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MX51_PAD_GPIO1_6__GPIO1_6,
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};
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#define CCXMX51_ECSPI1_CS0 IMX_GPIO_NR(4, 24)
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#define CCXMX51_ECSPI1_CS1 IMX_GPIO_NR(4, 25)
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static int ecspi_0_cs[] = { CCXMX51_ECSPI1_CS0, CCXMX51_ECSPI1_CS1, };
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static struct spi_imx_master ecspi_0_data = {
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.chipselect = ecspi_0_cs,
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.num_chipselect = ARRAY_SIZE(ecspi_0_cs),
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};
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static const struct spi_board_info ccxmx51_spi_board_info[] = {
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{
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.name = "mc13xxx-spi",
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.bus_num = 0,
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.chip_select = 0,
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},
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};
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static void ccxmx51_otghost_init(void)
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{
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#define MX51_USBOTHER_REGS_OFFSET 0x800
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#define MX51_USBCTRL_OFFSET 0x0
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#define MX51_USB_PHY_CTR_FUNC_OFFSET 0x8
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#define MX51_USB_PHY_CTR_FUNC2_OFFSET 0xc
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#define MX51_USB_UTMI_PHYCTRL1_PLLDIV_MASK 0x3
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#define MX51_USB_PLL_DIV_19_2_MHZ 0x00
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#define MX51_USB_PLL_DIV_24_MHZ 0x01
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#define MX51_USB_PLL_DIV_26_MHZ 0x02
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#define MX51_USB_PLL_DIV_27_MHZ 0x03
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#define MX51_OTG_PHYCTRL_OC_DIS_BIT (1 << 8)
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#define MX51_OTG_UCTRL_OWIE_BIT (1 << 27)
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#define MX51_OTG_UCTRL_OPM_BIT (1 << 24)
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#define USBOTHER_BASE (MX51_OTG_BASE_ADDR + MX51_USBOTHER_REGS_OFFSET)
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u32 reg;
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/* Set sysclock to 24 MHz */
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reg = readl(USBOTHER_BASE + MX51_USB_PHY_CTR_FUNC2_OFFSET);
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reg &= ~MX51_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
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reg |= MX51_USB_PLL_DIV_24_MHZ;
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writel(reg, USBOTHER_BASE + MX51_USB_PHY_CTR_FUNC2_OFFSET);
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/* OC is not used */
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reg = readl(USBOTHER_BASE + MX51_USB_PHY_CTR_FUNC_OFFSET);
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reg |= MX51_OTG_PHYCTRL_OC_DIS_BIT;
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writel(reg, USBOTHER_BASE + MX51_USB_PHY_CTR_FUNC_OFFSET);
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/* Power pins enable */
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reg = readl(USBOTHER_BASE + MX51_USBCTRL_OFFSET);
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reg |= MX51_OTG_UCTRL_OWIE_BIT | MX51_OTG_UCTRL_OPM_BIT;
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writel(reg, USBOTHER_BASE + MX51_USBCTRL_OFFSET);
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/* Setup PORTSC */
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reg = readl(MX51_OTG_BASE_ADDR + 0x184);
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reg &= ~(3 << 30);
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reg |= 1 << 28;
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writel(reg, MX51_OTG_BASE_ADDR + 0x184);
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mdelay(10);
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add_generic_usb_ehci_device(0, MX51_OTG_BASE_ADDR, NULL);
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}
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static int ccxmx51_power_init(void)
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{
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struct mc13xxx *mc13xxx_dev;
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u32 val;
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mc13xxx_dev = mc13xxx_get();
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if (!mc13xxx_dev)
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return -ENODEV;
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mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_POWER_MISC, &val);
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/* Reset devices by clearing GP01-GPO4 */
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val &= ~((1 << 21) | (3 << 12) | (3 << 10) | (3 << 8) | (3 << 6));
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/* Switching off the PWGT1SPIEN */
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val |= (1 << 15);
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/* Switching on the PWGT2SPIEN */
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val &= ~(1 << 16);
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/* Enable short circuit protection */
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val |= (1 << 0);
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mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_POWER_MISC, val);
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/* Allow charger to charge (4.2V and 560mA) */
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val = 0x238033;
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mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_CHARGE, val);
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/* Set core voltage (SW1) to 1.1V */
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mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_0, &val);
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val &= ~0x00001f;
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val |= 0x000014;
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mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_0, val);
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if (imx_silicon_revision() < IMX_CHIP_REV_3_0) {
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/* Setup VCC (SW2) to 1.25 */
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mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_1, &val);
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val &= ~0x00001f;
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val |= 0x00001a;
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mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_1, val);
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/* Setup 1V2_DIG1 (SW3) to 1.25 */
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mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_2, &val);
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val &= ~0x00001f;
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val |= 0x00001a;
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mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_2, val);
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} else {
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/* Setup VCC (SW2) to 1.225 */
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mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_1, &val);
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val &= ~0x00001f;
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val |= 0x000019;
|
|
|
|
mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_1, val);
|
|
|
|
|
|
|
|
/* Setup 1V2_DIG1 (SW3) to 1.2 */
|
|
|
|
mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_2, &val);
|
|
|
|
val &= ~0x00001f;
|
|
|
|
val |= 0x000018;
|
|
|
|
mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_2, val);
|
|
|
|
}
|
|
|
|
|
2012-08-04 09:15:53 +00:00
|
|
|
if (mc13xxx_revision(mc13xxx_dev) <= MC13892_REVISION_2_0) {
|
2012-06-14 06:59:38 +00:00
|
|
|
/* Set switchers in PWM mode for Atlas 2.0 and lower */
|
|
|
|
/* Setup the switcher mode for SW1 & SW2*/
|
|
|
|
mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_4, &val);
|
|
|
|
val &= ~0x003c0f;
|
|
|
|
val |= 0x001405;
|
|
|
|
mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_4, val);
|
|
|
|
|
|
|
|
/* Setup the switcher mode for SW3 & SW4 */
|
|
|
|
mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_5, &val);
|
|
|
|
val &= ~0x000f0f;
|
|
|
|
val |= 0x000505;
|
|
|
|
mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_5, val);
|
|
|
|
} else {
|
|
|
|
/* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */
|
|
|
|
/* Setup the switcher mode for SW1 & SW2*/
|
|
|
|
mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_4, &val);
|
|
|
|
val &= ~0x003c0f;
|
|
|
|
val |= 0x002008;
|
|
|
|
mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_4, val);
|
|
|
|
|
|
|
|
/* Setup the switcher mode for SW3 & SW4 */
|
|
|
|
mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_5, &val);
|
|
|
|
val &= ~0x000f0f;
|
|
|
|
val |= 0x000808;
|
|
|
|
mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_5, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
|
|
|
|
mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SETTING_1, &val);
|
|
|
|
val &= ~0x0001fc;
|
|
|
|
val |= 0x0001f4;
|
|
|
|
mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SETTING_1, val);
|
|
|
|
|
|
|
|
/* Configure VGEN3 and VCAM regulators to use external PNP */
|
|
|
|
val = 0x000208;
|
|
|
|
mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_MODE_1, val);
|
|
|
|
udelay(200);
|
|
|
|
|
|
|
|
/* Set VGEN3 to 1.8V */
|
|
|
|
mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SETTING_0, &val);
|
|
|
|
val &= ~(1 << 14);
|
|
|
|
mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SETTING_0, val);
|
|
|
|
|
|
|
|
/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
|
|
|
|
val = 0x049249;
|
|
|
|
mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_MODE_1, val);
|
|
|
|
|
|
|
|
/* Enable USB1 charger */
|
|
|
|
val = 0x000409;
|
|
|
|
mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_USB1, val);
|
|
|
|
|
|
|
|
/* Set VCOIN to 3.0V and Enable It */
|
|
|
|
mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_POWER_CTL0, &val);
|
|
|
|
val &= ~(7 << 20);
|
|
|
|
val |= (4 << 20) | (1 << 23);
|
|
|
|
mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_POWER_CTL0, val);
|
|
|
|
/* Keeps VSRTC and CLK32KMCU */
|
|
|
|
val |= (1 << 4);
|
|
|
|
mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_POWER_CTL0, val);
|
|
|
|
|
|
|
|
/* De-assert reset of external devices on GP01, GPO2, GPO3 and GPO4 */
|
|
|
|
mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_POWER_MISC, &val);
|
|
|
|
/* GPO1 - External */
|
|
|
|
/* GP02 - LAN9221 */
|
|
|
|
/* GP03 - FEC */
|
|
|
|
/* GP04 - Wireless */
|
|
|
|
if (IS_ENABLED(CONFIG_DRIVER_NET_SMC911X) && ccxmx51_id->eth0)
|
|
|
|
val |= (1 << 8);
|
|
|
|
if (IS_ENABLED(CONFIG_DRIVER_NET_FEC_IMX) && ccxmx51_id->eth1)
|
|
|
|
val |= (1 << 10);
|
|
|
|
if (ccxmx51_id->wless)
|
|
|
|
val |= (1 << 12);
|
|
|
|
mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_POWER_MISC, val);
|
|
|
|
|
|
|
|
udelay(100);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ccxmx51_devices_init(void)
|
|
|
|
{
|
|
|
|
u8 hwid[6];
|
|
|
|
int pwr;
|
|
|
|
char manloc;
|
|
|
|
|
|
|
|
if ((imx_iim_read(1, 9, hwid, sizeof(hwid)) != sizeof(hwid)) || (hwid[0] < 0x02) || (hwid[0] >= ARRAY_SIZE(ccxmx51_ids)))
|
|
|
|
memset(hwid, 0x00, sizeof(hwid));
|
|
|
|
|
|
|
|
ccxmx51_id = &ccxmx51_ids[hwid[0]];
|
|
|
|
printf("Module Variant: %s (0x%02x)\n", ccxmx51_id->id_string, hwid[0]);
|
|
|
|
|
|
|
|
if (hwid[0]) {
|
|
|
|
printf("Module HW Rev : %02x\n", hwid[1]);
|
|
|
|
switch (hwid[2] & 0xc0) {
|
|
|
|
case 0x00:
|
|
|
|
manloc = 'B';
|
|
|
|
break;
|
|
|
|
case 0x40:
|
|
|
|
manloc = 'W';
|
|
|
|
break;
|
|
|
|
case 0x80:
|
|
|
|
manloc = 'S';
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
manloc = 'N';
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
printf("Module Serial : %c%d\n", manloc, ((hwid[2] & 0x3f) << 24) | (hwid[3] << 16) | (hwid[4] << 8) | hwid[5]);
|
|
|
|
}
|
|
|
|
|
|
|
|
imx51_add_uart1();
|
|
|
|
imx51_add_uart2();
|
|
|
|
|
|
|
|
spi_register_board_info(ccxmx51_spi_board_info, ARRAY_SIZE(ccxmx51_spi_board_info));
|
|
|
|
imx51_add_spi0(&ecspi_0_data);
|
|
|
|
|
|
|
|
pwr = ccxmx51_power_init();
|
|
|
|
console_flush();
|
|
|
|
imx51_init_lowlevel((ccxmx51_id->industrial || pwr) ? 600 : 800);
|
|
|
|
clock_notifier_call_chain();
|
|
|
|
if (pwr)
|
|
|
|
printf("Could not setup PMIC. Clocks not adjusted.\n");
|
|
|
|
|
|
|
|
imx51_add_i2c1(NULL);
|
|
|
|
|
|
|
|
imx51_add_nand(&nand_info);
|
|
|
|
devfs_add_partition("nand0", 0x00000, 0x80000, DEVFS_PARTITION_FIXED, "self_raw");
|
|
|
|
dev_add_bb_dev("self_raw", "self0");
|
|
|
|
devfs_add_partition("nand0", 0x80000, 0x40000, DEVFS_PARTITION_FIXED, "env_raw");
|
|
|
|
dev_add_bb_dev("env_raw", "env0");
|
|
|
|
|
|
|
|
#ifdef CONFIG_DRIVER_NET_FEC_IMX
|
|
|
|
if (ccxmx51_id->eth0 && !pwr) {
|
|
|
|
imx51_add_fec(&fec_info);
|
|
|
|
eth_register_ethaddr(0, hwid);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_DRIVER_NET_SMC911X
|
|
|
|
if (ccxmx51_id->eth1 && !pwr) {
|
|
|
|
/* Configure the WEIM CS5 timming, bus width, etc */
|
|
|
|
/* 16 bit on DATA[31..16], not multiplexed, async */
|
|
|
|
writel(0x00420081, MX51_WEIM_BASE_ADDR + WEIM_CSxGCR1(5));
|
|
|
|
/* ADH has not effect on non muxed bus */
|
|
|
|
writel(0, MX51_WEIM_BASE_ADDR + WEIM_CSxGCR2(5));
|
|
|
|
/* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
|
|
|
|
writel(0x32260000, MX51_WEIM_BASE_ADDR + WEIM_CSxRCR1(5));
|
|
|
|
/* APR=0 */
|
|
|
|
writel(0, MX51_WEIM_BASE_ADDR + WEIM_CSxRCR2(5));
|
|
|
|
/* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0, WCSA=0 */
|
|
|
|
writel(0x72080f00, MX51_WEIM_BASE_ADDR + WEIM_CSxWCR1(5));
|
|
|
|
|
|
|
|
/* LAN9221 network controller */
|
|
|
|
add_generic_device("smc911x", 1, NULL, MX51_CS5_BASE_ADDR, SZ_4K, IORESOURCE_MEM, NULL);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
ccxmx51_otghost_init();
|
|
|
|
|
|
|
|
armlinux_set_bootparams((void *)(MX51_CSD0_BASE_ADDR + 0x100));
|
|
|
|
|
|
|
|
armlinux_set_architecture(ccxmx51_id->wless ? MACH_TYPE_CCWMX51 : MACH_TYPE_CCMX51);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
device_initcall(ccxmx51_devices_init);
|
|
|
|
|
|
|
|
static int ccxmx51_console_init(void)
|
|
|
|
{
|
|
|
|
mxc_iomux_v3_setup_multiple_pads(ccxmx51_pads, ARRAY_SIZE(ccxmx51_pads));
|
|
|
|
|
|
|
|
imx51_add_uart0();
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
console_initcall(ccxmx51_console_init);
|