2010-03-26 15:08:21 +00:00
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#include <common.h>
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#include <init.h>
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2011-09-22 17:02:57 +00:00
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#include <io.h>
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2010-03-26 15:08:21 +00:00
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#include <asm/mmu.h>
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2013-02-11 17:01:29 +00:00
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#include <asm/cache-l2x0.h>
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2010-03-26 15:08:21 +00:00
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#define CACHE_LINE_SIZE 32
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static void __iomem *l2x0_base;
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static inline void cache_wait(void __iomem *reg, unsigned long mask)
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{
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/* wait for the operation to complete */
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while (readl(reg) & mask)
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;
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}
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static inline void cache_sync(void)
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{
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void __iomem *base = l2x0_base;
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writel(0, base + L2X0_CACHE_SYNC);
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cache_wait(base + L2X0_CACHE_SYNC, 1);
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}
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static inline void l2x0_clean_line(unsigned long addr)
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{
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void __iomem *base = l2x0_base;
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cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
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writel(addr, base + L2X0_CLEAN_LINE_PA);
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}
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static inline void l2x0_inv_line(unsigned long addr)
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{
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void __iomem *base = l2x0_base;
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cache_wait(base + L2X0_INV_LINE_PA, 1);
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writel(addr, base + L2X0_INV_LINE_PA);
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}
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static inline void l2x0_flush_line(unsigned long addr)
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{
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void __iomem *base = l2x0_base;
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/* Clean by PA followed by Invalidate by PA */
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cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
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writel(addr, base + L2X0_CLEAN_LINE_PA);
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cache_wait(base + L2X0_INV_LINE_PA, 1);
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writel(addr, base + L2X0_INV_LINE_PA);
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}
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static inline void l2x0_inv_all(void)
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{
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/* invalidate all ways */
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writel(0xff, l2x0_base + L2X0_INV_WAY);
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cache_wait(l2x0_base + L2X0_INV_WAY, 0xff);
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cache_sync();
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}
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static void l2x0_inv_range(unsigned long start, unsigned long end)
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{
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if (start & (CACHE_LINE_SIZE - 1)) {
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start &= ~(CACHE_LINE_SIZE - 1);
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l2x0_flush_line(start);
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start += CACHE_LINE_SIZE;
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}
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if (end & (CACHE_LINE_SIZE - 1)) {
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end &= ~(CACHE_LINE_SIZE - 1);
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l2x0_flush_line(end);
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}
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while (start < end) {
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unsigned long blk_end = start + min(end - start, 4096UL);
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while (start < blk_end) {
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l2x0_inv_line(start);
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start += CACHE_LINE_SIZE;
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}
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}
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cache_wait(l2x0_base + L2X0_INV_LINE_PA, 1);
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cache_sync();
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}
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static void l2x0_clean_range(unsigned long start, unsigned long end)
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{
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void __iomem *base = l2x0_base;
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start &= ~(CACHE_LINE_SIZE - 1);
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while (start < end) {
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unsigned long blk_end = start + min(end - start, 4096UL);
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while (start < blk_end) {
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l2x0_clean_line(start);
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start += CACHE_LINE_SIZE;
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}
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}
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cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
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cache_sync();
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}
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2010-10-15 06:28:42 +00:00
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static void l2x0_flush_range(unsigned long start, unsigned long end)
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2010-03-26 15:08:21 +00:00
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{
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start &= ~(CACHE_LINE_SIZE - 1);
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while (start < end) {
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unsigned long blk_end = start + min(end - start, 4096UL);
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while (start < blk_end) {
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l2x0_flush_line(start);
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start += CACHE_LINE_SIZE;
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}
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}
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cache_wait(l2x0_base + L2X0_CLEAN_INV_LINE_PA, 1);
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cache_sync();
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}
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static void l2x0_disable(void)
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{
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writel(0xff, l2x0_base + L2X0_CLEAN_INV_WAY);
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while (readl(l2x0_base + L2X0_CLEAN_INV_WAY));
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writel(0, l2x0_base + L2X0_CTRL);
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}
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void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
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{
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__u32 aux;
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l2x0_base = base;
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/*
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* Check if l2x0 controller is already enabled.
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* If you are booting from non-secure mode
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* accessing the below registers will fault.
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*/
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if (!(readl(l2x0_base + L2X0_CTRL) & 1)) {
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/* l2x0 controller is disabled */
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aux = readl(l2x0_base + L2X0_AUX_CTRL);
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aux &= aux_mask;
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aux |= aux_val;
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writel(aux, l2x0_base + L2X0_AUX_CTRL);
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l2x0_inv_all();
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/* enable L2X0 */
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writel(1, l2x0_base + L2X0_CTRL);
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}
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outer_cache.inv_range = l2x0_inv_range;
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outer_cache.clean_range = l2x0_clean_range;
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outer_cache.flush_range = l2x0_flush_range;
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outer_cache.disable = l2x0_disable;
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}
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