95 lines
2.6 KiB
C
95 lines
2.6 KiB
C
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/**
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* @file
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* @brief Serial NS16550 header
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*
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* FileName: drivers/serial/serial_ns16550.h
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*
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* @code struct NS16550 @endcode
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* Register definitions for NS16550 device
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*/
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/*
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* This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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* NS16550 Serial Port
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* originally from linux source (arch/ppc/boot/ns16550.h)
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* modified slightly to
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* have addresses as offsets from CFG_ISA_BASE
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* added a few more definitions
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* added prototypes for ns16550.c
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* reduced no of com ports to 2
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* modifications (c) Rob Taylor, Flying Pig Systems. 2000.
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*
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* added support for port on 64-bit bus
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* by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
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*/
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#ifndef __SERIAL_NS16550__H
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#define __SERIAL_NS16550__H
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/** Register offset definitions
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* platform implementation needs to translate this
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*/
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#define rbr 0
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#define ier 1
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#define fcr 2
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#define lcr 3
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#define mcr 4
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#define lsr 5
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#define msr 6
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#define scr 7
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#ifdef CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS
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#define mdr1 8
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#define osc_12m_sel 9
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#endif
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#define thr rbr
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#define iir fcr
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#define dll rbr
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#define dlm ier
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#define FCR_FIFO_EN 0x01 /* Fifo enable */
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#define FCR_RXSR 0x02 /* Receiver soft reset */
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#define FCR_TXSR 0x04 /* Transmitter soft reset */
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#define MCR_DTR 0x01
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#define MCR_RTS 0x02
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#define MCR_DMA_EN 0x04
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#define MCR_TX_DFR 0x08
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#define LCR_WLS_MSK 0x03 /* character length select mask */
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#define LCR_WLS_5 0x00 /* 5 bit character length */
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#define LCR_WLS_6 0x01 /* 6 bit character length */
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#define LCR_WLS_7 0x02 /* 7 bit character length */
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#define LCR_WLS_8 0x03 /* 8 bit character length */
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/* Number of stop Bits, off = 1, on = 1.5 or 2) */
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#define LCR_STB 0x04
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#define LCR_PEN 0x08 /* Parity eneble */
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#define LCR_EPS 0x10 /* Even Parity Select */
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#define LCR_STKP 0x20 /* Stick Parity */
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#define LCR_SBRK 0x40 /* Set Break */
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#define LCR_BKSE 0x80 /* Bank select enable */
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#define LSR_DR 0x01 /* Data ready */
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#define LSR_OE 0x02 /* Overrun */
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#define LSR_PE 0x04 /* Parity error */
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#define LSR_FE 0x08 /* Framing error */
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#define LSR_BI 0x10 /* Break */
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#define LSR_THRE 0x20 /* Xmit holding register empty */
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#define LSR_TEMT 0x40 /* Xmitter empty */
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#define LSR_ERR 0x80 /* Error */
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/* useful defaults for LCR */
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#define LCR_8N1 0x03
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#define LCRVAL LCR_8N1 /* 8 data, 1 stop, no parity */
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#define MCRVAL (MCR_DTR | MCR_RTS) /* RTS/DTR */
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/* Clear & enable FIFOs */
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#define FCRVAL (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR)
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#define MODE_X_DIV 16
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#endif /* __SERIAL_NS16550__H */
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