2013-01-31 11:54:55 +00:00
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/*
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* Driver for AT91/AT32 LCD Controller
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*
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* Copyright (C) 2007 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <io.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <malloc.h>
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#include <asm/mmu.h>
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#include "atmel_lcdfb.h"
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static void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo)
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{
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clk_enable(sinfo->bus_clk);
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clk_enable(sinfo->lcdc_clk);
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}
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static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo)
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{
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clk_disable(sinfo->bus_clk);
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clk_disable(sinfo->lcdc_clk);
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}
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static void atmel_lcdc_power_controller(struct fb_info *fb_info, int i)
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{
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struct atmel_lcdfb_info *sinfo = fb_info->priv;
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struct atmel_lcdfb_platform_data *pdata = sinfo->pdata;
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if (pdata->atmel_lcdfb_power_control)
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pdata->atmel_lcdfb_power_control(1);
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}
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/**
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* @param fb_info Framebuffer information
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*/
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static void atmel_lcdc_enable_controller(struct fb_info *fb_info)
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{
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atmel_lcdc_power_controller(fb_info, 1);
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}
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/**
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* @param fb_info Framebuffer information
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*/
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static void atmel_lcdc_disable_controller(struct fb_info *fb_info)
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{
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atmel_lcdc_power_controller(fb_info, 0);
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}
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static int atmel_lcdfb_check_var(struct fb_info *info)
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{
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struct device_d *dev = &info->dev;
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struct atmel_lcdfb_info *sinfo = info->priv;
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struct atmel_lcdfb_platform_data *pdata = sinfo->pdata;
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struct fb_videomode *mode = info->mode;
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unsigned long clk_value_khz;
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clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
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dev_dbg(dev, "%s:\n", __func__);
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if (!(mode->pixclock && info->bits_per_pixel)) {
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dev_err(dev, "needed value not specified\n");
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return -EINVAL;
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}
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dev_dbg(dev, " resolution: %ux%u\n", mode->xres, mode->yres);
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dev_dbg(dev, " pixclk: %lu KHz\n", PICOS2KHZ(mode->pixclock));
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dev_dbg(dev, " bpp: %u\n", info->bits_per_pixel);
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dev_dbg(dev, " clk: %lu KHz\n", clk_value_khz);
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if (PICOS2KHZ(mode->pixclock) > clk_value_khz) {
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dev_err(dev, "%lu KHz pixel clock is too fast\n", PICOS2KHZ(mode->pixclock));
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return -EINVAL;
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}
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/* Saturate vertical and horizontal timings at maximum values */
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if (sinfo->dev_data->limit_screeninfo)
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sinfo->dev_data->limit_screeninfo(mode);
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mode->vsync_len = min_t(u32, mode->vsync_len,
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(ATMEL_LCDC_VPW >> ATMEL_LCDC_VPW_OFFSET) + 1);
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mode->upper_margin = min_t(u32, mode->upper_margin,
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ATMEL_LCDC_VBP >> ATMEL_LCDC_VBP_OFFSET);
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mode->lower_margin = min_t(u32, mode->lower_margin,
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ATMEL_LCDC_VFP);
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mode->right_margin = min_t(u32, mode->right_margin,
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(ATMEL_LCDC_HFP >> ATMEL_LCDC_HFP_OFFSET) + 1);
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mode->hsync_len = min_t(u32, mode->hsync_len,
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(ATMEL_LCDC_HPW >> ATMEL_LCDC_HPW_OFFSET) + 1);
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mode->left_margin = min_t(u32, mode->left_margin,
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ATMEL_LCDC_HBP + 1);
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/* Some parameters can't be zero */
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mode->vsync_len = max_t(u32, mode->vsync_len, 1);
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mode->right_margin = max_t(u32, mode->right_margin, 1);
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mode->hsync_len = max_t(u32, mode->hsync_len, 1);
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mode->left_margin = max_t(u32, mode->left_margin, 1);
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switch (info->bits_per_pixel) {
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case 1:
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case 2:
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case 4:
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case 8:
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info->red.offset = info->green.offset = info->blue.offset = 0;
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info->red.length = info->green.length = info->blue.length
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= info->bits_per_pixel;
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break;
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case 16:
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/* Older SOCs use IBGR:555 rather than BGR:565. */
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if (pdata->have_intensity_bit)
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info->green.length = 5;
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else
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info->green.length = 6;
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if (pdata->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
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/* RGB:5X5 mode */
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info->red.offset = info->green.length + 5;
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info->blue.offset = 0;
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} else {
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/* BGR:5X5 mode */
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info->red.offset = 0;
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info->blue.offset = info->green.length + 5;
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}
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info->green.offset = 5;
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info->red.length = info->blue.length = 5;
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break;
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case 32:
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info->transp.offset = 24;
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info->transp.length = 8;
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/* fall through */
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case 24:
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if (pdata->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
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/* RGB:888 mode */
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info->red.offset = 16;
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info->blue.offset = 0;
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} else {
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/* BGR:888 mode */
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info->red.offset = 0;
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info->blue.offset = 16;
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}
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info->green.offset = 8;
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info->red.length = info->green.length = info->blue.length = 8;
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break;
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default:
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dev_err(dev, "color depth %d not supported\n",
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info->bits_per_pixel);
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return -EINVAL;
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}
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return 0;
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}
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static void atmel_lcdfb_set_par(struct fb_info *info)
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{
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struct atmel_lcdfb_info *sinfo = info->priv;
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if (sinfo->dev_data->stop)
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sinfo->dev_data->stop(sinfo, ATMEL_LCDC_STOP_NOWAIT);
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/* Re-initialize the DMA engine... */
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dev_dbg(&info->dev, " * update DMA engine\n");
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sinfo->dev_data->update_dma(info);
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/* Now, the LCDC core... */
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sinfo->dev_data->setup_core(info);
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if (sinfo->dev_data->start)
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sinfo->dev_data->start(sinfo);
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dev_dbg(&info->dev, " * DONE\n");
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}
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static int atmel_lcdfb_alloc_video_memory(struct atmel_lcdfb_info *sinfo)
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{
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struct fb_info *info = &sinfo->info;
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struct fb_videomode *mode = info->mode;
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unsigned int smem_len;
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free(info->screen_base);
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smem_len = (mode->xres * mode->yres
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* ((info->bits_per_pixel + 7) / 8));
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smem_len = max(smem_len, sinfo->smem_len);
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info->screen_base = dma_alloc_coherent(smem_len);
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if (!info->screen_base)
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return -ENOMEM;
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memset(info->screen_base, 0, smem_len);
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return 0;
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}
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/**
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* Prepare the video hardware for a specified video mode
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* @param fb_info Framebuffer information
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* @param mode The video mode description to initialize
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* @return 0 on success
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*/
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static int atmel_lcdc_activate_var(struct fb_info *info)
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{
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struct atmel_lcdfb_info *sinfo = info->priv;
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int ret;
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ret = atmel_lcdfb_alloc_video_memory(sinfo);
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if (ret)
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return ret;
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atmel_lcdfb_set_par(info);
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if (sinfo->dev_data->init_contrast)
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sinfo->dev_data->init_contrast(sinfo);
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return atmel_lcdfb_check_var(info);
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}
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/*
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* There is only one video hardware instance available.
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* It makes no sense to dynamically allocate this data
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*/
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static struct fb_ops atmel_lcdc_ops = {
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.fb_activate_var = atmel_lcdc_activate_var,
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.fb_enable = atmel_lcdc_enable_controller,
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.fb_disable = atmel_lcdc_disable_controller,
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};
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int atmel_lcdc_register(struct device_d *dev, struct atmel_lcdfb_devdata *data)
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{
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struct atmel_lcdfb_info *sinfo;
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struct atmel_lcdfb_platform_data *pdata = dev->platform_data;
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int ret = 0;
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struct fb_info *info;
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if (!pdata) {
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dev_err(dev, "missing platform_data\n");
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return -EINVAL;
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}
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sinfo = xzalloc(sizeof(*sinfo));
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sinfo->pdata = pdata;
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sinfo->mmio = dev_request_mem_region(dev, 0);
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sinfo->dev_data = data;
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/* just init */
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info = &sinfo->info;
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info->priv = sinfo;
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info->fbops = &atmel_lcdc_ops;
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info->mode_list = pdata->mode_list;
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info->num_modes = pdata->num_modes;
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info->mode = &info->mode_list[0];
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info->xres = info->mode->xres;
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info->yres = info->mode->yres;
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info->bits_per_pixel = pdata->default_bpp;
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/* Enable LCDC Clocks */
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sinfo->bus_clk = clk_get(dev, "hck1");
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if (IS_ERR(sinfo->bus_clk)) {
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ret = PTR_ERR(sinfo->bus_clk);
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goto err;
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}
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sinfo->lcdc_clk = clk_get(dev, "lcdc_clk");
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if (IS_ERR(sinfo->lcdc_clk)) {
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ret = PTR_ERR(sinfo->lcdc_clk);
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goto put_bus_clk;
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}
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atmel_lcdfb_start_clock(sinfo);
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2013-01-31 11:54:56 +00:00
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if (data->dma_desc_size)
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sinfo->dma_desc = dma_alloc_coherent(data->dma_desc_size);
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2013-01-31 11:54:55 +00:00
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ret = register_framebuffer(info);
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if (ret != 0) {
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dev_err(dev, "Failed to register framebuffer\n");
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goto stop_clk;
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}
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return ret;
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stop_clk:
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2013-01-31 11:54:56 +00:00
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if (sinfo->dma_desc)
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free(sinfo->dma_desc);
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2013-01-31 11:54:55 +00:00
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atmel_lcdfb_stop_clock(sinfo);
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clk_put(sinfo->lcdc_clk);
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put_bus_clk:
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clk_put(sinfo->bus_clk);
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err:
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return ret;
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}
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