2008-03-14 11:59:55 +00:00
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/*
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* Copyright (C) 2008 Sascha Hauer, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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2008-03-11 21:13:06 +00:00
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#include <common.h>
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#include <init.h>
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#include <driver.h>
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#include <spi/spi.h>
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#include <xfuncs.h>
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2008-03-14 11:59:55 +00:00
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#include <asm/io.h>
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2009-10-02 13:34:25 +00:00
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#include <gpio.h>
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#include <asm/arch/spi.h>
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2008-03-14 11:59:55 +00:00
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#define MXC_CSPIRXDATA 0x00
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#define MXC_CSPITXDATA 0x04
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#define MXC_CSPICTRL 0x08
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#define MXC_CSPIINT 0x0C
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#define MXC_CSPIDMA 0x18
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#define MXC_CSPISTAT 0x0C
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#define MXC_CSPIPERIOD 0x14
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#define MXC_CSPITEST 0x10
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#define MXC_CSPIRESET 0x1C
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#define MXC_CSPICTRL_ENABLE (1 << 10)
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#define MXC_CSPICTRL_MASTER (1 << 11)
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#define MXC_CSPICTRL_XCH (1 << 9)
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#define MXC_CSPICTRL_LOWPOL (1 << 5)
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#define MXC_CSPICTRL_PHA (1 << 6)
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#define MXC_CSPICTRL_SSCTL (1 << 7)
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#define MXC_CSPICTRL_HIGHSSPOL (1 << 8)
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#define MXC_CSPICTRL_CS(x) (((x) & 0x3) << 19)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 0)
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#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 14)
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#define MXC_CSPICTRL_MAXDATRATE 0x10
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#define MXC_CSPICTRL_DATAMASK 0x1F
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#define MXC_CSPICTRL_DATASHIFT 14
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#define MXC_CSPISTAT_TE (1 << 0)
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#define MXC_CSPISTAT_TH (1 << 1)
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#define MXC_CSPISTAT_TF (1 << 2)
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2009-10-02 13:34:25 +00:00
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#define MXC_CSPISTAT_RR (1 << 4)
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#define MXC_CSPISTAT_RH (1 << 5)
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#define MXC_CSPISTAT_RF (1 << 6)
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#define MXC_CSPISTAT_RO (1 << 7)
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2008-03-14 11:59:55 +00:00
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#define MXC_CSPIPERIOD_32KHZ (1 << 15)
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#define MXC_CSPITEST_LBC (1 << 14)
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2009-10-02 13:34:25 +00:00
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struct imx_spi {
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struct spi_master master;
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int *chipselect;
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};
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2008-03-14 11:59:55 +00:00
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static int imx_spi_setup(struct spi_device *spi)
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{
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debug("%s mode 0x%08x bits_per_word: %d speed: %d\n",
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__FUNCTION__, spi->mode, spi->bits_per_word,
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spi->max_speed_hz);
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return 0;
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}
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2009-05-13 13:59:29 +00:00
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static unsigned int spi_xchg_single(ulong base, unsigned int data)
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2008-03-14 11:59:55 +00:00
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{
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unsigned int cfg_reg = readl(base + MXC_CSPICTRL);
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writel(data, base + MXC_CSPITXDATA);
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cfg_reg |= MXC_CSPICTRL_XCH;
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writel(cfg_reg, base + MXC_CSPICTRL);
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2009-10-02 13:34:25 +00:00
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while (!(readl(base + MXC_CSPIINT) & MXC_CSPISTAT_RR));
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2008-03-14 11:59:55 +00:00
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return readl(base + MXC_CSPIRXDATA);
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}
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static void mxc_spi_chipselect(struct spi_device *spi, int is_active)
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{
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struct spi_master *master = spi->master;
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2009-10-02 13:34:25 +00:00
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struct imx_spi *imx = container_of(master, struct imx_spi, master);
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2008-03-14 11:59:55 +00:00
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ulong base = master->dev->map_base;
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2009-10-02 13:34:25 +00:00
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unsigned int cs = 0;
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int gpio = imx->chipselect[spi->chip_select];
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2008-03-14 11:59:55 +00:00
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u32 ctrl_reg;
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2009-10-02 13:34:25 +00:00
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if (spi->mode & SPI_CS_HIGH)
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cs = 1;
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if (!is_active) {
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if (gpio >= 0)
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gpio_set_value(gpio, !cs);
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return;
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}
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ctrl_reg = MXC_CSPICTRL_BITCOUNT(spi->bits_per_word - 1)
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2008-03-14 11:59:55 +00:00
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| MXC_CSPICTRL_DATARATE(7) /* FIXME: calculate data rate */
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| MXC_CSPICTRL_ENABLE
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| MXC_CSPICTRL_MASTER;
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2009-10-02 13:34:25 +00:00
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if (gpio < 0) {
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ctrl_reg |= MXC_CSPICTRL_CS(gpio + 32);
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}
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2008-03-14 11:59:55 +00:00
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if (spi->mode & SPI_CPHA)
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ctrl_reg |= MXC_CSPICTRL_PHA;
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2009-10-02 13:34:25 +00:00
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if (spi->mode & SPI_CPOL)
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2008-03-14 11:59:55 +00:00
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ctrl_reg |= MXC_CSPICTRL_LOWPOL;
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if (spi->mode & SPI_CS_HIGH)
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ctrl_reg |= MXC_CSPICTRL_HIGHSSPOL;
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writel(ctrl_reg, base + MXC_CSPICTRL);
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2009-10-02 13:34:25 +00:00
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if (gpio >= 0)
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gpio_set_value(gpio, cs);
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2008-03-14 11:59:55 +00:00
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}
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static int imx_spi_transfer(struct spi_device *spi, struct spi_message *mesg)
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{
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struct spi_master *master = spi->master;
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ulong base = master->dev->map_base;
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struct spi_transfer *t = NULL;
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mxc_spi_chipselect(spi, 1);
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list_for_each_entry (t, &mesg->transfers, transfer_list) {
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const u32 *txbuf = t->tx_buf;
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u32 *rxbuf = t->rx_buf;
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int i = 0;
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while(i < t->len >> 2) {
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rxbuf[i] = spi_xchg_single(base, txbuf[i]);
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i++;
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}
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}
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2009-10-02 13:34:25 +00:00
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mxc_spi_chipselect(spi, 0);
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2008-03-14 11:59:55 +00:00
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return 0;
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}
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2008-03-11 21:13:06 +00:00
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static int imx_spi_probe(struct device_d *dev)
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{
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struct spi_master *master;
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2009-10-02 13:34:25 +00:00
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struct imx_spi *imx;
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struct spi_imx_master *pdata = dev->platform_data;
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2008-03-11 21:13:06 +00:00
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2009-10-02 13:34:25 +00:00
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imx = xzalloc(sizeof(*imx));
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2008-03-14 11:59:55 +00:00
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2009-10-02 13:34:25 +00:00
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master = &imx->master;
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2008-03-14 11:59:55 +00:00
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master->dev = dev;
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master->setup = imx_spi_setup;
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master->transfer = imx_spi_transfer;
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2009-10-02 13:34:25 +00:00
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master->num_chipselect = pdata->num_chipselect;
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imx->chipselect = pdata->chipselect;
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2008-03-14 11:59:55 +00:00
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writel(MXC_CSPICTRL_ENABLE | MXC_CSPICTRL_MASTER,
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dev->map_base + MXC_CSPICTRL);
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writel(MXC_CSPIPERIOD_32KHZ,
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dev->map_base + MXC_CSPIPERIOD);
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2009-10-02 13:34:25 +00:00
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while (readl(dev->map_base + MXC_CSPIINT) & MXC_CSPISTAT_RR)
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readl(dev->map_base + MXC_CSPIRXDATA);
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2008-03-14 11:59:55 +00:00
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writel(0, dev->map_base + MXC_CSPIINT);
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2008-03-11 21:13:06 +00:00
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spi_register_master(master);
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return 0;
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}
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static struct driver_d imx_spi_driver = {
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.name = "imx_spi",
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.probe = imx_spi_probe,
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};
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static int imx_spi_init(void)
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{
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2008-03-14 11:59:55 +00:00
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register_driver(&imx_spi_driver);
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return 0;
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2008-03-11 21:13:06 +00:00
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}
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device_initcall(imx_spi_init);
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