2008-07-08 07:25:35 +00:00
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/*
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2007-10-07 22:13:19 +00:00
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* Copyright (C) 2007 Sascha Hauer, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <net.h>
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#include <cfi_flash.h>
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#include <init.h>
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#include <environment.h>
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#include <asm/arch/imx-regs.h>
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2007-11-08 15:24:51 +00:00
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#include <fec.h>
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2007-10-07 22:13:19 +00:00
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#include <asm/arch/gpio.h>
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2008-02-26 14:38:37 +00:00
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#include <asm/armlinux.h>
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2008-03-11 21:13:06 +00:00
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#include <asm/mach-types.h>
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2008-03-14 12:01:13 +00:00
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#include <asm/arch/pmic.h>
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2007-10-07 22:13:19 +00:00
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#include <partition.h>
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#include <fs.h>
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#include <fcntl.h>
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2008-08-13 13:12:51 +00:00
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#include <nand.h>
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2008-03-11 21:13:06 +00:00
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#include <spi/spi.h>
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2008-03-14 12:01:13 +00:00
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#include <asm/io.h>
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2008-08-12 15:14:04 +00:00
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#include <asm/arch/imx-nand.h>
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2007-10-07 22:13:19 +00:00
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static struct device_d cfi_dev = {
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.name = "cfi_flash",
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.id = "nor0",
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.map_base = 0xC0000000,
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2007-10-09 15:18:36 +00:00
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.size = 32 * 1024 * 1024,
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2007-10-07 22:13:19 +00:00
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};
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static struct device_d sdram_dev = {
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.name = "ram",
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.id = "ram0",
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.map_base = 0xa0000000,
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2007-11-05 11:26:29 +00:00
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.size = 128 * 1024 * 1024,
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2007-10-07 22:13:19 +00:00
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.type = DEVICE_TYPE_DRAM,
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};
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2008-08-26 09:32:40 +00:00
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#if 0
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2008-08-14 08:24:48 +00:00
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static struct device_d sram_dev = {
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.name = "ram",
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.id = "sram0",
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.map_base = 0xc8000000,
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.size = 512 * 1024, /* Can be up to 2MiB */
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.type = DEVICE_TYPE_DRAM,
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};
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2008-08-26 09:32:40 +00:00
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#endif
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2008-08-14 08:24:48 +00:00
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2007-11-08 15:24:51 +00:00
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static struct fec_platform_data fec_info = {
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2007-11-05 11:26:29 +00:00
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.xcv_type = MII100,
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};
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2007-10-07 22:13:19 +00:00
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static struct device_d fec_dev = {
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2007-11-08 15:24:51 +00:00
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.name = "fec_imx27",
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2007-10-07 22:13:19 +00:00
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.id = "eth0",
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2007-11-05 11:26:29 +00:00
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.map_base = 0x1002b000,
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.platform_data = &fec_info,
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2007-10-07 22:13:19 +00:00
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.type = DEVICE_TYPE_ETHER,
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};
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2008-03-11 21:13:06 +00:00
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static struct device_d spi_dev = {
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.name = "imx_spi",
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.id = "spi0",
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.map_base = 0x1000e000,
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};
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static struct spi_board_info pcm038_spi_board_info[] = {
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{
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.name = "mc13783",
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.max_speed_hz = 3000000,
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.bus_num = 0,
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.chip_select = 0,
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}
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};
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2008-08-12 15:14:04 +00:00
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struct imx_nand_platform_data nand_info = {
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.width = 1,
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.hw_ecc = 1,
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};
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static struct device_d nand_dev = {
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.name = "imx_nand",
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.map_base = 0xd8000000,
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.platform_data = &nand_info,
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};
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2007-10-07 22:13:19 +00:00
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static int pcm038_devices_init(void)
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{
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int i;
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2008-08-13 12:39:44 +00:00
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struct device_d *nand, *dev;
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2008-08-14 07:30:08 +00:00
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char *envdev = "no";
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2008-08-13 12:39:44 +00:00
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2007-11-05 11:26:29 +00:00
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unsigned int mode[] = {
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2007-10-07 22:13:19 +00:00
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PD0_AIN_FEC_TXD0,
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PD1_AIN_FEC_TXD1,
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PD2_AIN_FEC_TXD2,
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PD3_AIN_FEC_TXD3,
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2007-11-05 11:26:29 +00:00
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PD4_AOUT_FEC_RX_ER,
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PD5_AOUT_FEC_RXD1,
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PD6_AOUT_FEC_RXD2,
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PD7_AOUT_FEC_RXD3,
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2007-10-07 22:13:19 +00:00
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PD8_AF_FEC_MDIO,
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2007-11-05 11:26:29 +00:00
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PD9_AIN_FEC_MDC | GPIO_PUEN,
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PD10_AOUT_FEC_CRS,
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PD11_AOUT_FEC_TX_CLK,
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PD12_AOUT_FEC_RXD0,
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PD13_AOUT_FEC_RX_DV,
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2007-10-07 22:13:19 +00:00
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PD14_AOUT_FEC_CLR,
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PD15_AOUT_FEC_COL,
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PD16_AIN_FEC_TX_ER,
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2007-11-05 11:26:29 +00:00
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PF23_AIN_FEC_TX_EN,
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2007-10-07 22:13:19 +00:00
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PE12_PF_UART1_TXD,
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PE13_PF_UART1_RXD,
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PE14_PF_UART1_CTS,
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2007-11-28 08:01:19 +00:00
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PE15_PF_UART1_RTS,
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2008-03-14 12:01:13 +00:00
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PD25_PF_CSPI1_RDY,
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PD26_PF_CSPI1_SS2,
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PD27_PF_CSPI1_SS1,
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PD28_PF_CSPI1_SS0,
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PD29_PF_CSPI1_SCLK,
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PD30_PF_CSPI1_MISO,
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PD31_PF_CSPI1_MOSI,
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2007-11-28 08:01:19 +00:00
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};
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2007-10-07 22:13:19 +00:00
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2008-08-12 15:14:04 +00:00
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/* configure 16 bit nor flash on cs0 */
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2008-08-14 07:43:03 +00:00
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CS0U = 0x0000CC03;
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CS0L = 0xa0330D01;
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CS0A = 0x00220800;
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/* configure SRAM on cs1 */
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CS1U = 0x0000d843;
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CS1L = 0x22252521;
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CS1A = 0x22220a00;
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/* configure SJA1000 on cs4 */
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CS4U = 0x0000DCF6;
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CS4L = 0x444A0301;
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CS4A = 0x44443302;
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2008-08-12 15:14:04 +00:00
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2007-11-28 08:01:19 +00:00
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/* initizalize gpios */
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for (i = 0; i < ARRAY_SIZE(mode); i++)
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2007-10-07 22:13:19 +00:00
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imx_gpio_mode(mode[i]);
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register_device(&cfi_dev);
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2008-08-12 15:14:04 +00:00
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register_device(&nand_dev);
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2007-10-07 22:13:19 +00:00
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register_device(&sdram_dev);
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2008-08-26 09:32:40 +00:00
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#if 0
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2008-08-14 08:24:48 +00:00
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register_device(&sram_dev);
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2008-08-26 09:32:40 +00:00
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#endif
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2008-03-14 12:01:13 +00:00
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PCCR0 |= PCCR0_CSPI1_EN;
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PCCR1 |= PCCR1_PERCLK2_EN;
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spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info));
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register_device(&spi_dev);
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2007-10-07 22:13:19 +00:00
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2008-08-13 12:39:44 +00:00
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switch ((GPCR & GPCR_BOOT_MASK) >> GPCR_BOOT_SHIFT) {
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case GPCR_BOOT_8BIT_NAND_2k:
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case GPCR_BOOT_16BIT_NAND_2k:
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case GPCR_BOOT_16BIT_NAND_512:
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case GPCR_BOOT_8BIT_NAND_512:
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nand = get_device_by_path("/dev/nand0");
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2008-08-14 07:30:08 +00:00
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if (!nand)
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break;
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2008-08-13 12:39:44 +00:00
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dev = dev_add_partition(nand, 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
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2008-08-14 07:30:08 +00:00
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if (!dev)
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break;
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2008-08-13 12:39:44 +00:00
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dev_add_bb_dev(dev, "self0");
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dev = dev_add_partition(nand, 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
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2008-08-14 07:30:08 +00:00
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if (!dev)
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break;
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2008-08-13 12:39:44 +00:00
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dev_add_bb_dev(dev, "env0");
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envdev = "NAND";
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break;
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default:
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dev_add_partition(&cfi_dev, 0x00000, 0x40000, PARTITION_FIXED, "self");
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dev_add_partition(&cfi_dev, 0x40000, 0x20000, PARTITION_FIXED, "env");
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dev_protect(&cfi_dev, 0x40000, 0, 1);
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envdev = "NOR";
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}
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printf("Using environment in %s Flash\n", envdev);
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2007-10-07 22:13:19 +00:00
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2008-02-26 14:38:37 +00:00
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armlinux_set_bootparams((void *)0xa0000100);
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armlinux_set_architecture(MACH_TYPE_PCM038);
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2007-10-07 22:13:19 +00:00
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return 0;
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}
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device_initcall(pcm038_devices_init);
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static struct device_d pcm038_serial_device = {
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.name = "imx_serial",
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.id = "cs0",
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.map_base = IMX_UART1_BASE,
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.size = 4096,
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.type = DEVICE_TYPE_CONSOLE,
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};
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static int pcm038_console_init(void)
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{
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register_device(&pcm038_serial_device);
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return 0;
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}
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console_initcall(pcm038_console_init);
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2008-03-14 12:01:13 +00:00
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static int pcm038_power_init(void)
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{
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2008-08-13 12:39:44 +00:00
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#ifdef CONFIG_DRIVER_SPI_MC13783
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2008-09-09 12:13:59 +00:00
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int i = 0;
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2008-03-14 12:01:13 +00:00
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int ret;
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ret = pmic_power();
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if (ret)
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goto out;
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MPCTL0 = PLL_PCTL_PD(0) |
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PLL_PCTL_MFD(51) |
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PLL_PCTL_MFI(7) |
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PLL_PCTL_MFN(35);
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CSCR |= CSCR_MPLL_RESTART;
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2008-09-09 12:13:59 +00:00
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while (i++ < 1000) {
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while (CCSR & CCSR_32K_SR);
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while (!(CCSR & CCSR_32K_SR));
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}
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2008-03-14 12:01:13 +00:00
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PCDR1 = 0x09030911;
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2008-05-12 14:07:40 +00:00
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2008-03-14 12:01:13 +00:00
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out:
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2008-05-12 14:07:40 +00:00
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#else
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#warning no pmic support enabled. your pcm038 will run on low speed
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#endif
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2008-03-14 12:01:13 +00:00
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/* Register the fec device after the PLL re-initialisation
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* as the fec depends on the (now higher) ipg clock
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*/
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register_device(&fec_dev);
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return 0;
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}
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late_initcall(pcm038_power_init);
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2008-08-12 15:14:04 +00:00
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#ifdef CONFIG_NAND_IMX_BOOT
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void __bare_init nand_boot(void)
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{
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imx_nand_load_image((void *)TEXT_BASE, 256 * 1024, 512, 16384);
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}
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#endif
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static int pll_init(void)
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{
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2008-09-09 12:13:59 +00:00
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int i = 0;
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2008-08-12 15:14:04 +00:00
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/*
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* pll clock initialization - see section 3.4.3 of the i.MX27 manual
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*/
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MPCTL0 = PLL_PCTL_PD(1) |
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PLL_PCTL_MFD(51) |
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PLL_PCTL_MFI(7) |
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PLL_PCTL_MFN(35); /* MPLL = 2 * 26 * 3.83654 MHz = 199.5 MHz */
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SPCTL0 = PLL_PCTL_PD(1) |
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PLL_PCTL_MFD(12) |
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PLL_PCTL_MFI(9) |
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PLL_PCTL_MFN(3); /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
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/*
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* ARM clock = (399 MHz / 2) / (ARM divider = 1) = 200 MHz
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* AHB clock = (399 MHz / 3) / (AHB divider = 2) = 66.5 MHz
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* System clock (HCLK) = 133 MHz
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*/
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#define CSCR_VAL CSCR_USB_DIV(3) | \
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CSCR_SD_CNT(3) | \
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CSCR_MSHC_SEL | \
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CSCR_H264_SEL | \
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CSCR_SSI1_SEL | \
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CSCR_SSI2_SEL | \
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CSCR_MCU_SEL | \
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CSCR_SP_SEL | \
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CSCR_ARM_SRC_MPLL | \
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CSCR_AHB_DIV(1) | \
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CSCR_ARM_DIV(0) | \
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CSCR_FPM_EN | \
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CSCR_SPEN | \
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CSCR_MPEN
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CSCR = CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART;
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2008-09-09 12:13:59 +00:00
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while (i++ < 1000) {
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|
while (CCSR & CCSR_32K_SR);
|
|
|
|
while (!(CCSR & CCSR_32K_SR));
|
|
|
|
}
|
2008-08-12 15:14:04 +00:00
|
|
|
|
|
|
|
/* clock gating enable */
|
|
|
|
GPCR = 0x00050f08;
|
|
|
|
|
|
|
|
/* peripheral clock divider */
|
|
|
|
PCDR0 = 0x130410c3; /* FIXME */
|
|
|
|
PCDR1 = 0x09030908; /* PERDIV1=08 @133 MHz */
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
core_initcall(pll_init);
|
|
|
|
|