949 lines
31 KiB
C
949 lines
31 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
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* Copyright (C) 2000 Silicon Graphics, Inc.
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* Modified for further R[236]000 support by Paul M. Antoine, 1996.
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* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000, 07 MIPS Technologies, Inc.
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* Copyright (C) 2003, 2004 Maciej W. Rozycki
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*/
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#ifndef _ASM_MIPSREGS_H
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#define _ASM_MIPSREGS_H
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/*
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* The following macros are especially useful for __asm__
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* inline assembler.
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*/
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#ifndef __STR
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#define __STR(x) #x
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#endif
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#ifndef STR
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#define STR(x) __STR(x)
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#endif
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/*
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* Configure language
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*/
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#ifdef __ASSEMBLY__
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#define _ULCAST_
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#else
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#define _ULCAST_ (unsigned long)
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#endif
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/*
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* Coprocessor 0 register names
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*/
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#define CP0_INDEX $0
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#define CP0_RANDOM $1
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#define CP0_ENTRYLO0 $2
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#define CP0_ENTRYLO1 $3
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#define CP0_CONF $3
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#define CP0_CONTEXT $4
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#define CP0_PAGEMASK $5
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#define CP0_WIRED $6
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#define CP0_INFO $7
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#define CP0_BADVADDR $8
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#define CP0_COUNT $9
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#define CP0_ENTRYHI $10
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#define CP0_COMPARE $11
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#define CP0_STATUS $12
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#define CP0_CAUSE $13
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#define CP0_EPC $14
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#define CP0_PRID $15
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#define CP0_CONFIG $16
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#define CP0_LLADDR $17
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#define CP0_WATCHLO $18
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#define CP0_WATCHHI $19
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#define CP0_XCONTEXT $20
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#define CP0_FRAMEMASK $21
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#define CP0_DIAGNOSTIC $22
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#define CP0_DEBUG $23
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#define CP0_DEPC $24
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#define CP0_PERFORMANCE $25
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#define CP0_ECC $26
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#define CP0_CACHEERR $27
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#define CP0_TAGLO $28
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#define CP0_TAGHI $29
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#define CP0_ERROREPC $30
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#define CP0_DESAVE $31
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/*
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* R4640/R4650 cp0 register names. These registers are listed
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* here only for completeness; without MMU these CPUs are not useable
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* by Linux. A future ELKS port might take make Linux run on them
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* though ...
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*/
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#define CP0_IBASE $0
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#define CP0_IBOUND $1
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#define CP0_DBASE $2
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#define CP0_DBOUND $3
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#define CP0_CALG $17
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#define CP0_IWATCH $18
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#define CP0_DWATCH $19
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/*
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* Coprocessor 0 Set 1 register names
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*/
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#define CP0_S1_DERRADDR0 $26
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#define CP0_S1_DERRADDR1 $27
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#define CP0_S1_INTCONTROL $20
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/*
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* Coprocessor 0 Set 2 register names
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*/
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#define CP0_S2_SRSCTL $12 /* MIPSR2 */
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/*
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* Coprocessor 0 Set 3 register names
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*/
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#define CP0_S3_SRSMAP $12 /* MIPSR2 */
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/*
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* TX39 Series
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*/
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#define CP0_TX39_CACHE $7
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/*
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* Coprocessor 1 (FPU) register names
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*/
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#define CP1_REVISION $0
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#define CP1_STATUS $31
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/*
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* FPU Status Register Values
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*/
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/*
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* Status Register Values
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*/
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#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
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#define FPU_CSR_COND 0x00800000 /* $fcc0 */
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#define FPU_CSR_COND0 0x00800000 /* $fcc0 */
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#define FPU_CSR_COND1 0x02000000 /* $fcc1 */
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#define FPU_CSR_COND2 0x04000000 /* $fcc2 */
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#define FPU_CSR_COND3 0x08000000 /* $fcc3 */
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#define FPU_CSR_COND4 0x10000000 /* $fcc4 */
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#define FPU_CSR_COND5 0x20000000 /* $fcc5 */
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#define FPU_CSR_COND6 0x40000000 /* $fcc6 */
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#define FPU_CSR_COND7 0x80000000 /* $fcc7 */
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/*
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* Bits 18 - 20 of the FPU Status Register will be read as 0,
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* and should be written as zero.
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*/
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#define FPU_CSR_RSVD 0x001c0000
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/*
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* X the exception cause indicator
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* E the exception enable
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* S the sticky/flag bit
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*/
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#define FPU_CSR_ALL_X 0x0003f000
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#define FPU_CSR_UNI_X 0x00020000
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#define FPU_CSR_INV_X 0x00010000
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#define FPU_CSR_DIV_X 0x00008000
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#define FPU_CSR_OVF_X 0x00004000
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#define FPU_CSR_UDF_X 0x00002000
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#define FPU_CSR_INE_X 0x00001000
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#define FPU_CSR_ALL_E 0x00000f80
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#define FPU_CSR_INV_E 0x00000800
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#define FPU_CSR_DIV_E 0x00000400
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#define FPU_CSR_OVF_E 0x00000200
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#define FPU_CSR_UDF_E 0x00000100
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#define FPU_CSR_INE_E 0x00000080
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#define FPU_CSR_ALL_S 0x0000007c
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#define FPU_CSR_INV_S 0x00000040
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#define FPU_CSR_DIV_S 0x00000020
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#define FPU_CSR_OVF_S 0x00000010
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#define FPU_CSR_UDF_S 0x00000008
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#define FPU_CSR_INE_S 0x00000004
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/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
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#define FPU_CSR_RM 0x00000003
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#define FPU_CSR_RN 0x0 /* nearest */
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#define FPU_CSR_RZ 0x1 /* towards zero */
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#define FPU_CSR_RU 0x2 /* towards +Infinity */
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#define FPU_CSR_RD 0x3 /* towards -Infinity */
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/*
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* Values for PageMask register
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*/
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#ifdef CONFIG_CPU_VR41XX
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/* Why doesn't stupidity hurt ... */
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#define PM_1K 0x00000000
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#define PM_4K 0x00001800
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#define PM_16K 0x00007800
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#define PM_64K 0x0001f800
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#define PM_256K 0x0007f800
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#else
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#define PM_4K 0x00000000
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#define PM_8K 0x00002000
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#define PM_16K 0x00006000
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#define PM_32K 0x0000e000
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#define PM_64K 0x0001e000
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#define PM_128K 0x0003e000
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#define PM_256K 0x0007e000
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#define PM_512K 0x000fe000
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#define PM_1M 0x001fe000
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#define PM_2M 0x003fe000
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#define PM_4M 0x007fe000
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#define PM_8M 0x00ffe000
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#define PM_16M 0x01ffe000
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#define PM_32M 0x03ffe000
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#define PM_64M 0x07ffe000
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#define PM_256M 0x1fffe000
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#define PM_1G 0x7fffe000
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#endif
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/*
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* Bitfields in the R4xx0 cp0 status register
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*/
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#define ST0_IE 0x00000001
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#define ST0_EXL 0x00000002
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#define ST0_ERL 0x00000004
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#define ST0_KSU 0x00000018
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# define KSU_USER 0x00000010
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# define KSU_SUPERVISOR 0x00000008
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# define KSU_KERNEL 0x00000000
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#define ST0_UX 0x00000020
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#define ST0_SX 0x00000040
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#define ST0_KX 0x00000080
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#define ST0_DE 0x00010000
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#define ST0_CE 0x00020000
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/*
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* Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
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* cacheops in userspace. This bit exists only on RM7000 and RM9000
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* processors.
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*/
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#define ST0_CO 0x08000000
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/*
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* Bitfields in the R[23]000 cp0 status register.
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*/
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#define ST0_IEC 0x00000001
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#define ST0_KUC 0x00000002
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#define ST0_IEP 0x00000004
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#define ST0_KUP 0x00000008
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#define ST0_IEO 0x00000010
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#define ST0_KUO 0x00000020
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/* bits 6 & 7 are reserved on R[23]000 */
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#define ST0_ISC 0x00010000
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#define ST0_SWC 0x00020000
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#define ST0_CM 0x00080000
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/*
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* Bits specific to the R4640/R4650
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*/
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#define ST0_UM (_ULCAST_(1) << 4)
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#define ST0_IL (_ULCAST_(1) << 23)
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#define ST0_DL (_ULCAST_(1) << 24)
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/*
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* Enable the MIPS MDMX and DSP ASEs
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*/
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#define ST0_MX 0x01000000
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/*
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* Status register bits available in all MIPS CPUs.
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*/
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#define ST0_IM 0x0000ff00
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#define STATUSB_IP0 8
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#define STATUSF_IP0 (_ULCAST_(1) << 8)
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#define STATUSB_IP1 9
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#define STATUSF_IP1 (_ULCAST_(1) << 9)
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#define STATUSB_IP2 10
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#define STATUSF_IP2 (_ULCAST_(1) << 10)
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#define STATUSB_IP3 11
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#define STATUSF_IP3 (_ULCAST_(1) << 11)
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#define STATUSB_IP4 12
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#define STATUSF_IP4 (_ULCAST_(1) << 12)
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#define STATUSB_IP5 13
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#define STATUSF_IP5 (_ULCAST_(1) << 13)
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#define STATUSB_IP6 14
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#define STATUSF_IP6 (_ULCAST_(1) << 14)
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#define STATUSB_IP7 15
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#define STATUSF_IP7 (_ULCAST_(1) << 15)
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#define STATUSB_IP8 0
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#define STATUSF_IP8 (_ULCAST_(1) << 0)
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#define STATUSB_IP9 1
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#define STATUSF_IP9 (_ULCAST_(1) << 1)
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#define STATUSB_IP10 2
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#define STATUSF_IP10 (_ULCAST_(1) << 2)
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#define STATUSB_IP11 3
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#define STATUSF_IP11 (_ULCAST_(1) << 3)
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#define STATUSB_IP12 4
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#define STATUSF_IP12 (_ULCAST_(1) << 4)
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#define STATUSB_IP13 5
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#define STATUSF_IP13 (_ULCAST_(1) << 5)
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#define STATUSB_IP14 6
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#define STATUSF_IP14 (_ULCAST_(1) << 6)
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#define STATUSB_IP15 7
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#define STATUSF_IP15 (_ULCAST_(1) << 7)
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#define ST0_CH 0x00040000
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#define ST0_NMI 0x00080000
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#define ST0_SR 0x00100000
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#define ST0_TS 0x00200000
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#define ST0_BEV 0x00400000
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#define ST0_RE 0x02000000
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#define ST0_FR 0x04000000
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#define ST0_CU 0xf0000000
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#define ST0_CU0 0x10000000
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#define ST0_CU1 0x20000000
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#define ST0_CU2 0x40000000
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#define ST0_CU3 0x80000000
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#define ST0_XX 0x80000000 /* MIPS IV naming */
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/*
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* Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
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*
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* Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
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*/
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#define INTCTLB_IPPCI 26
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#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
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#define INTCTLB_IPTI 29
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#define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
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/*
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* Bitfields and bit numbers in the coprocessor 0 cause register.
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*
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* Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
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*/
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#define CAUSEB_EXCCODE 2
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#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
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#define CAUSEB_IP 8
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#define CAUSEF_IP (_ULCAST_(255) << 8)
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#define CAUSEB_IP0 8
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#define CAUSEF_IP0 (_ULCAST_(1) << 8)
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#define CAUSEB_IP1 9
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#define CAUSEF_IP1 (_ULCAST_(1) << 9)
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#define CAUSEB_IP2 10
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#define CAUSEF_IP2 (_ULCAST_(1) << 10)
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#define CAUSEB_IP3 11
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#define CAUSEF_IP3 (_ULCAST_(1) << 11)
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#define CAUSEB_IP4 12
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#define CAUSEF_IP4 (_ULCAST_(1) << 12)
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#define CAUSEB_IP5 13
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#define CAUSEF_IP5 (_ULCAST_(1) << 13)
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#define CAUSEB_IP6 14
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#define CAUSEF_IP6 (_ULCAST_(1) << 14)
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#define CAUSEB_IP7 15
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#define CAUSEF_IP7 (_ULCAST_(1) << 15)
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#define CAUSEB_IV 23
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#define CAUSEF_IV (_ULCAST_(1) << 23)
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#define CAUSEB_CE 28
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#define CAUSEF_CE (_ULCAST_(3) << 28)
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#define CAUSEB_TI 30
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#define CAUSEF_TI (_ULCAST_(1) << 30)
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#define CAUSEB_BD 31
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#define CAUSEF_BD (_ULCAST_(1) << 31)
|
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/*
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* Bits in the coprocessor 0 config register.
|
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*/
|
||
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/* Generic bits. */
|
||
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#define CONF_CM_CACHABLE_NO_WA 0
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#define CONF_CM_CACHABLE_WA 1
|
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#define CONF_CM_UNCACHED 2
|
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#define CONF_CM_CACHABLE_NONCOHERENT 3
|
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#define CONF_CM_CACHABLE_CE 4
|
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#define CONF_CM_CACHABLE_COW 5
|
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#define CONF_CM_CACHABLE_CUW 6
|
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#define CONF_CM_CACHABLE_ACCELERATED 7
|
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#define CONF_CM_CMASK 7
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#define CONF_BE (_ULCAST_(1) << 15)
|
||
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|
||
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/* Bits common to various processors. */
|
||
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#define CONF_CU (_ULCAST_(1) << 3)
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#define CONF_DB (_ULCAST_(1) << 4)
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#define CONF_IB (_ULCAST_(1) << 5)
|
||
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#define CONF_DC (_ULCAST_(7) << 6)
|
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#define CONF_IC (_ULCAST_(7) << 9)
|
||
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#define CONF_EB (_ULCAST_(1) << 13)
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||
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#define CONF_EM (_ULCAST_(1) << 14)
|
||
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#define CONF_SM (_ULCAST_(1) << 16)
|
||
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#define CONF_SC (_ULCAST_(1) << 17)
|
||
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#define CONF_EW (_ULCAST_(3) << 18)
|
||
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#define CONF_EP (_ULCAST_(15)<< 24)
|
||
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#define CONF_EC (_ULCAST_(7) << 28)
|
||
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#define CONF_CM (_ULCAST_(1) << 31)
|
||
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|
||
|
/* Bits specific to the R4xx0. */
|
||
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#define R4K_CONF_SW (_ULCAST_(1) << 20)
|
||
|
#define R4K_CONF_SS (_ULCAST_(1) << 21)
|
||
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#define R4K_CONF_SB (_ULCAST_(3) << 22)
|
||
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|
||
|
/* Bits specific to the R5000. */
|
||
|
#define R5K_CONF_SE (_ULCAST_(1) << 12)
|
||
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#define R5K_CONF_SS (_ULCAST_(3) << 20)
|
||
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|
||
|
/* Bits specific to the RM7000. */
|
||
|
#define RM7K_CONF_SE (_ULCAST_(1) << 3)
|
||
|
#define RM7K_CONF_TE (_ULCAST_(1) << 12)
|
||
|
#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
|
||
|
#define RM7K_CONF_TC (_ULCAST_(1) << 17)
|
||
|
#define RM7K_CONF_SI (_ULCAST_(3) << 20)
|
||
|
#define RM7K_CONF_SC (_ULCAST_(1) << 31)
|
||
|
|
||
|
/* Bits specific to the R10000. */
|
||
|
#define R10K_CONF_DN (_ULCAST_(3) << 3)
|
||
|
#define R10K_CONF_CT (_ULCAST_(1) << 5)
|
||
|
#define R10K_CONF_PE (_ULCAST_(1) << 6)
|
||
|
#define R10K_CONF_PM (_ULCAST_(3) << 7)
|
||
|
#define R10K_CONF_EC (_ULCAST_(15)<< 9)
|
||
|
#define R10K_CONF_SB (_ULCAST_(1) << 13)
|
||
|
#define R10K_CONF_SK (_ULCAST_(1) << 14)
|
||
|
#define R10K_CONF_SS (_ULCAST_(7) << 16)
|
||
|
#define R10K_CONF_SC (_ULCAST_(7) << 19)
|
||
|
#define R10K_CONF_DC (_ULCAST_(7) << 26)
|
||
|
#define R10K_CONF_IC (_ULCAST_(7) << 29)
|
||
|
|
||
|
/* Bits specific to the R30xx. */
|
||
|
#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
|
||
|
#define R30XX_CONF_REV (_ULCAST_(1) << 22)
|
||
|
#define R30XX_CONF_AC (_ULCAST_(1) << 23)
|
||
|
#define R30XX_CONF_RF (_ULCAST_(1) << 24)
|
||
|
#define R30XX_CONF_HALT (_ULCAST_(1) << 25)
|
||
|
#define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
|
||
|
#define R30XX_CONF_DBR (_ULCAST_(1) << 29)
|
||
|
#define R30XX_CONF_SB (_ULCAST_(1) << 30)
|
||
|
#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
|
||
|
|
||
|
/* Bits specific to the TX49. */
|
||
|
#define TX49_CONF_DC (_ULCAST_(1) << 16)
|
||
|
#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
|
||
|
#define TX49_CONF_HALT (_ULCAST_(1) << 18)
|
||
|
#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
|
||
|
|
||
|
/* Bits specific to the MIPS32/64 PRA. */
|
||
|
#define MIPS_CONF_MT (_ULCAST_(7) << 7)
|
||
|
#define MIPS_CONF_AR (_ULCAST_(7) << 10)
|
||
|
#define MIPS_CONF_AT (_ULCAST_(3) << 13)
|
||
|
#define MIPS_CONF_M (_ULCAST_(1) << 31)
|
||
|
|
||
|
/*
|
||
|
* Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
|
||
|
*/
|
||
|
#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
|
||
|
#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
|
||
|
#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
|
||
|
#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
|
||
|
#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
|
||
|
#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
|
||
|
#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
|
||
|
#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
|
||
|
#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
|
||
|
#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
|
||
|
#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
|
||
|
#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
|
||
|
#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
|
||
|
#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
|
||
|
|
||
|
#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
|
||
|
#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
|
||
|
#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
|
||
|
#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
|
||
|
#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
|
||
|
#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
|
||
|
#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
|
||
|
#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
|
||
|
|
||
|
#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
|
||
|
#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
|
||
|
#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
|
||
|
#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
|
||
|
#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
|
||
|
#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
|
||
|
#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
|
||
|
#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
|
||
|
#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
|
||
|
|
||
|
#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
|
||
|
#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
|
||
|
#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
|
||
|
|
||
|
#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
|
||
|
|
||
|
#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
|
||
|
|
||
|
|
||
|
/*
|
||
|
* Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
|
||
|
*/
|
||
|
#define MIPS_FPIR_S (_ULCAST_(1) << 16)
|
||
|
#define MIPS_FPIR_D (_ULCAST_(1) << 17)
|
||
|
#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
|
||
|
#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
|
||
|
#define MIPS_FPIR_W (_ULCAST_(1) << 20)
|
||
|
#define MIPS_FPIR_L (_ULCAST_(1) << 21)
|
||
|
#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
|
||
|
|
||
|
#ifndef __ASSEMBLY__
|
||
|
|
||
|
/*
|
||
|
* Macros to access the system control coprocessor
|
||
|
*/
|
||
|
|
||
|
#define __read_32bit_c0_register(source, sel) \
|
||
|
({ int __res; \
|
||
|
if (sel == 0) \
|
||
|
__asm__ __volatile__( \
|
||
|
"mfc0\t%0, " #source "\n\t" \
|
||
|
: "=r" (__res)); \
|
||
|
else \
|
||
|
__asm__ __volatile__( \
|
||
|
".set\tmips32\n\t" \
|
||
|
"mfc0\t%0, " #source ", " #sel "\n\t" \
|
||
|
".set\tmips0\n\t" \
|
||
|
: "=r" (__res)); \
|
||
|
__res; \
|
||
|
})
|
||
|
|
||
|
#define __read_64bit_c0_register(source, sel) \
|
||
|
({ unsigned long long __res; \
|
||
|
if (sizeof(unsigned long) == 4) \
|
||
|
__res = __read_64bit_c0_split(source, sel); \
|
||
|
else if (sel == 0) \
|
||
|
__asm__ __volatile__( \
|
||
|
".set\tmips3\n\t" \
|
||
|
"dmfc0\t%0, " #source "\n\t" \
|
||
|
".set\tmips0" \
|
||
|
: "=r" (__res)); \
|
||
|
else \
|
||
|
__asm__ __volatile__( \
|
||
|
".set\tmips64\n\t" \
|
||
|
"dmfc0\t%0, " #source ", " #sel "\n\t" \
|
||
|
".set\tmips0" \
|
||
|
: "=r" (__res)); \
|
||
|
__res; \
|
||
|
})
|
||
|
|
||
|
#define __write_32bit_c0_register(register, sel, value) \
|
||
|
do { \
|
||
|
if (sel == 0) \
|
||
|
__asm__ __volatile__( \
|
||
|
"mtc0\t%z0, " #register "\n\t" \
|
||
|
: : "Jr" ((unsigned int)(value))); \
|
||
|
else \
|
||
|
__asm__ __volatile__( \
|
||
|
".set\tmips32\n\t" \
|
||
|
"mtc0\t%z0, " #register ", " #sel "\n\t" \
|
||
|
".set\tmips0" \
|
||
|
: : "Jr" ((unsigned int)(value))); \
|
||
|
} while (0)
|
||
|
|
||
|
#define __write_64bit_c0_register(register, sel, value) \
|
||
|
do { \
|
||
|
if (sizeof(unsigned long) == 4) \
|
||
|
__write_64bit_c0_split(register, sel, value); \
|
||
|
else if (sel == 0) \
|
||
|
__asm__ __volatile__( \
|
||
|
".set\tmips3\n\t" \
|
||
|
"dmtc0\t%z0, " #register "\n\t" \
|
||
|
".set\tmips0" \
|
||
|
: : "Jr" (value)); \
|
||
|
else \
|
||
|
__asm__ __volatile__( \
|
||
|
".set\tmips64\n\t" \
|
||
|
"dmtc0\t%z0, " #register ", " #sel "\n\t" \
|
||
|
".set\tmips0" \
|
||
|
: : "Jr" (value)); \
|
||
|
} while (0)
|
||
|
|
||
|
#define __read_ulong_c0_register(reg, sel) \
|
||
|
((sizeof(unsigned long) == 4) ? \
|
||
|
(unsigned long) __read_32bit_c0_register(reg, sel) : \
|
||
|
(unsigned long) __read_64bit_c0_register(reg, sel))
|
||
|
|
||
|
#define __write_ulong_c0_register(reg, sel, val) \
|
||
|
do { \
|
||
|
if (sizeof(unsigned long) == 4) \
|
||
|
__write_32bit_c0_register(reg, sel, val); \
|
||
|
else \
|
||
|
__write_64bit_c0_register(reg, sel, val); \
|
||
|
} while (0)
|
||
|
|
||
|
/*
|
||
|
* On RM7000/RM9000 these are uses to access cop0 set 1 registers
|
||
|
*/
|
||
|
#define __read_32bit_c0_ctrl_register(source) \
|
||
|
({ int __res; \
|
||
|
__asm__ __volatile__( \
|
||
|
"cfc0\t%0, " #source "\n\t" \
|
||
|
: "=r" (__res)); \
|
||
|
__res; \
|
||
|
})
|
||
|
|
||
|
#define __write_32bit_c0_ctrl_register(register, value) \
|
||
|
do { \
|
||
|
__asm__ __volatile__( \
|
||
|
"ctc0\t%z0, " #register "\n\t" \
|
||
|
: : "Jr" ((unsigned int)(value))); \
|
||
|
} while (0)
|
||
|
|
||
|
/*
|
||
|
* These versions are only needed for systems with more than 38 bits of
|
||
|
* physical address space running the 32-bit kernel. That's none atm :-)
|
||
|
*/
|
||
|
#define __read_64bit_c0_split(source, sel) \
|
||
|
({ \
|
||
|
unsigned long long __val; \
|
||
|
unsigned long __flags; \
|
||
|
\
|
||
|
local_irq_save(__flags); \
|
||
|
if (sel == 0) \
|
||
|
__asm__ __volatile__( \
|
||
|
".set\tmips64\n\t" \
|
||
|
"dmfc0\t%M0, " #source "\n\t" \
|
||
|
"dsll\t%L0, %M0, 32\n\t" \
|
||
|
"dsra\t%M0, %M0, 32\n\t" \
|
||
|
"dsra\t%L0, %L0, 32\n\t" \
|
||
|
".set\tmips0" \
|
||
|
: "=r" (__val)); \
|
||
|
else \
|
||
|
__asm__ __volatile__( \
|
||
|
".set\tmips64\n\t" \
|
||
|
"dmfc0\t%M0, " #source ", " #sel "\n\t" \
|
||
|
"dsll\t%L0, %M0, 32\n\t" \
|
||
|
"dsra\t%M0, %M0, 32\n\t" \
|
||
|
"dsra\t%L0, %L0, 32\n\t" \
|
||
|
".set\tmips0" \
|
||
|
: "=r" (__val)); \
|
||
|
local_irq_restore(__flags); \
|
||
|
\
|
||
|
__val; \
|
||
|
})
|
||
|
|
||
|
#define __write_64bit_c0_split(source, sel, val) \
|
||
|
do { \
|
||
|
unsigned long __flags; \
|
||
|
\
|
||
|
local_irq_save(__flags); \
|
||
|
if (sel == 0) \
|
||
|
__asm__ __volatile__( \
|
||
|
".set\tmips64\n\t" \
|
||
|
"dsll\t%L0, %L0, 32\n\t" \
|
||
|
"dsrl\t%L0, %L0, 32\n\t" \
|
||
|
"dsll\t%M0, %M0, 32\n\t" \
|
||
|
"or\t%L0, %L0, %M0\n\t" \
|
||
|
"dmtc0\t%L0, " #source "\n\t" \
|
||
|
".set\tmips0" \
|
||
|
: : "r" (val)); \
|
||
|
else \
|
||
|
__asm__ __volatile__( \
|
||
|
".set\tmips64\n\t" \
|
||
|
"dsll\t%L0, %L0, 32\n\t" \
|
||
|
"dsrl\t%L0, %L0, 32\n\t" \
|
||
|
"dsll\t%M0, %M0, 32\n\t" \
|
||
|
"or\t%L0, %L0, %M0\n\t" \
|
||
|
"dmtc0\t%L0, " #source ", " #sel "\n\t" \
|
||
|
".set\tmips0" \
|
||
|
: : "r" (val)); \
|
||
|
local_irq_restore(__flags); \
|
||
|
} while (0)
|
||
|
|
||
|
#define read_c0_index() __read_32bit_c0_register($0, 0)
|
||
|
#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
|
||
|
|
||
|
#define read_c0_random() __read_32bit_c0_register($1, 0)
|
||
|
#define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
|
||
|
|
||
|
#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
|
||
|
#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
|
||
|
|
||
|
#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
|
||
|
#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
|
||
|
|
||
|
#define read_c0_conf() __read_32bit_c0_register($3, 0)
|
||
|
#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
|
||
|
|
||
|
#define read_c0_context() __read_ulong_c0_register($4, 0)
|
||
|
#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
|
||
|
|
||
|
#define read_c0_userlocal() __read_ulong_c0_register($4, 2)
|
||
|
#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
|
||
|
|
||
|
#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
|
||
|
#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
|
||
|
|
||
|
#define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
|
||
|
#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
|
||
|
|
||
|
#define read_c0_wired() __read_32bit_c0_register($6, 0)
|
||
|
#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
|
||
|
|
||
|
#define read_c0_info() __read_32bit_c0_register($7, 0)
|
||
|
|
||
|
#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
|
||
|
#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
|
||
|
|
||
|
#define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
|
||
|
#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
|
||
|
|
||
|
#define read_c0_count() __read_32bit_c0_register($9, 0)
|
||
|
#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
|
||
|
|
||
|
#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
|
||
|
#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
|
||
|
|
||
|
#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
|
||
|
#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
|
||
|
|
||
|
#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
|
||
|
#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
|
||
|
|
||
|
#define read_c0_compare() __read_32bit_c0_register($11, 0)
|
||
|
#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
|
||
|
|
||
|
#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
|
||
|
#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
|
||
|
|
||
|
#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
|
||
|
#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
|
||
|
|
||
|
#define read_c0_status() __read_32bit_c0_register($12, 0)
|
||
|
#ifdef CONFIG_MIPS_MT_SMTC
|
||
|
#define write_c0_status(val) \
|
||
|
do { \
|
||
|
__write_32bit_c0_register($12, 0, val); \
|
||
|
__ehb(); \
|
||
|
} while (0)
|
||
|
#else
|
||
|
/*
|
||
|
* Legacy non-SMTC code, which may be hazardous
|
||
|
* but which might not support EHB
|
||
|
*/
|
||
|
#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
|
||
|
#endif /* CONFIG_MIPS_MT_SMTC */
|
||
|
|
||
|
#define read_c0_cause() __read_32bit_c0_register($13, 0)
|
||
|
#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
|
||
|
|
||
|
#define read_c0_epc() __read_ulong_c0_register($14, 0)
|
||
|
#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
|
||
|
|
||
|
#define read_c0_prid() __read_32bit_c0_register($15, 0)
|
||
|
|
||
|
#define read_c0_config() __read_32bit_c0_register($16, 0)
|
||
|
#define read_c0_config1() __read_32bit_c0_register($16, 1)
|
||
|
#define read_c0_config2() __read_32bit_c0_register($16, 2)
|
||
|
#define read_c0_config3() __read_32bit_c0_register($16, 3)
|
||
|
#define read_c0_config4() __read_32bit_c0_register($16, 4)
|
||
|
#define read_c0_config5() __read_32bit_c0_register($16, 5)
|
||
|
#define read_c0_config6() __read_32bit_c0_register($16, 6)
|
||
|
#define read_c0_config7() __read_32bit_c0_register($16, 7)
|
||
|
#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
|
||
|
#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
|
||
|
#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
|
||
|
#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
|
||
|
#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
|
||
|
#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
|
||
|
#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
|
||
|
#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
|
||
|
|
||
|
/*
|
||
|
* The WatchLo register. There may be up to 8 of them.
|
||
|
*/
|
||
|
#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
|
||
|
#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
|
||
|
#define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
|
||
|
#define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
|
||
|
#define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
|
||
|
#define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
|
||
|
#define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
|
||
|
#define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
|
||
|
#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
|
||
|
#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
|
||
|
#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
|
||
|
#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
|
||
|
#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
|
||
|
#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
|
||
|
#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
|
||
|
#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
|
||
|
|
||
|
/*
|
||
|
* The WatchHi register. There may be up to 8 of them.
|
||
|
*/
|
||
|
#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
|
||
|
#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
|
||
|
#define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
|
||
|
#define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
|
||
|
#define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
|
||
|
#define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
|
||
|
#define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
|
||
|
#define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
|
||
|
|
||
|
#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
|
||
|
#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
|
||
|
#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
|
||
|
#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
|
||
|
#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
|
||
|
#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
|
||
|
#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
|
||
|
#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
|
||
|
|
||
|
#define read_c0_xcontext() __read_ulong_c0_register($20, 0)
|
||
|
#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
|
||
|
|
||
|
#define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
|
||
|
#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
|
||
|
|
||
|
#define read_c0_framemask() __read_32bit_c0_register($21, 0)
|
||
|
#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
|
||
|
|
||
|
/* RM9000 PerfControl performance counter control register */
|
||
|
#define read_c0_perfcontrol() __read_32bit_c0_register($22, 0)
|
||
|
#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
|
||
|
|
||
|
#define read_c0_diag() __read_32bit_c0_register($22, 0)
|
||
|
#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
|
||
|
|
||
|
#define read_c0_diag1() __read_32bit_c0_register($22, 1)
|
||
|
#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
|
||
|
|
||
|
#define read_c0_diag2() __read_32bit_c0_register($22, 2)
|
||
|
#define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
|
||
|
|
||
|
#define read_c0_diag3() __read_32bit_c0_register($22, 3)
|
||
|
#define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
|
||
|
|
||
|
#define read_c0_diag4() __read_32bit_c0_register($22, 4)
|
||
|
#define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
|
||
|
|
||
|
#define read_c0_diag5() __read_32bit_c0_register($22, 5)
|
||
|
#define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
|
||
|
|
||
|
#define read_c0_debug() __read_32bit_c0_register($23, 0)
|
||
|
#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
|
||
|
|
||
|
#define read_c0_depc() __read_ulong_c0_register($24, 0)
|
||
|
#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
|
||
|
|
||
|
/*
|
||
|
* MIPS32 / MIPS64 performance counters
|
||
|
*/
|
||
|
#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
|
||
|
#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
|
||
|
#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
|
||
|
#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
|
||
|
#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
|
||
|
#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
|
||
|
#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
|
||
|
#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
|
||
|
#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
|
||
|
#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
|
||
|
#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
|
||
|
#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
|
||
|
#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
|
||
|
#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
|
||
|
#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
|
||
|
#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
|
||
|
|
||
|
/* RM9000 PerfCount performance counter register */
|
||
|
#define read_c0_perfcount() __read_64bit_c0_register($25, 0)
|
||
|
#define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
|
||
|
|
||
|
#define read_c0_ecc() __read_32bit_c0_register($26, 0)
|
||
|
#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
|
||
|
|
||
|
#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
|
||
|
#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
|
||
|
|
||
|
#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
|
||
|
|
||
|
#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
|
||
|
#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
|
||
|
|
||
|
#define read_c0_taglo() __read_32bit_c0_register($28, 0)
|
||
|
#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
|
||
|
|
||
|
#define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
|
||
|
#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
|
||
|
|
||
|
#define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
|
||
|
#define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
|
||
|
|
||
|
#define read_c0_staglo() __read_32bit_c0_register($28, 4)
|
||
|
#define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
|
||
|
|
||
|
#define read_c0_taghi() __read_32bit_c0_register($29, 0)
|
||
|
#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
|
||
|
|
||
|
#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
|
||
|
#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
|
||
|
|
||
|
/* MIPSR2 */
|
||
|
#define read_c0_hwrena() __read_32bit_c0_register($7, 0)
|
||
|
#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
|
||
|
|
||
|
#define read_c0_intctl() __read_32bit_c0_register($12, 1)
|
||
|
#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
|
||
|
|
||
|
#define read_c0_srsctl() __read_32bit_c0_register($12, 2)
|
||
|
#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
|
||
|
|
||
|
#define read_c0_srsmap() __read_32bit_c0_register($12, 3)
|
||
|
#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
|
||
|
|
||
|
#define read_c0_ebase() __read_32bit_c0_register($15, 1)
|
||
|
#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
|
||
|
|
||
|
/* BMIPS3300 */
|
||
|
#define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
|
||
|
#define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
|
||
|
|
||
|
#define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
|
||
|
#define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
|
||
|
|
||
|
#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
|
||
|
#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
|
||
|
|
||
|
/* BMIPS4380 */
|
||
|
#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
|
||
|
#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
|
||
|
|
||
|
#define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
|
||
|
#define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
|
||
|
|
||
|
#define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
|
||
|
#define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
|
||
|
|
||
|
#define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
|
||
|
#define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
|
||
|
|
||
|
#define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
|
||
|
#define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
|
||
|
|
||
|
/* BMIPS5000 */
|
||
|
#define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
|
||
|
#define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
|
||
|
|
||
|
#define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
|
||
|
#define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
|
||
|
|
||
|
#define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
|
||
|
#define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
|
||
|
|
||
|
#define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
|
||
|
#define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
|
||
|
|
||
|
#define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
|
||
|
#define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
|
||
|
|
||
|
#define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
|
||
|
#define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
|
||
|
|
||
|
#endif /* !__ASSEMBLY__ */
|
||
|
|
||
|
#endif /* _ASM_MIPSREGS_H */
|