2011-12-18 22:20:48 +00:00
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/*
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* Freescale i.MX28 APBH DMA driver
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*
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* Copyright (C) 2011 Wolfram Sang <w.sang@pengutronix.de>
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* Based on code from LTIB:
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* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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2013-07-09 14:47:09 +00:00
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#include <dma/apbh-dma.h>
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#include <stmp-device.h>
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2011-12-18 22:20:48 +00:00
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#include <linux/list.h>
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#include <common.h>
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2013-07-09 11:56:50 +00:00
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#include <driver.h>
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2011-12-18 22:20:48 +00:00
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#include <malloc.h>
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#include <errno.h>
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2013-07-09 14:47:09 +00:00
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#include <init.h>
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#include <io.h>
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2011-12-18 22:20:48 +00:00
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#include <asm/mmu.h>
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#define HW_APBHX_CTRL0 0x000
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#define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29)
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#define BM_APBH_CTRL0_APB_BURST_EN (1 << 28)
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#define BP_APBH_CTRL0_CLKGATE_CHANNEL 8
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#define BP_APBH_CTRL0_RESET_CHANNEL 16
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#define HW_APBHX_CTRL1 0x010
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#define BP_APBHX_CTRL1_CH_CMDCMPLT_IRQ_EN 16
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#define HW_APBHX_CTRL2 0x020
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#define HW_APBHX_CHANNEL_CTRL 0x030
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#define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16
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#define BP_APBHX_VERSION_MAJOR 24
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2013-07-09 11:56:50 +00:00
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#define HW_APBHX_CHn_NXTCMDAR_MX23(n) (0x050 + (n) * 0x70)
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#define HW_APBHX_CHn_NXTCMDAR_MX28(n) (0x110 + (n) * 0x70)
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#define HW_APBHX_CHn_SEMA_MX23(n) (0x080 + (n) * 0x70)
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#define HW_APBHX_CHn_SEMA_MX28(n) (0x140 + (n) * 0x70)
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2011-12-18 22:20:48 +00:00
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#define BM_APBHX_CHn_SEMA_PHORE (0xff << 16)
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#define BP_APBHX_CHn_SEMA_PHORE 16
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static struct mxs_dma_chan mxs_dma_channels[MXS_MAX_DMA_CHANNELS];
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2013-07-09 11:56:50 +00:00
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enum mxs_dma_id {
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IMX23_DMA,
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IMX28_DMA,
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};
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2011-12-18 22:20:48 +00:00
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2013-07-09 11:56:38 +00:00
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struct apbh_dma {
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void __iomem *regs;
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2013-07-09 11:56:50 +00:00
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enum mxs_dma_id id;
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2013-07-09 11:56:38 +00:00
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};
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2013-07-09 11:56:50 +00:00
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#define apbh_dma_is_imx23(aphb) ((apbh)->id == IMX23_DMA)
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2013-07-09 11:56:38 +00:00
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static struct apbh_dma *apbh_dma;
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2011-12-18 22:20:48 +00:00
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/*
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* Test is the DMA channel is valid channel
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*/
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int mxs_dma_validate_chan(int channel)
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{
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struct mxs_dma_chan *pchan;
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if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS))
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return -EINVAL;
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pchan = mxs_dma_channels + channel;
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if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
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return -EINVAL;
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return 0;
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}
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/*
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* Return the address of the command within a descriptor.
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*/
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static unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc)
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{
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return desc->address + offsetof(struct mxs_dma_desc, cmd);
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}
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/*
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* Read a DMA channel's hardware semaphore.
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*
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* As used by the MXS platform's DMA software, the DMA channel's hardware
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* semaphore reflects the number of DMA commands the hardware will process, but
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* has not yet finished. This is a volatile value read directly from hardware,
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* so it must be be viewed as immediately stale.
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*
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* If the channel is not marked busy, or has finished processing all its
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* commands, this value should be zero.
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*
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* See mxs_dma_append() for details on how DMA command blocks must be configured
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* to maintain the expected behavior of the semaphore's value.
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*/
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static int mxs_dma_read_semaphore(int channel)
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{
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2013-07-09 11:56:38 +00:00
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struct apbh_dma *apbh = apbh_dma;
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2011-12-18 22:20:48 +00:00
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uint32_t tmp;
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int ret;
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ret = mxs_dma_validate_chan(channel);
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if (ret)
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return ret;
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2013-07-09 11:56:50 +00:00
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if (apbh_dma_is_imx23(apbh))
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tmp = readl(apbh->regs + HW_APBHX_CHn_SEMA_MX23(channel));
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else
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tmp = readl(apbh->regs + HW_APBHX_CHn_SEMA_MX28(channel));
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2011-12-18 22:20:48 +00:00
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tmp &= BM_APBHX_CHn_SEMA_PHORE;
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tmp >>= BP_APBHX_CHn_SEMA_PHORE;
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return tmp;
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}
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/*
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* Enable a DMA channel.
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*
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* If the given channel has any DMA descriptors on its active list, this
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* function causes the DMA hardware to begin processing them.
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*
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* This function marks the DMA channel as "busy," whether or not there are any
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* descriptors to process.
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*/
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static int mxs_dma_enable(int channel)
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{
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2013-07-09 11:56:38 +00:00
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struct apbh_dma *apbh = apbh_dma;
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2011-12-18 22:20:48 +00:00
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unsigned int sem;
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struct mxs_dma_chan *pchan;
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struct mxs_dma_desc *pdesc;
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int channel_bit, ret;
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ret = mxs_dma_validate_chan(channel);
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if (ret)
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return ret;
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pchan = mxs_dma_channels + channel;
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if (pchan->pending_num == 0) {
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pchan->flags |= MXS_DMA_FLAGS_BUSY;
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return 0;
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}
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pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node);
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if (pdesc == NULL)
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return -EFAULT;
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if (pchan->flags & MXS_DMA_FLAGS_BUSY) {
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if (!(pdesc->cmd.data & MXS_DMA_DESC_CHAIN))
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return 0;
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sem = mxs_dma_read_semaphore(channel);
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if (sem == 0)
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return 0;
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if (sem == 1) {
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pdesc = list_entry(pdesc->node.next,
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struct mxs_dma_desc, node);
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2013-07-09 11:56:50 +00:00
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if (apbh_dma_is_imx23(apbh))
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writel(mxs_dma_cmd_address(pdesc),
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apbh->regs + HW_APBHX_CHn_NXTCMDAR_MX23(channel));
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else
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writel(mxs_dma_cmd_address(pdesc),
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apbh->regs + HW_APBHX_CHn_NXTCMDAR_MX28(channel));
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2011-12-18 22:20:48 +00:00
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}
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2013-07-09 11:56:50 +00:00
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if (apbh_dma_is_imx23(apbh))
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writel(pchan->pending_num,
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apbh->regs + HW_APBHX_CHn_SEMA_MX23(channel));
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else
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writel(pchan->pending_num,
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apbh->regs + HW_APBHX_CHn_SEMA_MX28(channel));
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2011-12-18 22:20:48 +00:00
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pchan->active_num += pchan->pending_num;
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pchan->pending_num = 0;
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} else {
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pchan->active_num += pchan->pending_num;
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pchan->pending_num = 0;
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2013-07-09 11:56:50 +00:00
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if (apbh_dma_is_imx23(apbh)) {
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writel(mxs_dma_cmd_address(pdesc),
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apbh->regs + HW_APBHX_CHn_NXTCMDAR_MX23(channel));
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writel(pchan->active_num,
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apbh->regs + HW_APBHX_CHn_SEMA_MX23(channel));
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channel_bit = channel + BP_APBH_CTRL0_CLKGATE_CHANNEL;
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} else {
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writel(mxs_dma_cmd_address(pdesc),
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apbh->regs + HW_APBHX_CHn_NXTCMDAR_MX28(channel));
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writel(pchan->active_num,
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apbh->regs + HW_APBHX_CHn_SEMA_MX28(channel));
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channel_bit = channel;
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}
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2013-07-09 11:56:38 +00:00
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writel(1 << channel_bit, apbh->regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_CLR);
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2011-12-18 22:20:48 +00:00
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}
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pchan->flags |= MXS_DMA_FLAGS_BUSY;
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return 0;
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}
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/*
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* Disable a DMA channel.
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*
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* This function shuts down a DMA channel and marks it as "not busy." Any
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* descriptors on the active list are immediately moved to the head of the
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* "done" list, whether or not they have actually been processed by the
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* hardware. The "ready" flags of these descriptors are NOT cleared, so they
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* still appear to be active.
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*
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* This function immediately shuts down a DMA channel's hardware, aborting any
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* I/O that may be in progress, potentially leaving I/O hardware in an undefined
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* state. It is unwise to call this function if there is ANY chance the hardware
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* is still processing a command.
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*/
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static int mxs_dma_disable(int channel)
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{
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struct mxs_dma_chan *pchan;
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2013-07-09 11:56:38 +00:00
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struct apbh_dma *apbh = apbh_dma;
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2011-12-18 22:20:48 +00:00
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int channel_bit, ret;
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ret = mxs_dma_validate_chan(channel);
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if (ret)
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return ret;
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pchan = mxs_dma_channels + channel;
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if (!(pchan->flags & MXS_DMA_FLAGS_BUSY))
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return -EINVAL;
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2013-07-09 11:56:50 +00:00
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if (apbh_dma_is_imx23(apbh))
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channel_bit = channel + BP_APBH_CTRL0_CLKGATE_CHANNEL;
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else
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channel_bit = channel + 0;
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2013-07-09 11:56:38 +00:00
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writel(1 << channel_bit, apbh->regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
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2011-12-18 22:20:48 +00:00
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pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
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pchan->active_num = 0;
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pchan->pending_num = 0;
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list_splice_init(&pchan->active, &pchan->done);
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return 0;
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}
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/*
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* Resets the DMA channel hardware.
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*/
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static int mxs_dma_reset(int channel)
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{
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2013-07-09 11:56:38 +00:00
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struct apbh_dma *apbh = apbh_dma;
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2011-12-18 22:20:48 +00:00
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int ret;
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ret = mxs_dma_validate_chan(channel);
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if (ret)
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return ret;
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2013-07-09 11:56:50 +00:00
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if (apbh_dma_is_imx23(apbh))
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2011-12-18 22:20:48 +00:00
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writel(1 << (channel + BP_APBH_CTRL0_RESET_CHANNEL),
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2013-07-09 11:56:38 +00:00
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apbh->regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
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2011-12-18 22:20:48 +00:00
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else
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writel(1 << (channel + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
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2013-07-09 11:56:38 +00:00
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apbh->regs + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET);
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2011-12-18 22:20:48 +00:00
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return 0;
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}
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/*
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* Enable or disable DMA interrupt.
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*
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* This function enables the given DMA channel to interrupt the CPU.
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*/
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static int mxs_dma_enable_irq(int channel, int enable)
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{
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2013-07-09 11:56:38 +00:00
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struct apbh_dma *apbh = apbh_dma;
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2011-12-18 22:20:48 +00:00
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int ret;
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ret = mxs_dma_validate_chan(channel);
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if (ret)
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return ret;
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if (enable)
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writel(1 << (channel + BP_APBHX_CTRL1_CH_CMDCMPLT_IRQ_EN),
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2013-07-09 11:56:38 +00:00
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apbh->regs + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET);
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2011-12-18 22:20:48 +00:00
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else
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writel(1 << (channel + BP_APBHX_CTRL1_CH_CMDCMPLT_IRQ_EN),
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2013-07-09 11:56:38 +00:00
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apbh->regs + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR);
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2011-12-18 22:20:48 +00:00
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return 0;
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}
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/*
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* Clear DMA interrupt.
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*
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* The software that is using the DMA channel must register to receive its
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* interrupts and, when they arrive, must call this function to clear them.
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*/
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static int mxs_dma_ack_irq(int channel)
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{
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2013-07-09 11:56:38 +00:00
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struct apbh_dma *apbh = apbh_dma;
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2011-12-18 22:20:48 +00:00
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int ret;
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ret = mxs_dma_validate_chan(channel);
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if (ret)
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return ret;
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2013-07-09 11:56:38 +00:00
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writel(1 << channel, apbh->regs + HW_APBHX_CTRL1 + STMP_OFFSET_REG_CLR);
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writel(1 << channel, apbh->regs + HW_APBHX_CTRL2 + STMP_OFFSET_REG_CLR);
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2011-12-18 22:20:48 +00:00
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return 0;
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}
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/*
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* Request to reserve a DMA channel
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*/
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static int mxs_dma_request(int channel)
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{
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struct mxs_dma_chan *pchan;
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if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS))
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|
return -EINVAL;
|
|
|
|
|
|
|
|
pchan = mxs_dma_channels + channel;
|
|
|
|
if ((pchan->flags & MXS_DMA_FLAGS_VALID) != MXS_DMA_FLAGS_VALID)
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
if (pchan->flags & MXS_DMA_FLAGS_ALLOCATED)
|
|
|
|
return -EBUSY;
|
|
|
|
|
|
|
|
pchan->flags |= MXS_DMA_FLAGS_ALLOCATED;
|
|
|
|
pchan->active_num = 0;
|
|
|
|
pchan->pending_num = 0;
|
|
|
|
|
|
|
|
INIT_LIST_HEAD(&pchan->active);
|
|
|
|
INIT_LIST_HEAD(&pchan->done);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Release a DMA channel.
|
|
|
|
*
|
|
|
|
* This function releases a DMA channel from its current owner.
|
|
|
|
*
|
|
|
|
* The channel will NOT be released if it's marked "busy" (see
|
|
|
|
* mxs_dma_enable()).
|
|
|
|
*/
|
|
|
|
static int mxs_dma_release(int channel)
|
|
|
|
{
|
|
|
|
struct mxs_dma_chan *pchan;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = mxs_dma_validate_chan(channel);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
pchan = mxs_dma_channels + channel;
|
|
|
|
|
|
|
|
if (pchan->flags & MXS_DMA_FLAGS_BUSY)
|
|
|
|
return -EBUSY;
|
|
|
|
|
|
|
|
pchan->dev = 0;
|
|
|
|
pchan->active_num = 0;
|
|
|
|
pchan->pending_num = 0;
|
|
|
|
pchan->flags &= ~MXS_DMA_FLAGS_ALLOCATED;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Allocate DMA descriptor
|
|
|
|
*/
|
|
|
|
struct mxs_dma_desc *mxs_dma_desc_alloc(void)
|
|
|
|
{
|
|
|
|
struct mxs_dma_desc *pdesc;
|
|
|
|
|
|
|
|
pdesc = dma_alloc_coherent(sizeof(struct mxs_dma_desc));
|
|
|
|
|
|
|
|
if (pdesc == NULL)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
memset(pdesc, 0, sizeof(*pdesc));
|
|
|
|
pdesc->address = (dma_addr_t)pdesc;
|
|
|
|
|
|
|
|
return pdesc;
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Free DMA descriptor
|
|
|
|
*/
|
|
|
|
void mxs_dma_desc_free(struct mxs_dma_desc *pdesc)
|
|
|
|
{
|
|
|
|
if (pdesc == NULL)
|
|
|
|
return;
|
|
|
|
|
|
|
|
free(pdesc);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Add a DMA descriptor to a channel.
|
|
|
|
*
|
|
|
|
* If the descriptor list for this channel is not empty, this function sets the
|
|
|
|
* CHAIN bit and the NEXTCMD_ADDR fields in the last descriptor's DMA command so
|
|
|
|
* it will chain to the new descriptor's command.
|
|
|
|
*
|
|
|
|
* Then, this function marks the new descriptor as "ready," adds it to the end
|
|
|
|
* of the active descriptor list, and increments the count of pending
|
|
|
|
* descriptors.
|
|
|
|
*
|
|
|
|
* The MXS platform DMA software imposes some rules on DMA commands to maintain
|
|
|
|
* important invariants. These rules are NOT checked, but they must be carefully
|
|
|
|
* applied by software that uses MXS DMA channels.
|
|
|
|
*
|
|
|
|
* Invariant:
|
|
|
|
* The DMA channel's hardware semaphore must reflect the number of DMA
|
|
|
|
* commands the hardware will process, but has not yet finished.
|
|
|
|
*
|
|
|
|
* Explanation:
|
|
|
|
* A DMA channel begins processing commands when its hardware semaphore is
|
|
|
|
* written with a value greater than zero, and it stops processing commands
|
|
|
|
* when the semaphore returns to zero.
|
|
|
|
*
|
|
|
|
* When a channel finishes a DMA command, it will decrement its semaphore if
|
|
|
|
* the DECREMENT_SEMAPHORE bit is set in that command's flags bits.
|
|
|
|
*
|
|
|
|
* In principle, it's not necessary for the DECREMENT_SEMAPHORE to be set,
|
|
|
|
* unless it suits the purposes of the software. For example, one could
|
|
|
|
* construct a series of five DMA commands, with the DECREMENT_SEMAPHORE
|
|
|
|
* bit set only in the last one. Then, setting the DMA channel's hardware
|
|
|
|
* semaphore to one would cause the entire series of five commands to be
|
|
|
|
* processed. However, this example would violate the invariant given above.
|
|
|
|
*
|
|
|
|
* Rule:
|
|
|
|
* ALL DMA commands MUST have the DECREMENT_SEMAPHORE bit set so that the DMA
|
|
|
|
* channel's hardware semaphore will be decremented EVERY time a command is
|
|
|
|
* processed.
|
|
|
|
*/
|
|
|
|
int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc)
|
|
|
|
{
|
|
|
|
struct mxs_dma_chan *pchan;
|
|
|
|
struct mxs_dma_desc *last;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = mxs_dma_validate_chan(channel);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
pchan = mxs_dma_channels + channel;
|
|
|
|
|
|
|
|
pdesc->cmd.next = mxs_dma_cmd_address(pdesc);
|
|
|
|
pdesc->flags |= MXS_DMA_DESC_FIRST | MXS_DMA_DESC_LAST;
|
|
|
|
|
|
|
|
if (!list_empty(&pchan->active)) {
|
|
|
|
last = list_entry(pchan->active.prev, struct mxs_dma_desc,
|
|
|
|
node);
|
|
|
|
|
|
|
|
pdesc->flags &= ~MXS_DMA_DESC_FIRST;
|
|
|
|
last->flags &= ~MXS_DMA_DESC_LAST;
|
|
|
|
|
|
|
|
last->cmd.next = mxs_dma_cmd_address(pdesc);
|
|
|
|
last->cmd.data |= MXS_DMA_DESC_CHAIN;
|
|
|
|
}
|
|
|
|
pdesc->flags |= MXS_DMA_DESC_READY;
|
|
|
|
if (pdesc->flags & MXS_DMA_DESC_FIRST)
|
|
|
|
pchan->pending_num++;
|
|
|
|
list_add_tail(&pdesc->node, &pchan->active);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Clean up processed DMA descriptors.
|
|
|
|
*
|
|
|
|
* This function removes processed DMA descriptors from the "active" list. Pass
|
|
|
|
* in a non-NULL list head to get the descriptors moved to your list. Pass NULL
|
|
|
|
* to get the descriptors moved to the channel's "done" list. Descriptors on
|
|
|
|
* the "done" list can be retrieved with mxs_dma_get_finished().
|
|
|
|
*
|
|
|
|
* This function marks the DMA channel as "not busy" if no unprocessed
|
|
|
|
* descriptors remain on the "active" list.
|
|
|
|
*/
|
|
|
|
static int mxs_dma_finish(int channel, struct list_head *head)
|
|
|
|
{
|
|
|
|
int sem;
|
|
|
|
struct mxs_dma_chan *pchan;
|
|
|
|
struct list_head *p, *q;
|
|
|
|
struct mxs_dma_desc *pdesc;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = mxs_dma_validate_chan(channel);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
pchan = mxs_dma_channels + channel;
|
|
|
|
|
|
|
|
sem = mxs_dma_read_semaphore(channel);
|
|
|
|
if (sem < 0)
|
|
|
|
return sem;
|
|
|
|
|
|
|
|
if (sem == pchan->active_num)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
list_for_each_safe(p, q, &pchan->active) {
|
|
|
|
if ((pchan->active_num) <= sem)
|
|
|
|
break;
|
|
|
|
|
|
|
|
pdesc = list_entry(p, struct mxs_dma_desc, node);
|
|
|
|
pdesc->flags &= ~MXS_DMA_DESC_READY;
|
|
|
|
|
|
|
|
if (head)
|
|
|
|
list_move_tail(p, head);
|
|
|
|
else
|
|
|
|
list_move_tail(p, &pchan->done);
|
|
|
|
|
|
|
|
if (pdesc->flags & MXS_DMA_DESC_LAST)
|
|
|
|
pchan->active_num--;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (sem == 0)
|
|
|
|
pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Wait for DMA channel to complete
|
|
|
|
*/
|
|
|
|
static int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan)
|
|
|
|
{
|
2013-07-09 11:56:38 +00:00
|
|
|
struct apbh_dma *apbh = apbh_dma;
|
2011-12-18 22:20:48 +00:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = mxs_dma_validate_chan(chan);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
while (--timeout) {
|
2013-07-09 11:56:38 +00:00
|
|
|
if (readl(apbh->regs + HW_APBHX_CTRL1) & (1 << chan))
|
2011-12-18 22:20:48 +00:00
|
|
|
break;
|
|
|
|
udelay(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (timeout == 0) {
|
|
|
|
ret = -ETIMEDOUT;
|
|
|
|
mxs_dma_reset(chan);
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Execute the DMA channel
|
|
|
|
*/
|
|
|
|
int mxs_dma_go(int chan)
|
|
|
|
{
|
|
|
|
uint32_t timeout = 10000;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
LIST_HEAD(tmp_desc_list);
|
|
|
|
|
|
|
|
mxs_dma_enable_irq(chan, 1);
|
|
|
|
mxs_dma_enable(chan);
|
|
|
|
|
|
|
|
/* Wait for DMA to finish. */
|
|
|
|
ret = mxs_dma_wait_complete(timeout, chan);
|
|
|
|
|
|
|
|
/* Clear out the descriptors we just ran. */
|
|
|
|
mxs_dma_finish(chan, &tmp_desc_list);
|
|
|
|
|
|
|
|
/* Shut the DMA channel down. */
|
|
|
|
mxs_dma_ack_irq(chan);
|
|
|
|
mxs_dma_reset(chan);
|
|
|
|
mxs_dma_enable_irq(chan, 0);
|
|
|
|
mxs_dma_disable(chan);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize the DMA hardware
|
|
|
|
*/
|
2013-07-09 11:56:50 +00:00
|
|
|
static int apbh_dma_probe(struct device_d *dev)
|
2011-12-18 22:20:48 +00:00
|
|
|
{
|
2013-07-09 11:56:38 +00:00
|
|
|
struct apbh_dma *apbh;
|
2011-12-18 22:20:48 +00:00
|
|
|
struct mxs_dma_chan *pchan;
|
2013-07-09 11:56:50 +00:00
|
|
|
enum mxs_dma_id id;
|
2011-12-18 22:20:48 +00:00
|
|
|
int ret, channel;
|
2013-07-09 11:56:38 +00:00
|
|
|
|
2013-07-09 11:56:50 +00:00
|
|
|
ret = dev_get_drvdata(dev, (unsigned long *)&id);
|
2012-10-30 14:21:14 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2011-12-18 22:20:48 +00:00
|
|
|
|
2013-07-09 11:56:50 +00:00
|
|
|
apbh_dma = apbh = xzalloc(sizeof(*apbh));
|
|
|
|
apbh->regs = dev_request_mem_region(dev, 0);
|
|
|
|
if (!apbh->regs)
|
|
|
|
return -EBUSY;
|
|
|
|
|
|
|
|
apbh->id = id;
|
2011-12-18 22:20:48 +00:00
|
|
|
|
2013-07-09 11:56:50 +00:00
|
|
|
ret = stmp_reset_block(apbh->regs, 0);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2011-12-18 22:20:48 +00:00
|
|
|
|
|
|
|
writel(BM_APBH_CTRL0_APB_BURST8_EN,
|
2013-07-09 11:56:38 +00:00
|
|
|
apbh->regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
|
2011-12-18 22:20:48 +00:00
|
|
|
|
|
|
|
writel(BM_APBH_CTRL0_APB_BURST_EN,
|
2013-07-09 11:56:38 +00:00
|
|
|
apbh->regs + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET);
|
2011-12-18 22:20:48 +00:00
|
|
|
|
|
|
|
for (channel = 0; channel < MXS_MAX_DMA_CHANNELS; channel++) {
|
|
|
|
pchan = mxs_dma_channels + channel;
|
|
|
|
pchan->flags = MXS_DMA_FLAGS_VALID;
|
|
|
|
|
|
|
|
ret = mxs_dma_request(channel);
|
|
|
|
|
|
|
|
if (ret) {
|
|
|
|
printf("MXS DMA: Can't acquire DMA channel %i\n",
|
|
|
|
channel);
|
|
|
|
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
mxs_dma_reset(channel);
|
|
|
|
mxs_dma_ack_irq(channel);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err:
|
|
|
|
while (--channel >= 0)
|
|
|
|
mxs_dma_release(channel);
|
|
|
|
return ret;
|
|
|
|
}
|
2013-07-09 11:56:50 +00:00
|
|
|
|
|
|
|
static struct platform_device_id apbh_ids[] = {
|
|
|
|
{
|
|
|
|
.name = "imx23-dma-apbh",
|
|
|
|
.driver_data = (unsigned long)IMX23_DMA,
|
|
|
|
}, {
|
|
|
|
.name = "imx28-dma-apbh",
|
|
|
|
.driver_data = (unsigned long)IMX28_DMA,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2013-07-09 14:44:49 +00:00
|
|
|
static __maybe_unused struct of_device_id apbh_dt_ids[] = {
|
|
|
|
{
|
|
|
|
.compatible = "fsl,imx23-dma-apbh",
|
|
|
|
.data = (unsigned long)IMX23_DMA,
|
|
|
|
}, {
|
|
|
|
.compatible = "fsl,imx28-dma-apbh",
|
|
|
|
.data = (unsigned long)IMX28_DMA,
|
|
|
|
}, {
|
|
|
|
/* sentinel */
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2013-07-09 11:56:50 +00:00
|
|
|
static struct driver_d apbh_dma_driver = {
|
|
|
|
.name = "dma-apbh",
|
|
|
|
.id_table = apbh_ids,
|
2013-07-09 14:44:49 +00:00
|
|
|
.of_compatible = DRV_OF_COMPAT(apbh_dt_ids),
|
2013-07-09 11:56:50 +00:00
|
|
|
.probe = apbh_dma_probe,
|
|
|
|
};
|
|
|
|
coredevice_platform_driver(apbh_dma_driver);
|