2009-06-23 13:46:15 +00:00
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/*
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2012-01-02 11:44:00 +00:00
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* (c) 2009...2011 Juergen Beisert <j.beisert@pengutronix.de>
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2009-06-23 13:46:15 +00:00
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*
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* Based on code from:
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* (c) 2004 Sascha Hauer <sascha@saschahauer.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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*/
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#include <common.h>
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#include <driver.h>
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#include <init.h>
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#include <malloc.h>
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2011-09-22 17:02:57 +00:00
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#include <io.h>
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2012-01-02 11:43:51 +00:00
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#include <mach/s3c-generic.h>
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#include <mach/s3c-iomap.h>
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2009-06-23 13:46:15 +00:00
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/* Note: Offsets are for little endian access */
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#define ULCON 0x00 /* line control */
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#define UCON 0x04 /* UART control */
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2012-07-20 19:29:40 +00:00
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# define UCON_SET_CLK_SRC(x) (((x) & 0x03) << 10)
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# define UCON_GET_CLK_SRC(x) (((x) >> 10) & 0x03)
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2009-06-23 13:46:15 +00:00
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#define UFCON 0x08 /* FIFO control */
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#define UMCON 0x0c /* modem control */
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#define UTRSTAT 0x10 /* Rx/Tx status */
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#define UERSTAT 0x14 /* error status */
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#define UFSTAT 0x18 /* FIFO status */
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#define UMSTAT 0x1c /* modem status */
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#define UTXH 0x20 /* transmitt */
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#define URXH 0x24 /* receive */
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#define UBRDIV 0x28 /* baudrate generator */
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2012-07-20 19:29:41 +00:00
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#define UBRDIVSLOT 0x2c /* baudrate slot generator */
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#define UINTM 0x38 /* interrupt mask register */
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2012-05-14 09:38:05 +00:00
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2012-02-25 13:31:33 +00:00
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struct s3c_uart {
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void __iomem *regs;
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struct console_device cdev;
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};
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#define to_s3c_uart(c) container_of(c, struct s3c_uart, cdev)
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2012-07-24 09:24:51 +00:00
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/* each architecture has a preferred reference clock for its UARTs */
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static unsigned s3c_select_arch_input_clock(void)
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{
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/* S3C24xx: 0=2=PCLK, 1=UEXTCLK, 3=FCLK/n */
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if (IS_ENABLED(CONFIG_ARCH_S3C24xx))
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return 0; /* use the internal PCLK */
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2012-07-30 12:32:48 +00:00
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/* S3C64xx: 0=2=PCLK, 1=UCLK0, 3=UCLK1 */
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if (IS_ENABLED(CONFIG_ARCH_S3C64xx))
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return 3; /* use the internal UCLK1 */
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2012-07-24 09:24:51 +00:00
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/* S5PCxx: 0=PCLK, 1=SCLK_UART */
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if (IS_ENABLED(CONFIG_ARCH_S5PCxx))
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return 0; /* use the internal PCLK */
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}
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2012-01-02 11:44:00 +00:00
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static unsigned s3c_get_arch_uart_input_clock(void __iomem *base)
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{
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unsigned reg = readw(base + UCON);
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2012-07-20 19:29:40 +00:00
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return s3c_get_uart_clk(UCON_GET_CLK_SRC(reg));
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2012-01-02 11:44:00 +00:00
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}
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2012-05-14 09:38:05 +00:00
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/*
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* This table takes the fractional value of the baud divisor and gives
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* the recommended setting for the UDIVSLOT register. Refer the datasheet
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* for further details
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*/
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static const uint16_t udivslot_table[] __maybe_unused = {
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0x0000, 0x0080, 0x0808, 0x0888, 0x2222, 0x4924, 0x4A52, 0x54AA,
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0x5555, 0xD555, 0xD5D5, 0xDDD5, 0xDDDD, 0xDFDD, 0xDFDF, 0xFFDF,
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};
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2012-01-02 11:44:00 +00:00
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static int s3c_serial_setbaudrate(struct console_device *cdev, int baudrate)
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2009-06-23 13:46:15 +00:00
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{
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2012-02-25 13:31:33 +00:00
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struct s3c_uart *priv = to_s3c_uart(cdev);
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void __iomem *base = priv->regs;
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2009-06-23 13:46:15 +00:00
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unsigned val;
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2012-07-24 09:24:49 +00:00
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if (IS_ENABLED(CONFIG_DRIVER_SERIAL_S3C_IMPROVED)) {
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val = s3c_get_arch_uart_input_clock(base) / baudrate;
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writew(udivslot_table[val & 15], base + UBRDIVSLOT);
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}
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2012-01-02 11:44:00 +00:00
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val = s3c_get_arch_uart_input_clock(base) / (16 * baudrate) - 1;
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2011-07-28 13:05:34 +00:00
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writew(val, base + UBRDIV);
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2009-06-23 13:46:15 +00:00
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return 0;
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}
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2012-01-02 11:44:00 +00:00
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static int s3c_serial_init_port(struct console_device *cdev)
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2009-06-23 13:46:15 +00:00
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{
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2012-02-25 13:31:33 +00:00
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struct s3c_uart *priv = to_s3c_uart(cdev);
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void __iomem *base = priv->regs;
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2009-06-23 13:46:15 +00:00
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/* FIFO enable, Tx/Rx FIFO clear */
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2011-07-28 13:05:34 +00:00
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writeb(0x07, base + UFCON);
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writeb(0x00, base + UMCON);
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2009-06-23 13:46:15 +00:00
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/* Normal,No parity,1 stop,8 bit */
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2011-07-28 13:05:34 +00:00
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writeb(0x03, base + ULCON);
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2012-05-14 09:38:05 +00:00
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2012-07-24 09:24:50 +00:00
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/*
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* S3C2440 SoC:
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* - no clock divider
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* all SoCs:
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* - enable receive and transmit mode
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*/
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2012-07-24 09:24:51 +00:00
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writew(0x0005 | UCON_SET_CLK_SRC(s3c_select_arch_input_clock()),
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2012-07-20 19:29:40 +00:00
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base + UCON);
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2012-05-14 09:38:05 +00:00
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2012-07-24 09:24:49 +00:00
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if (IS_ENABLED(CONFIG_DRIVER_SERIAL_S3C_IMPROVED))
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/* 'interrupt or polling mode' for both directions */
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writeb(0xf, base + UINTM);
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2009-06-23 13:46:15 +00:00
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2012-07-20 19:29:39 +00:00
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if (IS_ENABLED(CONFIG_DRIVER_SERIAL_S3C_AUTOSYNC))
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writeb(0x10, base + UMCON); /* enable auto flow control */
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else
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writeb(0x01, base + UMCON); /* RTS up */
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2009-06-23 13:46:15 +00:00
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return 0;
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}
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2012-01-02 11:44:00 +00:00
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static void s3c_serial_putc(struct console_device *cdev, char c)
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2009-06-23 13:46:15 +00:00
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{
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2012-02-25 13:31:33 +00:00
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struct s3c_uart *priv = to_s3c_uart(cdev);
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void __iomem *base = priv->regs;
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2009-06-23 13:46:15 +00:00
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/* Wait for Tx FIFO not full */
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2011-07-28 13:05:34 +00:00
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while (!(readb(base + UTRSTAT) & 0x2))
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2009-06-23 13:46:15 +00:00
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;
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2011-07-28 13:05:34 +00:00
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writeb(c, base + UTXH);
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2009-06-23 13:46:15 +00:00
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}
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2012-01-02 11:44:00 +00:00
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static int s3c_serial_tstc(struct console_device *cdev)
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2009-06-23 13:46:15 +00:00
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{
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2012-02-25 13:31:33 +00:00
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struct s3c_uart *priv = to_s3c_uart(cdev);
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void __iomem *base = priv->regs;
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2009-06-23 13:46:15 +00:00
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/* If receive fifo is empty, return false */
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2011-07-28 13:05:34 +00:00
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if (readb(base + UTRSTAT) & 0x1)
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2009-06-23 13:46:15 +00:00
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return 1;
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return 0;
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}
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2012-01-02 11:44:00 +00:00
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static int s3c_serial_getc(struct console_device *cdev)
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2009-06-23 13:46:15 +00:00
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{
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2012-02-25 13:31:33 +00:00
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struct s3c_uart *priv = to_s3c_uart(cdev);
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void __iomem *base = priv->regs;
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2009-06-23 13:46:15 +00:00
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/* wait for a character */
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2011-07-28 13:05:34 +00:00
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while (!(readb(base + UTRSTAT) & 0x1))
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2009-06-23 13:46:15 +00:00
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;
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2011-07-28 13:05:34 +00:00
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return readb(base + URXH);
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2009-06-23 13:46:15 +00:00
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}
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2012-01-02 11:44:00 +00:00
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static void s3c_serial_flush(struct console_device *cdev)
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2009-06-23 13:46:15 +00:00
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{
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2012-02-25 13:31:33 +00:00
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struct s3c_uart *priv = to_s3c_uart(cdev);
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void __iomem *base = priv->regs;
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2009-06-23 13:46:15 +00:00
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2011-07-28 13:05:34 +00:00
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while (!(readb(base + UTRSTAT) & 0x4))
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2009-06-23 13:46:15 +00:00
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;
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}
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2012-01-02 11:44:00 +00:00
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static int s3c_serial_probe(struct device_d *dev)
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2009-06-23 13:46:15 +00:00
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{
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2012-02-25 13:31:33 +00:00
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struct s3c_uart *priv;
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2009-06-23 13:46:15 +00:00
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struct console_device *cdev;
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2012-03-12 13:57:59 +00:00
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priv = xzalloc(sizeof(struct s3c_uart));
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2012-02-25 13:31:33 +00:00
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cdev = &priv->cdev;
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priv->regs = dev_request_mem_region(dev, 0);
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dev->priv = priv;
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2009-06-23 13:46:15 +00:00
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cdev->dev = dev;
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cdev->f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR;
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2012-01-02 11:44:00 +00:00
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cdev->tstc = s3c_serial_tstc;
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cdev->putc = s3c_serial_putc;
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cdev->getc = s3c_serial_getc;
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cdev->flush = s3c_serial_flush;
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cdev->setbrg = s3c_serial_setbaudrate;
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2009-06-23 13:46:15 +00:00
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2012-01-02 11:44:00 +00:00
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s3c_serial_init_port(cdev);
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2009-06-23 13:46:15 +00:00
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/* Enable UART */
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console_register(cdev);
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return 0;
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}
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2012-01-02 11:44:00 +00:00
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static void s3c_serial_remove(struct device_d *dev)
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2009-06-23 13:46:15 +00:00
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{
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2012-02-25 13:31:33 +00:00
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struct s3c_uart *priv= dev->priv;
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2009-06-23 13:46:15 +00:00
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2012-02-25 13:31:33 +00:00
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s3c_serial_flush(&priv->cdev);
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console_unregister(&priv->cdev);
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free(priv);
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2009-06-23 13:46:15 +00:00
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}
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2012-01-02 11:44:00 +00:00
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static struct driver_d s3c_serial_driver = {
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.name = "s3c_serial",
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.probe = s3c_serial_probe,
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.remove = s3c_serial_remove,
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2009-06-23 13:46:15 +00:00
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};
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2012-01-02 11:44:00 +00:00
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static int s3c_serial_init(void)
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2009-06-23 13:46:15 +00:00
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{
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2012-09-19 19:22:17 +00:00
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platform_driver_register(&s3c_serial_driver);
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2009-06-23 13:46:15 +00:00
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return 0;
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}
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2012-01-02 11:44:00 +00:00
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console_initcall(s3c_serial_init);
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