2010-10-19 07:48:52 +00:00
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/*
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* Copyright (C) 2010 Marek Belisko <marek.belisko@open-nandra.com>
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*
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* Based on a9m2440.c board init by Juergen Beisert, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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/**
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* @file
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* @brief mini2440 Specific Board Initialization routines
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*
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*/
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#include <common.h>
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#include <driver.h>
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#include <init.h>
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2010-11-12 12:50:55 +00:00
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#include <generated/mach-types.h>
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2010-10-19 07:48:52 +00:00
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#include <partition.h>
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2011-02-16 18:13:32 +00:00
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#include <dm9000.h>
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2010-10-19 07:48:52 +00:00
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#include <nand.h>
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2011-02-16 18:13:40 +00:00
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#include <mci.h>
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2011-05-18 09:40:40 +00:00
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#include <fb.h>
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2011-02-16 18:13:32 +00:00
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#include <asm/armlinux.h>
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2011-09-22 17:02:57 +00:00
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#include <io.h>
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2011-02-16 18:13:39 +00:00
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#include <mach/gpio.h>
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2012-01-02 11:43:51 +00:00
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#include <mach/s3c-iomap.h>
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2012-01-02 11:43:52 +00:00
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#include <mach/s3c24xx-nand.h>
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2012-01-02 11:43:51 +00:00
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#include <mach/s3c-generic.h>
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2011-02-16 18:13:40 +00:00
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#include <mach/mci.h>
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2011-05-18 09:40:40 +00:00
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#include <mach/fb.h>
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2010-10-19 07:48:52 +00:00
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static struct s3c24x0_nand_platform_data nand_info = {
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2011-11-26 18:30:29 +00:00
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.nand_timing = CALC_NFCONF_TIMING(MINI2440_TACLS, MINI2440_TWRPH0,
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MINI2440_TWRPH1),
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2011-02-16 18:13:42 +00:00
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.flash_bbt = 1, /* same as the kernel */
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2010-10-19 07:48:52 +00:00
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};
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/*
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* dm9000 network controller onboard
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2011-02-16 18:13:34 +00:00
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* Connected to CS line 4 and interrupt line EINT7,
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* data width is 16 bit
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* Area 1: Offset 0x300...0x303
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* Area 2: Offset 0x304...0x307
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2010-10-19 07:48:52 +00:00
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*/
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static struct dm9000_platform_data dm9000_data = {
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.srom = 1,
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};
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2011-02-16 18:13:40 +00:00
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static struct s3c_mci_platform_data mci_data = {
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.caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz,
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.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
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.gpio_detect = 232, /* GPG8_GPIO */
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.detect_invert = 0,
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};
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2011-05-18 09:40:40 +00:00
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static struct fb_videomode s3c24x0_fb_modes[] = {
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#ifdef CONFIG_MINI2440_VIDEO_N35
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{
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.name = "N35",
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.refresh = 60,
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.xres = 240,
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.left_margin = 21,
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.right_margin = 38,
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.hsync_len = 6,
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.yres = 320,
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.upper_margin = 4,
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.lower_margin = 4,
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.vsync_len = 2,
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.pixclock = 115913,
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.sync = FB_SYNC_USE_PWREN,
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.vmode = FB_VMODE_NONINTERLACED,
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.flag = 0,
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},
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#endif
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#ifdef CONFIG_MINI2440_VIDEO_A70
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{
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.name = "A70",
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.refresh = 50,
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.xres = 800,
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.left_margin = 40,
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.right_margin = 40,
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.hsync_len = 48,
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.yres = 480,
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.upper_margin = 29,
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.lower_margin = 3,
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.vsync_len = 3,
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.pixclock = 41848,
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.sync = FB_SYNC_USE_PWREN | FB_SYNC_DE_HIGH_ACT,
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.vmode = FB_VMODE_NONINTERLACED,
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.flag = 0,
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},
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#endif
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#ifdef CONFIG_MINI2440_VIDEO_SVGA
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{
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.name = "SVGA",
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.refresh = 24,
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.xres = 1024,
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.left_margin = 1,
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.right_margin = 2,
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.hsync_len = 2,
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.yres = 768,
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.upper_margin = 200,
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.lower_margin = 16,
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.vsync_len = 16,
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.pixclock = 40492,
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.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_DE_HIGH_ACT
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/* | FB_SYNC_SWAP_HW */ /* FIXME maybe */ ,
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.vmode = FB_VMODE_NONINTERLACED,
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.flag = 0,
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},
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#endif
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};
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static struct s3c_fb_platform_data s3c24x0_fb_data = {
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.mode_list = s3c24x0_fb_modes,
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.mode_cnt = sizeof(s3c24x0_fb_modes) / sizeof(struct fb_videomode),
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.bits_per_pixel = 16,
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.passive_display = 0,
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};
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2011-02-16 18:13:39 +00:00
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static const unsigned pin_usage[] = {
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/* address bus, used by NOR, SDRAM */
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GPA1_ADDR16,
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GPA2_ADDR17,
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GPA3_ADDR18,
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GPA4_ADDR19,
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GPA5_ADDR20,
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GPA6_ADDR21,
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GPA7_ADDR22,
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GPA8_ADDR23_GPIO | GPIO_IN,
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GPA9_ADDR24, /* BA0 */
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GPA10_ADDR25, /* BA1 */
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GPA11_ADDR26_GPIO | GPIO_IN, /* not connected */
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/* DM9000 requirements */
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GPA15_NGCS4,
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GPF7_EINT7,
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/* de-activate the speaker */
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GPB0_GPIO | GPIO_OUT | GPIO_VAL(0),
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/* SD socket */
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GPE5_SDCLK,
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GPE6_SDCMD,
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GPE7_SDDAT0,
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GPE8_SDDAT1,
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GPE9_SDDAT2,
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GPE10_SDDAT3,
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GPG8_GPIO | GPIO_IN, /* change detection */
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GPH8_GPIO | GPIO_IN, /* write protection sense */
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/* NAND requirements */
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GPA17_CLE,
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GPA18_ALE,
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GPA19_NFWE,
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GPA20_NFRE,
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GPA21_NRSTOUT,
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GPA22_NFCE,
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/* Video out */
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GPC0_LEND,
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GPC1_VCLK,
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GPC2_VLINE,
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GPC3_VFRAME,
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GPC4_VM,
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GPC5_LPCOE,
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GPC6_LPCREV,
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GPC7_LPCREVB,
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GPG4_LCD_PWREN,
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GPC8_VD0,
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GPC9_VD1,
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GPC10_VD2,
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GPC11_VD3,
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GPC12_VD4,
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GPC13_VD5,
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GPC14_VD6,
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GPC15_VD7,
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GPD0_VD8,
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GPD1_VD9,
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GPD2_VD10,
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GPD3_VD11,
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GPD4_VD12,
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GPD5_VD13,
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GPD6_VD14,
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GPD7_VD15,
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GPD8_VD16,
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GPD9_VD17,
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GPD10_VD18,
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GPD11_VD19,
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GPD12_VD20,
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GPD13_VD21,
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GPD14_VD22,
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GPD15_VD23,
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/* K6 or CON12, pin 6, external pull up */
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GPG11_EINT19 | GPIO_IN,
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/* K5 or CON12, pin 5*/
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GPG7_EINT15 | GPIO_IN,
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/* K4 or CON12, pin 4 */
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GPG6_EINT14 | GPIO_IN,
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/* K3 or CON12, pin 3 */
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GPG5_EINT13 | GPIO_IN,
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/* K2 or CON12, pin 2 */
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GPG3_EINT11 | GPIO_IN,
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/* K1 or CON12, pin 1, external pull up */
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GPG0_EINT8 | GPIO_IN,
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/* LED 1 1=off */
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GPB5_GPIO | GPIO_OUT | GPIO_VAL(1),
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/* LED 2 1=off */
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GPB6_GPIO | GPIO_OUT | GPIO_VAL(1),
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/* LED 3 1=off */
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GPB7_GPIO | GPIO_OUT | GPIO_VAL(1),
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/* LED 4 1=off */
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GPB8_GPIO | GPIO_OUT | GPIO_VAL(1),
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/* camera interface (ignore it) */
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GPJ0_GPIO | GPIO_IN,
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GPJ1_GPIO | GPIO_IN,
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GPJ2_GPIO | GPIO_IN,
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GPJ3_GPIO | GPIO_IN,
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GPJ4_GPIO | GPIO_IN,
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GPJ5_GPIO | GPIO_IN,
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GPJ6_GPIO | GPIO_IN,
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GPJ7_GPIO | GPIO_IN,
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GPJ8_GPIO | GPIO_IN,
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GPJ9_GPIO | GPIO_IN,
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GPJ10_GPIO | GPIO_IN,
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GPJ11_GPIO | GPIO_IN,
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GPJ12_GPIO | GPIO_IN,
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/* I2C bus */
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GPE14_IICSCL, /* external pull up */
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GPE15_IICSDA, /* external pull up */
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GPA12_NGCS1, /* CON5, pin 7 */
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GPA13_NGCS2, /* CON5, pin 8 */
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GPA14_NGCS3, /* CON5, pin 9 */
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GPA16_NGCS5, /* CON5, pin 10 */
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/* UART2 (spare) */
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GPH4_TXD1,
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GPH5_RXD1,
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/* UART3 (spare) */
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GPH6_TXD2,
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GPH7_RXD2,
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};
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2011-07-29 09:43:48 +00:00
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static int mini2440_mem_init(void)
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{
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arm_add_mem_device("ram0", CS6_BASE, s3c24x0_get_memory_size());
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return 0;
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}
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mem_initcall(mini2440_mem_init);
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2010-10-19 07:48:52 +00:00
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static int mini2440_devices_init(void)
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{
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uint32_t reg;
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2011-02-16 18:13:39 +00:00
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int i;
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2011-02-16 18:13:38 +00:00
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2011-02-16 18:13:39 +00:00
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/* ----------- configure the access to the outer space ---------- */
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for (i = 0; i < ARRAY_SIZE(pin_usage); i++)
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s3c_gpio_mode(pin_usage[i]);
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2010-10-19 07:48:52 +00:00
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reg = readl(BWSCON);
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/* CS#4 to access the network controller */
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reg &= ~0x000f0000;
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reg |= 0x000d0000; /* 16 bit */
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writel(0x1f4c, BANKCON4);
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writel(reg, BWSCON);
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/* release the reset signal to external devices */
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reg = readl(MISCCR);
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reg |= 0x10000;
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writel(reg, MISCCR);
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2011-07-29 05:31:19 +00:00
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add_generic_device("s3c24x0_nand", -1, NULL, S3C24X0_NAND_BASE, 0,
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IORESOURCE_MEM, &nand_info);
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2011-07-19 07:58:32 +00:00
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2011-07-23 09:42:28 +00:00
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add_dm9000_device(0, CS4_BASE + 0x300, CS4_BASE + 0x304,
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IORESOURCE_MEM_16BIT, &dm9000_data);
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2010-10-19 07:48:52 +00:00
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#ifdef CONFIG_NAND
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/* ----------- add some vital partitions -------- */
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devfs_del_partition("self_raw");
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devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
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2011-02-16 18:13:41 +00:00
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dev_add_bb_dev("self_raw", "self0");
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2010-10-19 07:48:52 +00:00
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devfs_del_partition("env_raw");
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devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
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2011-02-16 18:13:41 +00:00
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dev_add_bb_dev("env_raw", "env0");
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2010-10-19 07:48:52 +00:00
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#endif
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2011-07-29 05:31:19 +00:00
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add_generic_device("s3c_mci", 0, NULL, S3C2410_SDI_BASE, 0,
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IORESOURCE_MEM, &mci_data);
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add_generic_device("s3c_fb", 0, NULL, S3C2410_LCD_BASE, 0,
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IORESOURCE_MEM, &s3c24x0_fb_data);
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2011-11-16 09:10:24 +00:00
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add_generic_device("ohci", 0, NULL, S3C2410_USB_HOST_BASE, 0x100,
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IORESOURCE_MEM, NULL);
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2011-07-29 09:43:48 +00:00
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armlinux_set_bootparams((void*)CS6_BASE + 0x100);
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2010-10-19 07:48:52 +00:00
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armlinux_set_architecture(MACH_TYPE_MINI2440);
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return 0;
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}
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device_initcall(mini2440_devices_init);
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#ifdef CONFIG_S3C24XX_NAND_BOOT
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void __bare_init nand_boot(void)
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{
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2011-03-12 19:14:55 +00:00
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s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0);
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2010-10-19 07:48:52 +00:00
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}
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#endif
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static int mini2440_console_init(void)
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|
{
|
2011-02-16 18:13:37 +00:00
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/*
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* configure the UART1 right now, as barebox will
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|
* start to send data immediately
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|
*/
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s3c_gpio_mode(GPH0_NCTS0);
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|
|
s3c_gpio_mode(GPH1_NRTS0);
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s3c_gpio_mode(GPH2_TXD0);
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|
s3c_gpio_mode(GPH3_RXD0);
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|
|
2011-07-29 05:31:19 +00:00
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|
add_generic_device("s3c24x0_serial", -1, NULL, UART1_BASE, UART1_SIZE,
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|
|
IORESOURCE_MEM, NULL);
|
2010-10-19 07:48:52 +00:00
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|
return 0;
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|
}
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|
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console_initcall(mini2440_console_init);
|
2011-02-16 18:13:34 +00:00
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/** @page mini2440 FriendlyARM's mini2440
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This system is based on a Samsung S3C2440 CPU. The card is shipped with:
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- S3C2440\@400 MHz or 533 MHz (ARM920T/ARMv4T)
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- 12 MHz crystal reference
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|
- 32.768 kHz crystal reference
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- SDRAM 64 MiB (one bank only)
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- HY57V561620 (two devices for 64 MiB to form a 32 bit bus)
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- 4M x 16bit x 4 Banks Mobile SDRAM
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- 8192 refresh cycles / 64 ms
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- CL2\@100 MHz
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- 133 MHz max
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- collumn address size is 9 bits
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- row address size is 13 bits
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- MT48LC16M16 (two devices for 64 MiB to form a 32 bit bus)
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- 4M x 16bit x 4 Banks Mobile SDRAM
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- commercial & industrial type
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- 8192 refresh cycles / 64 ms
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- CL2\@100 MHz
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- 133 MHz max
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- collumn address size is 9 bits
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- row address size is 13 bits
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- NAND Flash 128MiB...1GiB
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- K9Fxx08
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- NOR Flash (up to 22 address lines available)
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- AM29LV160DB, 2 MiB
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- SST39VF1601, 2 MiB
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- 16 bit data bus
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- SD card interface, 3.3V (fixed voltage)
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- Host and device USB interface, USB1.1 compliant
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- UDA1341TS Audio
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- DM9000 Ethernet interface
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- uses CS#4
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- uses EINT7
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- 16 bit data bus
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- I2C interface, 100 KHz and 400 KHz
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- EEPROM
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- ST M24C08
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- address 0x50
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- Speaker on GPB0 ("low" = inactive)
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- LCD interface
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- Touch Screen interface
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- Camera interface
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- I2S interface
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- AC97 Audio-CODEC interface
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- three serial RS232 interfaces (one with level converter)
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- SPI interface
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- JTAG interface
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|
How to get the binary image:
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|
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Using the default configuration:
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@code
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make ARCH=arm mini2440_defconfig
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@endcode
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Build the binary image:
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@code
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make ARCH=arm CROSS_COMPILE=armv4compiler
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@endcode
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@note replace the armv4compiler with your ARM v4 cross compiler.
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How to bring in \a barebox ?
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|
First run it as a second stage bootloader. There are two known working ways to
|
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|
do so:
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|
|
One way is to use the "device firmware update" feature of the 'supervivi'.
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|
|
- connect a terminal application to the mini2440's serial connector
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|
|
- switch S2 to 'boot from NOR' to boot into 'supervivi'
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|
|
- connect your host to the usb device connector on the mini2440
|
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|
|
- switch on your mini2440
|
|
|
|
- in 'supervivi' type q (command line) then:
|
|
|
|
@code
|
|
|
|
load ram 0x31000000 \<barebox-size\> u
|
|
|
|
@endcode
|
|
|
|
- use a tool for DFU update (for example from openkomo) to transfer the 'barebox.bin' binary
|
|
|
|
- then in 'supervivi' just run
|
|
|
|
@code
|
|
|
|
go 0x31000000
|
|
|
|
@endcode
|
|
|
|
|
|
|
|
A second way is to use any kind of JTAG adapter. For this case I'm using the
|
|
|
|
'JTAKkey tiny' from Amontec and OpenOCD. First you need an adapter for this
|
|
|
|
kind of Dongle as it uses a 20 pin connector with 2.54 mm grid, and the
|
|
|
|
mini2440 uses a 10 pin connector with 2 mm grid.
|
|
|
|
|
|
|
|
@code
|
|
|
|
Amontec JTAGkey tiny mini2440
|
|
|
|
-------------------------------------------------------
|
|
|
|
VREF 1 2 n.c. VREF 1 2 VREF
|
|
|
|
TRST_N 3 4 GND TRST_N 3 4 SRST_N
|
|
|
|
TDI 5 6 GND TDI 5 6 TDO
|
|
|
|
TMS 7 8 GND TMS 7 8 GND
|
|
|
|
TCK 9 10 GND TCK 9 10 GND
|
|
|
|
n.c. 11 12 GND
|
|
|
|
TDO 13 14 GND
|
|
|
|
SRST_N 15 16 GND
|
|
|
|
n.c. 17 18 GND
|
|
|
|
n.c. 19 20 GND
|
|
|
|
@endcode
|
|
|
|
|
|
|
|
Create a simple board description file. I did it this way:
|
|
|
|
|
|
|
|
@code
|
|
|
|
source [find interface/jtagkey-tiny.cfg]
|
|
|
|
source [find target/samsung_s3c2440.cfg]
|
|
|
|
|
|
|
|
adapter_khz 12000
|
|
|
|
@endcode
|
|
|
|
|
|
|
|
And then the following steps:
|
|
|
|
- connect a terminal application to the mini2440's serial connector
|
|
|
|
- connect the mini2440 to a working network
|
|
|
|
- switch S2 to boot from NOR to boot into 'supervivi'
|
|
|
|
- switch on your mini2440
|
|
|
|
- run the OpenOCD daemon configured with the file shown above
|
|
|
|
- connect to the OpenOCD daemon via 'telnet'.
|
|
|
|
- run the following commands to download @a barebox into your target
|
|
|
|
@code
|
|
|
|
> halt
|
|
|
|
> load_image \<path to the 'barebox.bin'\> 0x31000000 bin
|
|
|
|
> resume 0x31000000
|
|
|
|
@endcode
|
|
|
|
|
|
|
|
Now @a barebox is starting from an already initialized CPU and SDRAM (done by
|
|
|
|
'supervivi').
|
|
|
|
|
|
|
|
Change to your terminal console and configure the network first. Adapt the
|
|
|
|
following settings to your network:
|
|
|
|
@code
|
|
|
|
eth0.ipaddr=192.168.1.240
|
|
|
|
eth0.netmask=255.255.255.0
|
|
|
|
eth0.gateway=192.168.23.2
|
|
|
|
eth0.serverip=192.168.1.7
|
|
|
|
eth0.ethaddr=00:04:f3:00:06:35
|
|
|
|
@endcode
|
|
|
|
|
|
|
|
A 'ping' to your TFTP server should bring a "...is alive" message now.
|
|
|
|
|
|
|
|
We are ready now to program @a barebox into the NAND flash:
|
|
|
|
|
|
|
|
@code
|
|
|
|
erase /dev/nand0.barebox.bb
|
|
|
|
tftp barebox.bin /dev/nand0.barebox.bb
|
|
|
|
@endcode
|
|
|
|
|
|
|
|
*/
|