2009-06-23 14:31:25 +00:00
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/*
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*
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*/
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#include <config.h>
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2012-10-14 20:22:39 +00:00
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#include <sizes.h>
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2012-01-02 11:43:51 +00:00
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#include <mach/s3c-iomap.h>
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2012-09-24 08:18:34 +00:00
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#include <asm/barebox-arm-head.h>
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2009-06-23 14:31:25 +00:00
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2013-02-05 13:45:26 +00:00
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.section ".text_bare_init.barebox_arm_reset_vector","ax"
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2009-06-23 14:31:25 +00:00
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2013-02-05 13:45:26 +00:00
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.globl barebox_arm_reset_vector
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barebox_arm_reset_vector:
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2009-06-23 14:31:25 +00:00
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2013-06-02 17:05:59 +00:00
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bl arm_cpu_lowlevel_init
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2009-06-23 14:31:25 +00:00
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bl s3c24x0_disable_wd
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/* skip everything here if we are already running from SDRAM */
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2012-01-02 11:44:01 +00:00
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cmp pc, #S3C_SDRAM_BASE
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2009-06-23 14:31:25 +00:00
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blo 1f
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2012-01-02 11:44:01 +00:00
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cmp pc, #S3C_SDRAM_END
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2009-06-23 14:31:25 +00:00
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bhs 1f
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2012-10-14 20:22:39 +00:00
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b out
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2009-06-23 14:31:25 +00:00
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/* we are running from NOR or NAND/SRAM memory. Do further initialisation */
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1:
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bl s3c24x0_pll_init
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bl s3c24x0_sdram_init
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2012-05-18 09:43:25 +00:00
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#ifdef CONFIG_S3C_NAND_BOOT
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2009-06-23 14:31:25 +00:00
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/* up to here we are running from the internal SRAM area */
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2012-09-24 08:18:34 +00:00
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bl s3c24x0_nand_boot
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2009-06-23 14:31:25 +00:00
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#endif
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2012-10-14 20:22:39 +00:00
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out:
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mov r0, #S3C_SDRAM_BASE
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mov r1, #SZ_32M
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mov r2, #0
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b barebox_arm_entry
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