2012-09-22 13:14:15 +00:00
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/*
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* Copyright (C) 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <driver.h>
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#include <linux/clk.h>
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#include <io.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <mach/imx35-regs.h>
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#include "clk.h"
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#define CCM_CCMR 0x00
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#define CCM_PDR0 0x04
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#define CCM_PDR1 0x08
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#define CCM_PDR2 0x0C
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#define CCM_PDR3 0x10
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#define CCM_PDR4 0x14
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#define CCM_RCSR 0x18
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#define CCM_MPCTL 0x1C
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#define CCM_PPCTL 0x20
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#define CCM_ACMR 0x24
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#define CCM_COSR 0x28
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#define CCM_CGR0 0x2C
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#define CCM_CGR1 0x30
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#define CCM_CGR2 0x34
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#define CCM_CGR3 0x38
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struct arm_ahb_div {
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unsigned char arm, ahb, sel;
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};
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static struct arm_ahb_div clk_consumer[] = {
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{ .arm = 1, .ahb = 4, .sel = 0},
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{ .arm = 1, .ahb = 3, .sel = 1},
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{ .arm = 2, .ahb = 2, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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{ .arm = 4, .ahb = 1, .sel = 0},
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{ .arm = 1, .ahb = 5, .sel = 0},
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{ .arm = 1, .ahb = 8, .sel = 0},
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{ .arm = 1, .ahb = 6, .sel = 1},
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{ .arm = 2, .ahb = 4, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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{ .arm = 4, .ahb = 2, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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};
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static char hsp_div_532[] = { 4, 8, 3, 0 };
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static char hsp_div_400[] = { 3, 6, 3, 0 };
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enum mx35_clks {
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ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg,
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arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, esdhc_sel,
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esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel, spdif_div_pre,
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spdif_div_post, ssi_sel, ssi1_div_pre, ssi1_div_post, ssi2_div_pre,
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ssi2_div_post, usb_sel, usb_div, nfc_div, asrc_gate, pata_gate,
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audmux_gate, can1_gate, can2_gate, cspi1_gate, cspi2_gate, ect_gate,
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edio_gate, emi_gate, epit1_gate, epit2_gate, esai_gate, esdhc1_gate,
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esdhc2_gate, esdhc3_gate, fec_gate, gpio1_gate, gpio2_gate, gpio3_gate,
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gpt_gate, i2c1_gate, i2c2_gate, i2c3_gate, iomuxc_gate, ipu_gate,
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kpp_gate, mlb_gate, mshc_gate, owire_gate, pwm_gate, rngc_gate,
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rtc_gate, rtic_gate, scc_gate, sdma_gate, spba_gate, spdif_gate,
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ssi1_gate, ssi2_gate, uart1_gate, uart2_gate, uart3_gate, usbotg_gate,
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wdog_gate, max_gate, admux_gate, csi_gate, iim_gate, gpu2d_gate,
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clk_max
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};
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static struct clk *clks[clk_max];
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static const char *std_sel[] = {
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"ppll",
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"arm",
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};
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static const char *ipg_per_sel[] = {
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"ahb_per_div",
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"arm_per_div",
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};
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static int imx35_ccm_probe(struct device_d *dev)
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{
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u32 pdr0, consumer_sel, hsp_sel;
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struct arm_ahb_div *aad;
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unsigned char *hsp_div;
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void __iomem *base;
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base = dev_request_mem_region(dev, 0);
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writel(0xffffffff, base + CCM_CGR0);
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writel(0xffffffff, base + CCM_CGR1);
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ARM i.MX35: Let MAX clk be in run-mode-on
The reset value for the MAX clk gate is 0b10, that is it is turned
on in CPU run mode and off in stop mode. Configure it that way during
startup.
The 0b11 value previously in this field causes some nasty behaviour in
the Linux kernel:
- The i.MX35 has two bits per clock gate which are decoded as follows:
0b00 -> clock off
0b01 -> clock is on in run mode, off in wait/doze
0b10 -> clock is on in run/wait mode, off in doze
0b11 -> clock is always on
The MAX clock is needed by the SoC, yet unused in the Kernel, so the
common clock framework will disable it during late init time. It will
only disable clocks though which it detects as being on. This detection
is made depending on the lower bit of the gate. So with the value of
0b11 the clock framework will detect the clock as turned on, yet unused,
hence it will turn it off and the system locks up.
With the value of 0b10 instead, the clock framework will detect the
clock as being disabled and will not try to turn it off, so the
system works.
The real bug is in the Linux clock framework. However, the value 0f 0b10
seems to be a sane default value, so restore it. This lets Linux work
again and gives time to fix the bug in Linux.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2013-02-26 09:34:40 +00:00
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writel(0xfbffffff, base + CCM_CGR2);
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2012-09-22 13:14:15 +00:00
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writel(0xffffffff, base + CCM_CGR3);
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pdr0 = __raw_readl(base + CCM_PDR0);
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consumer_sel = (pdr0 >> 16) & 0xf;
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aad = &clk_consumer[consumer_sel];
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if (!aad->arm) {
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pr_err("i.MX35 clk: illegal consumer mux selection 0x%x\n", consumer_sel);
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/*
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* We are basically stuck. Continue with a default entry and hope we
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* get far enough to actually show the above message
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*/
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aad = &clk_consumer[0];
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}
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clks[ckih] = clk_fixed("ckih", 24000000);
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clks[mpll] = imx_clk_pllv1("mpll", "ckih", base + CCM_MPCTL);
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clks[ppll] = imx_clk_pllv1("ppll", "ckih", base + CCM_PPCTL);
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clks[mpll_075] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4);
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if (aad->sel)
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clks[arm] = imx_clk_fixed_factor("arm", "mpll_075", 1, aad->arm);
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else
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clks[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm);
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if (clk_get_rate(clks[arm]) > 400000000)
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hsp_div = hsp_div_532;
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else
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hsp_div = hsp_div_400;
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hsp_sel = (pdr0 >> 20) & 0x3;
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if (!hsp_div[hsp_sel]) {
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pr_err("i.MX35 clk: illegal hsp clk selection 0x%x\n", hsp_sel);
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hsp_sel = 0;
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}
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clks[hsp] = imx_clk_fixed_factor("hsp", "arm", 1, hsp_div[hsp_sel]);
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clks[ahb] = imx_clk_fixed_factor("ahb", "arm", 1, aad->ahb);
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clks[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
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clks[arm_per_div] = imx_clk_divider("arm_per_div", "arm", base + CCM_PDR4, 16, 6);
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clks[ahb_per_div] = imx_clk_divider("ahb_per_div", "ahb", base + CCM_PDR0, 12, 3);
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clks[ipg_per] = imx_clk_mux("ipg_per", base + CCM_PDR0, 26, 1, ipg_per_sel, ARRAY_SIZE(ipg_per_sel));
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clks[uart_sel] = imx_clk_mux("uart_sel", base + CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel));
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clks[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + CCM_PDR4, 10, 6);
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clks[esdhc_sel] = imx_clk_mux("esdhc_sel", base + CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel));
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clks[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc_sel", base + CCM_PDR3, 0, 6);
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clks[esdhc2_div] = imx_clk_divider("esdhc2_div", "esdhc_sel", base + CCM_PDR3, 8, 6);
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clks[esdhc3_div] = imx_clk_divider("esdhc3_div", "esdhc_sel", base + CCM_PDR3, 16, 6);
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clks[usb_sel] = imx_clk_mux("usb_sel", base + CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel));
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clks[usb_div] = imx_clk_divider("usb_div", "usb_sel", base + CCM_PDR4, 22, 6);
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clkdev_add_physbase(clks[uart_div], MX35_UART1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[uart_div], MX35_UART2_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[uart_div], MX35_UART3_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[ipg_per], MX35_I2C1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[ipg_per], MX35_I2C2_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[ipg_per], MX35_I2C3_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[ipg], MX35_CSPI1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[ipg], MX35_CSPI2_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[ipg], MX35_FEC_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[ipg], MX35_GPT1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[esdhc1_div], MX35_ESDHC1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[esdhc2_div], MX35_ESDHC2_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[esdhc3_div], MX35_ESDHC3_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[hsp], MX35_IPU_CTRL_BASE_ADDR, NULL);
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return 0;
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}
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2012-10-05 08:38:58 +00:00
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static __maybe_unused struct of_device_id imx35_ccm_dt_ids[] = {
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{
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.compatible = "fsl,imx35-ccm",
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}, {
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/* sentinel */
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}
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};
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2012-09-22 13:14:15 +00:00
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static struct driver_d imx35_ccm_driver = {
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.probe = imx35_ccm_probe,
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.name = "imx35-ccm",
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2012-10-05 08:38:58 +00:00
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.of_compatible = DRV_OF_COMPAT(imx35_ccm_dt_ids),
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2012-09-22 13:14:15 +00:00
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};
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static int imx35_ccm_init(void)
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{
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2012-10-04 13:24:27 +00:00
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return platform_driver_register(&imx35_ccm_driver);
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2012-09-22 13:14:15 +00:00
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}
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2013-06-12 09:36:40 +00:00
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core_initcall(imx35_ccm_init);
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