2010-10-12 14:39:08 +00:00
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/*
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* (C) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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* (C) 2009 Pengutronix, Juergen Beisert <kernel@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Board support for the Garz+Fricke Cupid board
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*/
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#include <common.h>
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#include <command.h>
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#include <init.h>
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#include <driver.h>
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#include <environment.h>
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#include <fs.h>
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#include <mach/imx-regs.h>
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#include <asm/armlinux.h>
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#include <mach/gpio.h>
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#include <asm/io.h>
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#include <partition.h>
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#include <nand.h>
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#include <generated/mach-types.h>
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#include <mach/imx-nand.h>
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#include <fec.h>
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#include <fb.h>
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#include <asm/mmu.h>
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#include <mach/imx-ipu-fb.h>
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#include <mach/imx-pll.h>
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#include <mach/iomux-mx35.h>
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2011-07-28 07:13:11 +00:00
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#include <mach/devices-imx35.h>
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2010-10-12 14:39:08 +00:00
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static struct fec_platform_data fec_info = {
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.xcv_type = MII100,
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};
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struct imx_nand_platform_data nand_info = {
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.width = 1,
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.hw_ecc = 1,
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.flash_bbt = 1,
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};
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static struct fb_videomode guf_cupid_fb_mode = {
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/* 800x480 @ 70 Hz */
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.name = "CPT CLAA070LC0JCT",
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.refresh = 70,
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.xres = 800,
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.yres = 480,
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.pixclock = 30761,
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.left_margin = 24,
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.right_margin = 47,
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.upper_margin = 5,
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.lower_margin = 3,
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.hsync_len = 24,
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.vsync_len = 3,
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.sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_CLK_INVERT |
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FB_SYNC_OE_ACT_HIGH,
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.vmode = FB_VMODE_NONINTERLACED,
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.flag = 0,
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};
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#define GPIO_LCD_ENABLE (2 * 32 + 24)
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#define GPIO_LCD_BACKLIGHT (0 * 32 + 19)
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static void cupid_fb_enable(int enable)
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{
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if (enable) {
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gpio_direction_output(GPIO_LCD_ENABLE, 1);
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mdelay(100);
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gpio_direction_output(GPIO_LCD_BACKLIGHT, 1);
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} else {
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gpio_direction_output(GPIO_LCD_BACKLIGHT, 0);
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mdelay(100);
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gpio_direction_output(GPIO_LCD_ENABLE, 0);
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}
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}
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static struct imx_ipu_fb_platform_data ipu_fb_data = {
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.mode = &guf_cupid_fb_mode,
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.bpp = 16,
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.enable = cupid_fb_enable,
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};
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#ifdef CONFIG_MMU
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static int cupid_mmu_init(void)
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{
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mmu_init();
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arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED);
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arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED);
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setup_dma_coherent(0x10000000);
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mmu_enable();
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#ifdef CONFIG_CACHE_L2X0
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l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
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#endif
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return 0;
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}
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postcore_initcall(cupid_mmu_init);
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#endif
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static int cupid_devices_init(void)
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{
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uint32_t reg;
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2011-07-19 07:58:32 +00:00
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struct device_d *sdram_dev;
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2010-10-12 14:39:08 +00:00
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gpio_direction_output(GPIO_LCD_ENABLE, 0);
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gpio_direction_output(GPIO_LCD_BACKLIGHT, 0);
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reg = readl(IMX_CCM_BASE + CCM_RCSR);
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/* some fuses provide us vital information about connected hardware */
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if (reg & 0x20000000)
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nand_info.width = 2; /* 16 bit */
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else
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nand_info.width = 1; /* 8 bit */
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2011-07-28 07:13:11 +00:00
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imx35_add_fec(&fec_info);
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imx35_add_nand(&nand_info);
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2010-10-12 14:39:08 +00:00
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devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
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dev_add_bb_dev("self_raw", "self0");
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devfs_add_partition("nand0", 0x40000, 0x80000, PARTITION_FIXED, "env_raw");
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dev_add_bb_dev("env_raw", "env0");
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2011-07-19 07:58:32 +00:00
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sdram_dev = add_mem_device("ram0", IMX_SDRAM_CS0, 128 * 1024 * 1024,
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IORESOURCE_MEM_WRITEABLE);
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armlinux_add_dram(sdram_dev);
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2011-07-28 07:13:11 +00:00
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imx35_add_fb(&ipu_fb_data);
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imx35_add_mmc0(NULL);
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2010-10-12 14:39:08 +00:00
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armlinux_set_bootparams((void *)0x80000100);
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armlinux_set_architecture(MACH_TYPE_GUF_CUPID);
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return 0;
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}
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device_initcall(cupid_devices_init);
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static struct pad_desc cupid_pads[] = {
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/* UART1 */
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MX35_PAD_CTS1__UART1_CTS,
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MX35_PAD_RTS1__UART1_RTS,
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MX35_PAD_TXD1__UART1_TXD_MUX,
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MX35_PAD_RXD1__UART1_RXD_MUX,
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/* UART2 */
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MX35_PAD_CTS2__UART2_CTS,
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MX35_PAD_RTS2__UART2_RTS,
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MX35_PAD_TXD2__UART2_TXD_MUX,
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MX35_PAD_RXD2__UART2_RXD_MUX,
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/* FEC */
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MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
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MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
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MX35_PAD_FEC_RX_DV__FEC_RX_DV,
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MX35_PAD_FEC_COL__FEC_COL,
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MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
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MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
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MX35_PAD_FEC_TX_EN__FEC_TX_EN,
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MX35_PAD_FEC_MDC__FEC_MDC,
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MX35_PAD_FEC_MDIO__FEC_MDIO,
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MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
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MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
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MX35_PAD_FEC_CRS__FEC_CRS,
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MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
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MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
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MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
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MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
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MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
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MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
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/* I2C1 */
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MX35_PAD_I2C1_CLK__I2C1_SCL,
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MX35_PAD_I2C1_DAT__I2C1_SDA,
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/* Display */
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MX35_PAD_LD0__IPU_DISPB_DAT_0,
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MX35_PAD_LD1__IPU_DISPB_DAT_1,
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MX35_PAD_LD2__IPU_DISPB_DAT_2,
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MX35_PAD_LD3__IPU_DISPB_DAT_3,
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MX35_PAD_LD4__IPU_DISPB_DAT_4,
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MX35_PAD_LD5__IPU_DISPB_DAT_5,
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MX35_PAD_LD6__IPU_DISPB_DAT_6,
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MX35_PAD_LD7__IPU_DISPB_DAT_7,
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MX35_PAD_LD8__IPU_DISPB_DAT_8,
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MX35_PAD_LD9__IPU_DISPB_DAT_9,
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MX35_PAD_LD10__IPU_DISPB_DAT_10,
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MX35_PAD_LD11__IPU_DISPB_DAT_11,
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MX35_PAD_LD12__IPU_DISPB_DAT_12,
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MX35_PAD_LD13__IPU_DISPB_DAT_13,
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MX35_PAD_LD14__IPU_DISPB_DAT_14,
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MX35_PAD_LD15__IPU_DISPB_DAT_15,
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MX35_PAD_LD16__IPU_DISPB_DAT_16,
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MX35_PAD_LD17__IPU_DISPB_DAT_17,
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MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
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MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
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MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
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MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
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MX35_PAD_LD18__GPIO3_24, /* LCD enable */
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MX35_PAD_CSPI1_SS1__GPIO1_19, /* LCD backligtht PWM */
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/* USB Host*/
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MX35_PAD_MLB_CLK__GPIO3_3, /* USB Host PWR */
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MX35_PAD_MLB_DAT__GPIO3_4, /* USB Host Overcurrent */
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/* USB OTG */
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MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
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MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
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/* SSI */
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MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
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MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
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MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
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MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
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/* UCB1400 IRQ */
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MX35_PAD_ATA_INTRQ__GPIO2_29,
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/* Speaker On */
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MX35_PAD_LD20__GPIO3_26,
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/* LEDs */
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MX35_PAD_TX1__GPIO1_14,
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/* ESDHC1 */
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MX35_PAD_SD1_CMD__ESDHC1_CMD,
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MX35_PAD_SD1_CLK__ESDHC1_CLK,
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MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
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MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
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MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
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MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
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/* ESDHC1 CD */
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MX35_PAD_ATA_DATA5__GPIO2_18,
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/* ESDHC1 WP */
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MX35_PAD_ATA_DATA6__GPIO2_19,
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};
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static int cupid_console_init(void)
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{
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mxc_iomux_v3_setup_multiple_pads(cupid_pads, ARRAY_SIZE(cupid_pads));
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2011-07-28 07:13:11 +00:00
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imx35_add_uart0();
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2010-10-12 14:39:08 +00:00
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return 0;
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}
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console_initcall(cupid_console_init);
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static int cupid_core_setup(void)
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{
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u32 tmp;
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/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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writel(0x77777777, IMX_AIPS1_BASE);
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writel(0x77777777, IMX_AIPS1_BASE + 0x4);
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writel(0x77777777, IMX_AIPS2_BASE);
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writel(0x77777777, IMX_AIPS2_BASE + 0x4);
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/*
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* Clear the on and off peripheral modules Supervisor Protect bit
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* for SDMA to access them. Did not change the AIPS control registers
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* (offset 0x20) access type
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*/
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writel(0x0, IMX_AIPS1_BASE + 0x40);
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writel(0x0, IMX_AIPS1_BASE + 0x44);
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writel(0x0, IMX_AIPS1_BASE + 0x48);
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writel(0x0, IMX_AIPS1_BASE + 0x4C);
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tmp = readl(IMX_AIPS1_BASE + 0x50);
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tmp &= 0x00FFFFFF;
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writel(tmp, IMX_AIPS1_BASE + 0x50);
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writel(0x0, IMX_AIPS2_BASE + 0x40);
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writel(0x0, IMX_AIPS2_BASE + 0x44);
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writel(0x0, IMX_AIPS2_BASE + 0x48);
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writel(0x0, IMX_AIPS2_BASE + 0x4C);
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tmp = readl(IMX_AIPS2_BASE + 0x50);
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tmp &= 0x00FFFFFF;
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writel(tmp, IMX_AIPS2_BASE + 0x50);
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/* MAX (Multi-Layer AHB Crossbar Switch) setup */
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/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
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#define MAX_PARAM1 0x00302154
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writel(MAX_PARAM1, IMX_MAX_BASE + 0x0); /* for S0 */
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writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */
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writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */
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writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */
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writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */
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/* SGPCR - always park on last master */
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writel(0x10, IMX_MAX_BASE + 0x10); /* for S0 */
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writel(0x10, IMX_MAX_BASE + 0x110); /* for S1 */
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writel(0x10, IMX_MAX_BASE + 0x210); /* for S2 */
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writel(0x10, IMX_MAX_BASE + 0x310); /* for S3 */
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writel(0x10, IMX_MAX_BASE + 0x410); /* for S4 */
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/* MGPCR - restore default values */
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writel(0x0, IMX_MAX_BASE + 0x800); /* for M0 */
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writel(0x0, IMX_MAX_BASE + 0x900); /* for M1 */
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writel(0x0, IMX_MAX_BASE + 0xa00); /* for M2 */
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writel(0x0, IMX_MAX_BASE + 0xb00); /* for M3 */
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|
|
writel(0x0, IMX_MAX_BASE + 0xc00); /* for M4 */
|
|
|
|
writel(0x0, IMX_MAX_BASE + 0xd00); /* for M5 */
|
|
|
|
|
|
|
|
writel(0x0000DCF6, CSCR_U(0)); /* CS0: NOR Flash */
|
|
|
|
writel(0x444A4541, CSCR_L(0));
|
|
|
|
writel(0x44443302, CSCR_A(0));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* M3IF Control Register (M3IFCTL)
|
|
|
|
* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
|
|
|
|
* MRRP[1] = MAX1 not on priority list (0 << 0) = 0x00000000
|
|
|
|
* MRRP[2] = L2CC1 not on priority list (0 << 0) = 0x00000000
|
|
|
|
* MRRP[3] = USB not on priority list (0 << 0) = 0x00000000
|
|
|
|
* MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
|
|
|
|
* MRRP[5] = GPU not on priority list (0 << 0) = 0x00000000
|
|
|
|
* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
|
|
|
|
* MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
|
|
|
|
* ------------
|
|
|
|
* 0x00000040
|
|
|
|
*/
|
|
|
|
writel(0x40, IMX_M3IF_BASE);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
core_initcall(cupid_core_setup);
|
|
|
|
|
|
|
|
#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5))
|
|
|
|
#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1))
|
|
|
|
|
|
|
|
static int do_cpufreq(struct command *cmdtp, int argc, char *argv[])
|
|
|
|
{
|
|
|
|
unsigned long freq;
|
|
|
|
|
|
|
|
if (argc != 2)
|
|
|
|
return COMMAND_ERROR_USAGE;
|
|
|
|
|
|
|
|
freq = simple_strtoul(argv[1], NULL, 0);
|
|
|
|
|
|
|
|
switch (freq) {
|
|
|
|
case 399:
|
|
|
|
writel(MPCTL_PARAM_399, IMX_CCM_BASE + CCM_MPCTL);
|
|
|
|
break;
|
|
|
|
case 532:
|
|
|
|
writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return COMMAND_ERROR_USAGE;
|
|
|
|
}
|
|
|
|
|
2011-01-07 10:37:15 +00:00
|
|
|
printf("Switched CPU frequency to %ldMHz\n", freq);
|
2010-10-12 14:39:08 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const __maybe_unused char cmd_cpufreq_help[] =
|
|
|
|
"Usage: cpufreq 399|532\n"
|
|
|
|
"\n"
|
|
|
|
"Set CPU frequency to <freq> MHz\n";
|
|
|
|
|
|
|
|
BAREBOX_CMD_START(cpufreq)
|
|
|
|
.cmd = do_cpufreq,
|
|
|
|
.usage = "adjust CPU frequency",
|
|
|
|
BAREBOX_CMD_HELP(cmd_cpufreq_help)
|
|
|
|
BAREBOX_CMD_END
|
|
|
|
|