2012-10-18 19:42:42 +00:00
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/*
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* Author: Carlo Caione <carlo@carlocaione.org>
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*
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* Based on mach-nomadik
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* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <io.h>
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#include <asm/armlinux.h>
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#include <sizes.h>
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#include <mach/platform.h>
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#include <mach/wd.h>
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#include <mach/core.h>
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#include <linux/amba/bus.h>
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enum brcm_clks {
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dummy, clk_ref_3, clk_ref_1, clks_max
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};
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static struct clk *clks[clks_max];
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static int bcm2835_clk_init(void)
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{
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int ret;
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clks[dummy] = clk_fixed("dummy", 0);
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clks[clk_ref_3] = clk_fixed("ref3", 3 * 1000 * 1000);
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clks[clk_ref_1] = clk_fixed("ref1", 1 * 1000 * 1000);
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ret = clk_register_clkdev(clks[dummy], "apb_pclk", NULL);
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if (ret)
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goto clk_err;
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ret = clk_register_clkdev(clks[clk_ref_3], NULL, "uart0-pl0110");
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if (ret)
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goto clk_err;
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ret = clk_register_clkdev(clks[clk_ref_1], NULL, "bcm2835-cs");
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if (ret)
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goto clk_err;
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return 0;
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clk_err:
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return ret;
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}
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postcore_initcall(bcm2835_clk_init);
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static int bcm2835_dev_init(void)
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{
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add_generic_device("bcm2835-gpio", 0, NULL, BCM2835_GPIO_BASE, 0xB0, IORESOURCE_MEM, NULL);
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add_generic_device("bcm2835-cs", DEVICE_ID_SINGLE, NULL, BCM2835_ST_BASE, 0x1C, IORESOURCE_MEM, NULL);
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return 0;
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}
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coredevice_initcall(bcm2835_dev_init);
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void bcm2835_register_uart(void)
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{
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amba_apb_device_add(NULL, "uart0-pl011", 0, BCM2835_UART0_BASE, 4096, NULL, 0);
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}
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void bcm2835_add_device_sdram(u32 size)
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{
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if (!size)
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size = get_ram_size((ulong *) BCM2835_SDRAM_BASE, SZ_128M);
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arm_add_mem_device("ram0", BCM2835_SDRAM_BASE, size);
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}
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#define RESET_TIMEOUT 10
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void __noreturn reset_cpu (unsigned long addr)
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{
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uint32_t rstc;
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rstc = readl(PM_RSTC);
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rstc &= ~PM_RSTC_WRCFG_SET;
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rstc |= PM_RSTC_WRCFG_FULL_RESET;
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writel(PM_PASSWORD | RESET_TIMEOUT, PM_WDOG);
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writel(PM_PASSWORD | rstc, PM_RSTC);
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2013-01-25 19:43:52 +00:00
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while (1);
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2012-10-18 19:42:42 +00:00
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}
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EXPORT_SYMBOL(reset_cpu);
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