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sysmo-bts
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barebox
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c7f45d762d
barebox
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arch
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openrisc
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include
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asm
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byteorder.h
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Add OpenRISC arch OpenRISC is the original flagship project of the OpenCores community. This project aims to develop a series of general purpose open source RISC CPU architectures. A team from OpenCores provided the first implementation, the OpenRISC 1200, written in the Verilog hardware description language. Even though I should have created an mach-or1200 directory, it is not necessary for now. The OpenRISC 1200 CPU is the only one available and it will be for some time. Signed-off-by: Franck Jullien <franck.jullien@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-12-20 22:11:36 +00:00
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include
<linux/byteorder/big_endian.h>