569 lines
18 KiB
C
569 lines
18 KiB
C
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/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*/
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/**
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* Defines the SDRAM parameter structure.
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*
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* Note that PLLM is used by EMC.
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*/
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#ifndef INCLUDED_NVBOOT_SDRAM_PARAM_T30_H
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#define INCLUDED_NVBOOT_SDRAM_PARAM_T30_H
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#define NVBOOT_BCT_SDRAM_ARB_CONFIG_WORDS 27
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typedef enum {
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/* Specifies the memory type to be undefined */
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nvboot_memory_type_none = 0,
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/* Specifies the memory type to be DDR SDRAM */
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nvboot_memory_type_ddr,
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/* Specifies the memory type to be LPDDR SDRAM */
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nvboot_memory_type_lpddr,
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/* Specifies the memory type to be DDR2 SDRAM */
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nvboot_memory_type_ddr2,
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/* Specifies the memory type to be LPDDR2 SDRAM */
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nvboot_memory_type_lpddr2,
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/* Specifies the memory type to be DDR3 SDRAM */
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nvboot_memory_type_ddr3,
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nvboot_memory_type_num,
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nvboot_memory_type_force32 = 0x7FFFFFF
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} nvboot_memory_type;
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/**
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* Defines the SDRAM parameter structure
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*/
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typedef struct nvboot_sdram_params_rec {
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/* sdram data structure generated by tool warmboot_code_gen */
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/* Specifies the type of memory device */
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nvboot_memory_type memory_type;
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/* MC/EMC clock source configuration */
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/* Specifies the CPCON value for PllM */
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u_int32_t pllm_charge_pump_setup_ctrl;
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/* Specifies the LPCON value for PllM */
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u_int32_t pllm_loop_filter_setup_ctrl;
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/* Specifies the M value for PllM */
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u_int32_t pllm_input_divider;
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/* Specifies the N value for PllM */
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u_int32_t pllm_feedback_divider;
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/* Specifies the P value for PllM */
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u_int32_t pllm_post_divider;
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/* Specifies the time to wait for PLLM to lock (in microseconds) */
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u_int32_t pllm_stable_time;
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/* Specifies the divider for the EMC Clock Source */
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u_int32_t emc_clock_divider;
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/* Specifies the PLL source for the EMC Clock Source */
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u_int32_t emc_clock_source;
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/*
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* Specifies the enable for using low jitter clock for
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* the EMC Clock Source
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*/
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u_int32_t emc_clock_use_pll_mud;
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/* Auto-calibration of EMC pads */
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/* Specifies the value for EMC_AUTO_CAL_INTERVAL */
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u_int32_t emc_auto_cal_interval;
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/*
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* Specifies the value for EMC_AUTO_CAL_CONFIG
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* Note: Trigger bits are set by the SDRAM code.
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*/
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u_int32_t emc_auto_cal_config;
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/*
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* Specifies the time for the calibration
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* to stabilize (in microseconds)
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*/
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u_int32_t emc_auto_cal_wait;
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/*
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* DRAM size information
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* Specifies the value for EMC_ADR_CFG
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*/
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u_int32_t emc_adr_cfg;
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/*
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* Specifies the time to wait after asserting pin
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* CKE (in microseconds)
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*/
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u_int32_t emc_pin_program_wait;
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/* Specifies the extra delay before/after pin RESET/CKE command */
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u_int32_t emc_pin_extra_wait;
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/*
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* Specifies the extra delay after the first writing
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* of EMC_TIMING_CONTROL
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*/
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u_int32_t emc_timing_control_wait;
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/* Timing parameters required for the SDRAM */
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/* Specifies the value for EMC_RC */
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u_int32_t emc_rc;
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/* Specifies the value for EMC_RFC */
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u_int32_t emc_rfc;
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/* Specifies the value for EMC_RAS */
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u_int32_t emc_ras;
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/* Specifies the value for EMC_RP */
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u_int32_t emc_rp;
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/* Specifies the value for EMC_R2W */
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u_int32_t emc_r2w;
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/* Specifies the value for EMC_R2W */
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u_int32_t emc_w2r;
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/* Specifies the value for EMC_R2P */
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u_int32_t emc_r2p;
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/* Specifies the value for EMC_W2P */
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u_int32_t emc_w2p;
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/* Specifies the value for EMC_RD_RCD */
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u_int32_t emc_rd_rcd;
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/* Specifies the value for EMC_WR_RCD */
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u_int32_t emc_wr_rcd;
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/* Specifies the value for EMC_RRD */
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u_int32_t emc_rrd;
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/* Specifies the value for EMC_REXT */
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u_int32_t emc_rext;
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/* Specifies the value for EMC_WEXT */
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u_int32_t emc_wext;
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/* Specifies the value for EMC_WDV */
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u_int32_t emc_wdv;
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/* Specifies the value for EMC_QUSE */
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u_int32_t emc_quse;
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/* Specifies the value for EMC_QRST */
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u_int32_t emc_qrst;
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/* Specifies the value for EMC_QSAFE */
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u_int32_t emc_qsafe;
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/* Specifies the value for EMC_RDV */
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u_int32_t emc_rdv;
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/* Specifies the value for EMC_CTT */
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u_int32_t emc_ctt;
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/* Specifies the value for EMC_CTT_DURATION */
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u_int32_t emc_ctt_duration;
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/* Specifies the value for EMC_REFRESH */
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u_int32_t emc_refresh;
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/* Specifies the value for EMC_BURST_REFRESH_NUM */
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u_int32_t emc_burst_refresh_num;
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/* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */
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u_int32_t emc_prerefresh_req_cnt;
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/* Specifies the value for EMC_PDEX2WR */
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u_int32_t emc_pdex2wr;
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/* Specifies the value for EMC_PDEX2RD */
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u_int32_t emc_pdex2rd;
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/* Specifies the value for EMC_PCHG2PDEN */
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u_int32_t emc_pchg2pden;
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/* Specifies the value for EMC_ACT2PDEN */
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u_int32_t emc_act2pden;
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/* Specifies the value for EMC_AR2PDEN */
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u_int32_t emc_ar2pden;
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/* Specifies the value for EMC_RW2PDEN */
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u_int32_t emc_rw2pden;
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/* Specifies the value for EMC_TXSR */
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u_int32_t emc_txsr;
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/* Specifies the value for EMC_TXSRDLL */
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u_int32_t emc_txsr_dll;
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/* Specifies the value for EMC_TCKE */
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u_int32_t emc_tcke;
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/* Specifies the value for EMC_TFAW */
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u_int32_t emc_tfaw;
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/* Specifies the value for EMC_TRPAB */
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u_int32_t emc_trpab;
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/* Specifies the value for EMC_TCLKSTABLE */
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u_int32_t emc_tclkstable;
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/* Specifies the value for EMC_TCLKSTOP */
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u_int32_t emc_tclkstop;
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/* Specifies the value for EMC_TREFBW */
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u_int32_t emc_trefbw;
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/* Specifies the value for EMC_QUSE_EXTRA */
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u_int32_t emc_quse_extra;
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/* FBIO configuration values */
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/* Specifies the value for EMC_FBIO_CFG5 */
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u_int32_t emc_fbio_cfg5;
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/* Specifies the value for EMC_FBIO_CFG6 */
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u_int32_t emc_fbio_cfg6;
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/* Specifies the value for EMC_FBIO_SPARE */
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u_int32_t emc_fbio_spare;
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/* Specifies the value for EMC_CFG_RSV */
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u_int32_t emc_cfg_rsv;
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/* MRS command values */
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/* Specifies the value for EMC_MRS */
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u_int32_t emc_mrs;
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/* Specifies the value for EMC_EMRS */
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u_int32_t emc_emrs;
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/* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */
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u_int32_t emc_mrw1;
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/* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */
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u_int32_t emc_mrw2;
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/* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */
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u_int32_t emc_mrw3;
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/*
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* Specifies the programming to extra LPDDR2 Mode Register
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* at cold boot
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*/
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u_int32_t emc_mrw_extra;
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/* Specifies the programming to LPDDR2 Mode Register 1 at warm boot */
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u_int32_t emc_warm_boot_mrw1;
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/* Specifies the programming to LPDDR2 Mode Register 2 at warm boot */
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u_int32_t emc_warm_boot_mrw2;
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/* Specifies the programming to LPDDR2 Mode Register 3 at warm boot */
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u_int32_t emc_warm_boot_mrw3;
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/*
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* Specifies the programming to extra LPDDR2 Mode Register
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* at warm boot
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*/
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u_int32_t emc_warm_boot_mrw_extra;
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/*
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* Specify the enable of extra Mode Register programming at
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* warm boot
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*/
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u_int32_t emc_warm_boot_extramode_reg_write_enable;
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/*
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* Specify the enable of extra Mode Register programming at
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* cold boot
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*/
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u_int32_t emc_extramode_reg_write_enable;
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/* Specifies the EMC_MRW reset command value */
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u_int32_t emc_mrw_reset_command;
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/* Specifies the EMC Reset wait time (in microseconds) */
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u_int32_t emc_mrw_reset_ninit_wait;
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/* Specifies the value for EMC_MRS_WAIT_CNT */
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u_int32_t emc_mrs_wait_cnt;
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/* EMC miscellaneous configurations */
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/* Specifies the value for EMC_CFG */
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u_int32_t emc_cfg;
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/* Specifies the value for EMC_CFG_2 */
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u_int32_t emc_cfg2;
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/* Specifies the value for EMC_DBG */
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u_int32_t emc_dbg;
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/* Specifies the value for EMC_CMDQ */
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u_int32_t emc_cmd_q;
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/* Specifies the value for EMC_MC2EMCQ */
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u_int32_t emc_mc2emc_q;
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/* Specifies the value for EMC_DYN_SELF_REF_CONTROL */
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u_int32_t emc_dyn_self_ref_control;
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/* Specifies the value for MEM_INIT_DONE */
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u_int32_t ahb_arbitration_xbar_ctrl_meminit_done;
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/* Specifies the value for EMC_CFG_DIG_DLL */
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u_int32_t emc_cfg_dig_dll;
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/* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */
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u_int32_t emc_cfg_dig_dll_period;
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/* Specifies the vlaue of *DEV_SELECTN of various EMC registers */
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u_int32_t emc_dev_select;
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/* Specifies the value for EMC_SEL_DPD_CTRL */
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u_int32_t emc_sel_dpd_ctrl;
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/* Pads trimmer delays */
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/* Specifies the value for EMC_DLL_XFORM_DQS0 */
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u_int32_t emc_dll_xform_dqs0;
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/* Specifies the value for EMC_DLL_XFORM_DQS1 */
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u_int32_t emc_dll_xform_dqs1;
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/* Specifies the value for EMC_DLL_XFORM_DQS2 */
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u_int32_t emc_dll_xform_dqs2;
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/* Specifies the value for EMC_DLL_XFORM_DQS3 */
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u_int32_t emc_dll_xform_dqs3;
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/* Specifies the value for EMC_DLL_XFORM_DQS4 */
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u_int32_t emc_dll_xform_dqs4;
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/* Specifies the value for EMC_DLL_XFORM_DQS5 */
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u_int32_t emc_dll_xform_dqs5;
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/* Specifies the value for EMC_DLL_XFORM_DQS6 */
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u_int32_t emc_dll_xform_dqs6;
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/* Specifies the value for EMC_DLL_XFORM_DQS7 */
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u_int32_t emc_dll_xform_dqs7;
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/* Specifies the value for EMC_DLL_XFORM_QUSE0 */
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u_int32_t emc_dll_xform_quse0;
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/* Specifies the value for EMC_DLL_XFORM_QUSE1 */
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u_int32_t emc_dll_xform_quse1;
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/* Specifies the value for EMC_DLL_XFORM_QUSE2 */
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u_int32_t emc_dll_xform_quse2;
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/* Specifies the value for EMC_DLL_XFORM_QUSE3 */
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u_int32_t emc_dll_xform_quse3;
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/* Specifies the value for EMC_DLL_XFORM_QUSE4 */
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u_int32_t emc_dll_xform_quse4;
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/* Specifies the value for EMC_DLL_XFORM_QUSE5 */
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u_int32_t emc_dll_xform_quse5;
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/* Specifies the value for EMC_DLL_XFORM_QUSE6 */
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u_int32_t emc_dll_xform_quse6;
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/* Specifies the value for EMC_DLL_XFORM_QUSE7 */
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u_int32_t emc_dll_xform_quse7;
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/* Specifies the value for EMC_DLI_TRIM_TXDQS0 */
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u_int32_t emc_dli_trim_tx_dqs0;
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/* Specifies the value for EMC_DLI_TRIM_TXDQS1 */
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u_int32_t emc_dli_trim_tx_dqs1;
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/* Specifies the value for EMC_DLI_TRIM_TXDQS2 */
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u_int32_t emc_dli_trim_tx_dqs2;
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/* Specifies the value for EMC_DLI_TRIM_TXDQS3 */
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u_int32_t emc_dli_trim_tx_dqs3;
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/* Specifies the value for EMC_DLI_TRIM_TXDQS4 */
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u_int32_t emc_dli_trim_tx_dqs4;
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/* Specifies the value for EMC_DLI_TRIM_TXDQS5 */
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u_int32_t emc_dli_trim_tx_dqs5;
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/* Specifies the value for EMC_DLI_TRIM_TXDQS6 */
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u_int32_t emc_dli_trim_tx_dqs6;
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/* Specifies the value for EMC_DLI_TRIM_TXDQS7 */
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u_int32_t emc_dli_trim_tx_dqs7;
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/* Specifies the value for EMC_DLL_XFORM_DQ0 */
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u_int32_t emc_dll_xform_dq0;
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/* Specifies the value for EMC_DLL_XFORM_DQ1 */
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u_int32_t emc_dll_xform_dq1;
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/* Specifies the value for EMC_DLL_XFORM_DQ2 */
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u_int32_t emc_dll_xform_dq2;
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/* Specifies the value for EMC_DLL_XFORM_DQ3 */
|
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u_int32_t emc_dll_xform_dq3;
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/*
|
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* Specifies the delay after asserting CKE pin during a WarmBoot0
|
||
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* sequence (in microseconds)
|
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*/
|
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u_int32_t warm_boot_wait;
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/* Specifies the value for EMC_CTT_TERM_CTRL */
|
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u_int32_t emc_ctt_term_ctrl;
|
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/* Specifies the value for EMC_ODT_WRITE */
|
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u_int32_t emc_odt_write;
|
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/* Specifies the value for EMC_ODT_WRITE */
|
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u_int32_t emc_odt_read;
|
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/* Periodic ZQ calibration */
|
||
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|
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/*
|
||
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* Specifies the value for EMC_ZCAL_INTERVAL
|
||
|
* Value 0 disables ZQ calibration
|
||
|
*/
|
||
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u_int32_t emc_zcal_interval;
|
||
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/* Specifies the value for EMC_ZCAL_WAIT_CNT */
|
||
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u_int32_t emc_zcal_wait_cnt;
|
||
|
/* Specifies the value for EMC_ZCAL_MRW_CMD */
|
||
|
u_int32_t emc_zcal_mrw_cmd;
|
||
|
|
||
|
/* DRAM initialization sequence flow control */
|
||
|
|
||
|
/* Specifies the MRS command value for resetting DLL */
|
||
|
u_int32_t emc_mrs_reset_dll;
|
||
|
/* Specifies the command for ZQ initialization of device 0 */
|
||
|
u_int32_t emc_zcal_init_dev0;
|
||
|
/* Specifies the command for ZQ initialization of device 1 */
|
||
|
u_int32_t emc_zcal_init_dev1;
|
||
|
/*
|
||
|
* Specifies the wait time after programming a ZQ initialization
|
||
|
* command (in microseconds)
|
||
|
*/
|
||
|
u_int32_t emc_zcal_init_wait;
|
||
|
/* Specifies the enable for ZQ calibration at cold boot */
|
||
|
u_int32_t emc_zcal_cold_boot_enable;
|
||
|
/* Specifies the enable for ZQ calibration at warm boot */
|
||
|
u_int32_t emc_zcal_warm_boot_enable;
|
||
|
|
||
|
/*
|
||
|
* Specifies the MRW command to LPDDR2 for ZQ calibration
|
||
|
*on warmboot
|
||
|
*/
|
||
|
/* Is issued to both devices separately */
|
||
|
u_int32_t emc_mrw_lpddr2zcal_warm_boot;
|
||
|
/*
|
||
|
* Specifies the ZQ command to DDR3 for ZQ calibration on warmboot
|
||
|
* Is issued to both devices separately
|
||
|
*/
|
||
|
u_int32_t emc_zqcal_ddr3_warm_boot;
|
||
|
/*
|
||
|
* Specifies the wait time for ZQ calibration on warmboot
|
||
|
* (in microseconds)
|
||
|
*/
|
||
|
u_int32_t emc_zcal_warm_boot_wait;
|
||
|
/*
|
||
|
* Specifies the enable for DRAM Mode Register programming
|
||
|
* at warm boot
|
||
|
*/
|
||
|
u_int32_t emc_mrs_warm_boot_enable;
|
||
|
/*
|
||
|
* Specifies the wait time after sending an MRS DLL reset command
|
||
|
* in microseconds)
|
||
|
*/
|
||
|
u_int32_t emc_mrs_reset_dll_wait;
|
||
|
/*
|
||
|
* Specifies the first of two EMRS commands to initialize mode
|
||
|
* registers
|
||
|
*/
|
||
|
u_int32_t emc_emrs_emr2;
|
||
|
/*
|
||
|
* Specifies the second of two EMRS commands to initialize mode
|
||
|
* registers
|
||
|
*/
|
||
|
u_int32_t emc_emrs_emr3;
|
||
|
/* Specifies the extra MRS command to initialize mode registers */
|
||
|
u_int32_t emc_mrs_extra;
|
||
|
/* Specifies the programming to DDR3 Mode Register 0 at warm boot */
|
||
|
u_int32_t emc_warm_boot_mrs;
|
||
|
/* Specifies the programming to DDR3 Mode Register 1 at warm boot */
|
||
|
u_int32_t emc_warm_boot_emrs;
|
||
|
/* Specifies the programming to DDR3 Mode Register 2 at warm boot */
|
||
|
u_int32_t emc_warm_boot_emr2;
|
||
|
/* Specifies the programming to DDR3 Mode Register 3 at warm boot */
|
||
|
u_int32_t emc_warm_boot_emr3;
|
||
|
/* Specifies the extra MRS command at warm boot */
|
||
|
u_int32_t emc_warm_boot_mrs_extra;
|
||
|
/* Specifies the EMRS command to enable the DDR2 DLL */
|
||
|
u_int32_t emc_emrs_ddr2_dll_enable;
|
||
|
/* Specifies the MRS command to reset the DDR2 DLL */
|
||
|
u_int32_t emc_mrs_ddr2_dll_reset;
|
||
|
/* Specifies the EMRS command to set OCD calibration */
|
||
|
u_int32_t emc_emrs_ddr2_ocd_calib;
|
||
|
/*
|
||
|
* Specifies the wait between initializing DDR and setting OCD
|
||
|
* calibration (in microseconds)
|
||
|
*/
|
||
|
u_int32_t emc_ddr2_wait;
|
||
|
/* Specifies the value for EMC_CLKEN_OVERRIDE */
|
||
|
u_int32_t emc_clken_override;
|
||
|
/*
|
||
|
* Specifies LOG2 of the extra refresh numbers after booting
|
||
|
* Program 0 to disable
|
||
|
*/
|
||
|
u_int32_t emc_extra_refresh_num;
|
||
|
/* Specifies the master override for all EMC clocks */
|
||
|
u_int32_t emc_clken_override_allwarm_boot;
|
||
|
/* Specifies the master override for all MC clocks */
|
||
|
u_int32_t mc_clken_override_allwarm_boot;
|
||
|
/* Specifies digital dll period, choosing between 4 to 64 ms */
|
||
|
u_int32_t emc_cfg_dig_dll_period_warm_boot;
|
||
|
|
||
|
/* Pad controls */
|
||
|
|
||
|
/* Specifies the value for PMC_VDDP_SEL */
|
||
|
u_int32_t pmc_vddp_sel;
|
||
|
/* Specifies the value for PMC_DDR_PWR */
|
||
|
u_int32_t pmc_ddr_pwr;
|
||
|
/* Specifies the value for PMC_DDR_CFG */
|
||
|
u_int32_t pmc_ddr_cfg;
|
||
|
/* Specifies the value for PMC_IO_DPD_REQ */
|
||
|
u_int32_t pmc_io_dpd_req;
|
||
|
/* Specifies the value for PMC_E_NO_VTTGEN */
|
||
|
u_int32_t pmc_eno_vtt_gen;
|
||
|
/* Specifies the value for PMC_NO_IOPOWER */
|
||
|
u_int32_t pmc_no_io_power;
|
||
|
/* Specifies the value for EMC_XM2CMDPADCTRL */
|
||
|
u_int32_t emc_xm2cmd_pad_ctrl;
|
||
|
/* Specifies the value for EMC_XM2CMDPADCTRL2 */
|
||
|
u_int32_t emc_xm2cmd_pad_ctrl2;
|
||
|
/* Specifies the value for EMC_XM2DQSPADCTRL */
|
||
|
u_int32_t emc_xm2dqs_pad_ctrl;
|
||
|
/* Specifies the value for EMC_XM2DQSPADCTRL2 */
|
||
|
u_int32_t emc_xm2dqs_pad_ctrl2;
|
||
|
/* Specifies the value for EMC_XM2DQSPADCTRL3 */
|
||
|
u_int32_t emc_xm2dqs_pad_ctrl3;
|
||
|
/* Specifies the value for EMC_XM2DQPADCTRL */
|
||
|
u_int32_t emc_xm2dq_pad_ctrl;
|
||
|
/* Specifies the value for EMC_XM2DQPADCTRL2 */
|
||
|
u_int32_t emc_xm2dq_pad_ctrl2;
|
||
|
/* Specifies the value for EMC_XM2CLKPADCTRL */
|
||
|
u_int32_t emc_xm2clk_pad_ctrl;
|
||
|
/* Specifies the value for EMC_XM2COMPPADCTRL */
|
||
|
u_int32_t emc_xm2comp_pad_ctrl;
|
||
|
/* Specifies the value for EMC_XM2VTTGENPADCTRL */
|
||
|
u_int32_t emc_xm2vttgen_pad_ctrl;
|
||
|
/* Specifies the value for EMC_XM2VTTGENPADCTRL2 */
|
||
|
u_int32_t emc_xm2vttgen_pad_ctrl2;
|
||
|
/* Specifies the value for EMC_XM2QUSEPADCTRL */
|
||
|
u_int32_t emc_xm2quse_pad_ctrl;
|
||
|
|
||
|
/* DRAM size information */
|
||
|
|
||
|
/* Specifies the value for MC_EMEM_ADR_CFG */
|
||
|
u_int32_t mc_emem_adr_cfg;
|
||
|
/* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */
|
||
|
u_int32_t mc_emem_adr_cfg_dev0;
|
||
|
/* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */
|
||
|
u_int32_t mc_emem_adr_cfg_dev1;
|
||
|
|
||
|
/*
|
||
|
* Specifies the value for MC_EMEM_CFG which holds the external memory
|
||
|
* size (in KBytes)
|
||
|
*/
|
||
|
u_int32_t mc_emem_cfg;
|
||
|
|
||
|
/* MC arbitration configuration */
|
||
|
|
||
|
/* Specifies the value for MC_EMEM_ARB_CFG */
|
||
|
u_int32_t mc_emem_arb_cfg;
|
||
|
/* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */
|
||
|
u_int32_t mc_emem_arb_outstanding_req;
|
||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_RCD */
|
||
|
u_int32_t mc_emem_arb_timing_rcd;
|
||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_RP */
|
||
|
u_int32_t mc_emem_arb_timing_rp;
|
||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_RC */
|
||
|
u_int32_t mc_emem_arb_timing_rc;
|
||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_RAS */
|
||
|
u_int32_t mc_emem_arb_timing_ras;
|
||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_FAW */
|
||
|
u_int32_t mc_emem_arb_timing_faw;
|
||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_RRD */
|
||
|
u_int32_t mc_emem_arb_timing_rrd;
|
||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */
|
||
|
u_int32_t mc_emem_arb_timing_rap2pre;
|
||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */
|
||
|
u_int32_t mc_emem_arb_timing_wap2pre;
|
||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_R2R */
|
||
|
u_int32_t mc_emem_arb_timing_r2r;
|
||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_W2W */
|
||
|
u_int32_t mc_emem_arb_timing_w2w;
|
||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_R2W */
|
||
|
u_int32_t mc_emem_arb_timing_r2w;
|
||
|
/* Specifies the value for MC_EMEM_ARB_TIMING_W2R */
|
||
|
u_int32_t mc_emem_arb_timing_w2r;
|
||
|
/* Specifies the value for MC_EMEM_ARB_DA_TURNS */
|
||
|
u_int32_t mc_emem_arb_da_turns;
|
||
|
/* Specifies the value for MC_EMEM_ARB_DA_COVERS */
|
||
|
u_int32_t mc_emem_arb_da_covers;
|
||
|
/* Specifies the value for MC_EMEM_ARB_MISC0 */
|
||
|
u_int32_t mc_emem_arb_misc0;
|
||
|
/* Specifies the value for MC_EMEM_ARB_MISC1 */
|
||
|
u_int32_t mc_emem_arb_misc1;
|
||
|
/* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */
|
||
|
u_int32_t mc_emem_arb_ring1_throttle;
|
||
|
/* Specifies the value for MC_EMEM_ARB_OVERRIDE */
|
||
|
u_int32_t mc_emem_arb_override;
|
||
|
/* Specifies the value for MC_EMEM_ARB_RSV */
|
||
|
u_int32_t mc_emem_arb_rsv;
|
||
|
|
||
|
/* Specifies the value for MC_CLKEN_OVERRIDE */
|
||
|
u_int32_t mc_clken_override;
|
||
|
|
||
|
/* End of generated code by warmboot_code_gen */
|
||
|
} nvboot_sdram_params;
|
||
|
#endif /* #ifndef INCLUDED_NVBOOT_SDRAM_PARAM_T30_H */
|
||
|
|