319 lines
7.7 KiB
C
319 lines
7.7 KiB
C
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/*
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* Copyright (C) 2007 Sascha Hauer, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <net.h>
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#include <init.h>
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#include <environment.h>
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#include <mach/imx-regs.h>
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#include <fec.h>
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#include <mach/gpio.h>
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#include <asm/armlinux.h>
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#include <generated/mach-types.h>
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#include <partition.h>
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#include <fs.h>
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#include <fcntl.h>
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#include <nand.h>
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#include <spi/spi.h>
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#include <mfd/mc13892.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <mach/imx-nand.h>
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#include <mach/spi.h>
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#include <mach/generic.h>
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#include <mach/iomux-mx51.h>
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static struct memory_platform_data ram_pdata = {
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.name = "ram0",
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.flags = DEVFS_RDWR,
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};
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static struct device_d sdram_dev = {
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.id = -1,
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.name = "mem",
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.map_base = 0x90000000,
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.size = 512 * 1024 * 1024,
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.platform_data = &ram_pdata,
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};
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static struct fec_platform_data fec_info = {
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.xcv_type = MII100,
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};
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static struct device_d fec_dev = {
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.name = "fec_imx",
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.map_base = 0x83fec000,
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.platform_data = &fec_info,
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};
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static struct device_d esdhc_dev = {
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.name = "imx-esdhc",
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.map_base = 0x70004000,
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};
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static struct pad_desc f3s_pads[] = {
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MX51_PAD_EIM_EB2__FEC_MDIO,
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MX51_PAD_EIM_EB3__FEC_RDATA1,
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MX51_PAD_EIM_CS2__FEC_RDATA2,
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MX51_PAD_EIM_CS3__FEC_RDATA3,
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MX51_PAD_EIM_CS4__FEC_RX_ER,
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MX51_PAD_EIM_CS5__FEC_CRS,
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MX51_PAD_NANDF_RB2__FEC_COL,
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MX51_PAD_NANDF_RB3__FEC_RX_CLK,
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MX51_PAD_NANDF_RB7__FEC_TX_ER,
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MX51_PAD_NANDF_CS3__FEC_MDC,
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MX51_PAD_NANDF_CS4__FEC_TDATA1,
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MX51_PAD_NANDF_CS5__FEC_TDATA2,
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MX51_PAD_NANDF_CS6__FEC_TDATA3,
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MX51_PAD_NANDF_CS7__FEC_TX_EN,
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MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
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MX51_PAD_NANDF_D11__FEC_RX_DV,
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MX51_PAD_NANDF_RB6__FEC_RDATA0,
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MX51_PAD_NANDF_D8__FEC_TDATA0,
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MX51_PAD_CSPI1_SS0__CSPI1_SS0,
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MX51_PAD_CSPI1_MOSI__CSPI1_MOSI,
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MX51_PAD_CSPI1_MISO__CSPI1_MISO,
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MX51_PAD_CSPI1_RDY__CSPI1_RDY,
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MX51_PAD_CSPI1_SCLK__CSPI1_SCLK,
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MX51_PAD_EIM_A20__GPIO2_14, /* LAN8700 reset pin */
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IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, 0x85), /* FIXME: needed? */
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};
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#ifdef CONFIG_MMU
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static void babbage_mmu_init(void)
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{
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mmu_init();
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arm_create_section(0x90000000, 0x90000000, 512, PMD_SECT_DEF_CACHED);
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arm_create_section(0xb0000000, 0x90000000, 512, PMD_SECT_DEF_UNCACHED);
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setup_dma_coherent(0x20000000);
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#if TEXT_BASE & (0x100000 - 1)
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#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary
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#else
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arm_create_section(0x0, TEXT_BASE, 1, PMD_SECT_DEF_UNCACHED);
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#endif
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mmu_enable();
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}
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#else
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static void babbage_mmu_init(void)
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{
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}
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#endif
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//extern int babbage_power_init(void);
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#define BABBAGE_ECSPI1_CS0 (3 * 32 + 24)
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static int spi_0_cs[] = {BABBAGE_ECSPI1_CS0};
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static struct spi_imx_master spi_0_data = {
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.chipselect = spi_0_cs,
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.num_chipselect = ARRAY_SIZE(spi_0_cs),
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};
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static struct device_d spi_dev = {
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.id = -1,
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.name = "imx_spi",
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.map_base = MX51_CSPI1_BASE_ADDR,
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.platform_data = &spi_0_data,
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};
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static const struct spi_board_info mx51_babbage_spi_board_info[] = {
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{
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.name = "mc13892-spi",
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.max_speed_hz = 300000,
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.bus_num = 0,
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.chip_select = 0,
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},
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};
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#define MX51_CCM_CACRR 0x10
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static void babbage_power_init(void)
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{
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struct mc13892 *mc13892;
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u32 val;
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mc13892 = mc13892_get();
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if (!mc13892) {
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printf("could not get mc13892\n");
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return;
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}
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/* Write needed to Power Gate 2 register */
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mc13892_reg_read(mc13892, 34, &val);
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val &= ~0x10000;
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mc13892_reg_write(mc13892, 34, val);
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/* Write needed to update Charger 0 */
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mc13892_reg_write(mc13892, 48, 0x0023807F);
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/* power up the system first */
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mc13892_reg_write(mc13892, 34, 0x00200000);
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if (imx_silicon_revision() < MX51_CHIP_REV_3_0) {
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/* Set core voltage to 1.1V */
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mc13892_reg_read(mc13892, 24, &val);
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val &= ~0x1f;
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val |= 0x14;
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mc13892_reg_write(mc13892, 24, val);
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/* Setup VCC (SW2) to 1.25 */
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mc13892_reg_read(mc13892, 25, &val);
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val &= ~0x1f;
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val |= 0x1a;
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mc13892_reg_write(mc13892, 25, val);
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/* Setup 1V2_DIG1 (SW3) to 1.25 */
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mc13892_reg_read(mc13892, 26, &val);
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val &= ~0x1f;
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val |= 0x1a;
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mc13892_reg_write(mc13892, 26, val);
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udelay(50);
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/* Raise the core frequency to 800MHz */
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writel(0x0, MX51_CCM_BASE_ADDR + MX51_CCM_CACRR);
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} else {
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/* Setup VCC (SW2) to 1.225 */
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mc13892_reg_read(mc13892, 25, &val);
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val &= ~0x1f;
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val |= 0x19;
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mc13892_reg_write(mc13892, 25, val);
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/* Setup 1V2_DIG1 (SW3) to 1.2 */
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mc13892_reg_read(mc13892, 26, &val);
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val &= ~0x1f;
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val |= 0x18;
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mc13892_reg_write(mc13892, 26, val);
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}
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if (mc13892_get_revision(mc13892) < MC13892_REVISION_2_0) {
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/* Set switchers in PWM mode for Atlas 2.0 and lower */
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/* Setup the switcher mode for SW1 & SW2*/
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mc13892_reg_read(mc13892, 28, &val);
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val &= ~0x3c0f;
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val |= 0x1405;
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mc13892_reg_write(mc13892, 28, val);
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/* Setup the switcher mode for SW3 & SW4 */
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mc13892_reg_read(mc13892, 29, &val);
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val &= ~0xf0f;
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val |= 0x505;
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mc13892_reg_write(mc13892, 29, val);
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} else {
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/* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */
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/* Setup the switcher mode for SW1 & SW2*/
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mc13892_reg_read(mc13892, 28, &val);
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val &= ~0x3c0f;
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val |= 0x2008;
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mc13892_reg_write(mc13892, 28, val);
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/* Setup the switcher mode for SW3 & SW4 */
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mc13892_reg_read(mc13892, 29, &val);
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val &= ~0xf0f;
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val |= 0x808;
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mc13892_reg_write(mc13892, 29, val);
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}
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/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */
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mc13892_reg_read(mc13892, 30, &val);
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val &= ~0x34030;
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val |= 0x10020;
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mc13892_reg_write(mc13892, 30, val);
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/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
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mc13892_reg_read(mc13892, 31, &val);
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val &= ~0x1FC;
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val |= 0x1F4;
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mc13892_reg_write(mc13892, 31, val);
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/* Configure VGEN3 and VCAM regulators to use external PNP */
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val = 0x208;
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mc13892_reg_write(mc13892, 33, val);
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udelay(200);
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#define GPIO_LAN8700_RESET (1 * 32 + 14)
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/* Reset the ethernet controller over GPIO */
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gpio_direction_output(GPIO_LAN8700_RESET, 0);
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/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
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val = 0x49249;
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mc13892_reg_write(mc13892, 33, val);
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udelay(500);
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gpio_set_value(GPIO_LAN8700_RESET, 1);
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}
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static int f3s_devices_init(void)
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{
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babbage_mmu_init();
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register_device(&sdram_dev);
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register_device(&fec_dev);
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register_device(&esdhc_dev);
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spi_register_board_info(mx51_babbage_spi_board_info,
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ARRAY_SIZE(mx51_babbage_spi_board_info));
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register_device(&spi_dev);
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babbage_power_init();
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armlinux_add_dram(&sdram_dev);
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armlinux_set_bootparams((void *)0x90000100);
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armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE);
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return 0;
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}
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device_initcall(f3s_devices_init);
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static int f3s_part_init(void)
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{
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devfs_add_partition("disk0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
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devfs_add_partition("disk0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
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return 0;
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}
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late_initcall(f3s_part_init);
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static struct device_d f3s_serial_device = {
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.name = "imx_serial",
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.map_base = 0x73fbc000,
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.size = 4096,
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};
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static int f3s_console_init(void)
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{
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mxc_iomux_v3_setup_multiple_pads(f3s_pads, ARRAY_SIZE(f3s_pads));
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writel(0, 0x73fa8228);
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writel(0, 0x73fa822c);
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writel(0, 0x73fa8230);
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writel(0, 0x73fa8234);
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register_device(&f3s_serial_device);
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return 0;
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}
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console_initcall(f3s_console_init);
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